diff --git a/.project/device/project_am243x.js b/.project/device/project_am243x.js index b8046be..6941f31 100644 --- a/.project/device/project_am243x.js +++ b/.project/device/project_am243x.js @@ -31,6 +31,8 @@ const example_file_list = [ "source/position_sense/hdsl/firmware/freerun_300_mhz/.project/project.js", "source/position_sense/hdsl/firmware/multichannel_ch0/.project/project.js", "source/position_sense/hdsl/firmware/multichannel_ch1/.project/project.js", + "source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project.js", + "source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project.js", "source/position_sense/hdsl/firmware/sync_225_mhz/.project/project.js", "source/position_sense/tamagawa/firmware/multi_channel/.project/project.js", "source/position_sense/tamagawa/firmware/single_channel/.project/project.js", diff --git a/.project/device/project_am64x.js b/.project/device/project_am64x.js index a656523..6670ef1 100644 --- a/.project/device/project_am64x.js +++ b/.project/device/project_am64x.js @@ -31,6 +31,8 @@ const example_file_list = [ "source/position_sense/hdsl/firmware/freerun_300_mhz/.project/project.js", "source/position_sense/hdsl/firmware/multichannel_ch0/.project/project.js", "source/position_sense/hdsl/firmware/multichannel_ch1/.project/project.js", + "source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project.js", + "source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project.js", "source/position_sense/hdsl/firmware/sync_225_mhz/.project/project.js", "source/position_sense/tamagawa/firmware/multi_channel/.project/project.js", "source/position_sense/tamagawa/firmware/single_channel/.project/project.js", diff --git a/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c b/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c index 47fe97f..851895a 100644 --- a/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c +++ b/examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c @@ -56,32 +56,19 @@ #include #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000) -#include -#include +#include +#include /* Divide factor for normal clock (default value for 225 MHz=23) */ #define DIV_FACTOR_NORMAL 23 /* Divide factor for oversampled clock (default value for 225 MHz=2) */ #define DIV_FACTOR_OVERSAMPLED 2 #endif -#if(CONFIG_HDSL0_CHANNEL0 + CONFIG_HDSL0_CHANNEL1 >1) -#define MULTICHANNEL 1 -#endif -#if(CONFIG_HDSL0_CHANNEL0 + CONFIG_HDSL0_CHANNEL1 <=1) -#define MULTICHANNEL 0 -#endif - #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) - -#if (MULTICHANNEL==0) -#include -#endif - -#if (MULTICHANNEL==1) #include #include -#endif - +#include +#include /* Divide factor for normal clock (default value for 300 MHz=31) */ #define DIV_FACTOR_NORMAL 31 /* Divide factor for oversampled clock (default value for 300 MHz=3) */ @@ -131,7 +118,8 @@ PRUICSS_IntcInitData gPruss1_intc_initdata = PRU_ICSS1_INTC_INITDATA; static char gUart_buffer[256]; static void *gPru_cfg; void *gPru_dramx; - +void *gPru_dramx_0; +void *gPru_dramx_1; int get_pos=1; uint32_t gMulti_turn, gRes; @@ -146,18 +134,23 @@ uint8_t gPc_addrh, gPc_addrl, gPc_offh, gPc_offl, gPc_buf0, gPc_buf1, gPc_buf2, static TCA6424_Config gTCA6424_Config; #endif -void sync_calculation(void) +void sync_calculation(HDSL_Handle hdslHandle) { uint8_t ES; uint16_t wait_before_start; uint32_t counter, period, index; volatile uint32_t cap6_rise0, cap6_rise1, cap6_fall0, cap6_fall1; uint8_t EXTRA_EDGE_ARR[8] = {0x00 ,0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC, 0xFE}; - uint32_t minm_bits = 112, cycle_per_bit = 24, max_stuffing = 26, stuffing_size = 6, cycle_per_overclock_bit =3, minm_extra_size = 4, sync_param_mem_start = 0xDC; - uint32_t cycles_left, additional_bits, minm_cycles, time_gRest, extra_edge, extra_size, num_of_stuffing, extra_size_remainder, stuffing_remainder, bottom_up_cycles; - + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000) + uint32_t minm_bits = 112, cycle_per_bit = 24, max_stuffing = 26, stuffing_size = 6, cycle_per_overclock_bit =3, minm_extra_size = 4, sync_param_mem_start = 0xDC; + uint32_t cycles_left, additional_bits, minm_cycles, time_gRest, extra_edge, extra_size, num_of_stuffing, extra_size_remainder, stuffing_remainder, bottom_up_cycles; + #endif + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) + uint32_t minm_bits = 112, cycle_per_bit = 32, max_stuffing = 26, stuffing_size = 6, cycle_per_overclock_bit =4, minm_extra_size = 4, sync_param_mem_start = 0xDC; + uint32_t cycles_left, additional_bits, minm_cycles, time_gRest, extra_edge, extra_size, num_of_stuffing, extra_size_remainder, stuffing_remainder, bottom_up_cycles; + #endif /*measure of SYNC period starts*/ - ES = HDSL_get_sync_ctrl(gHdslHandleCh0); + ES = HDSL_get_sync_ctrl(hdslHandle); volatile uint32_t* carp6_rise_addr = (uint32_t*)(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP1_SLV_REGS_BASE + CSL_ICSS_G_PR1_IEP0_SLV_CAPR6_REG0); volatile uint32_t* carp6_fall_addr = (uint32_t*)(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP1_SLV_REGS_BASE + CSL_ICSS_G_PR1_IEP0_SLV_CAPF6_REG0); cap6_rise0 = *(carp6_rise_addr); @@ -216,6 +209,9 @@ void sync_calculation(void) { DebugP_log("\r\n ERROR: ES or period selected is Invalid "); } + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) + wait_before_start=4968; + #endif DebugP_log("\r\n ********************************************************************"); DebugP_log("\r\n SYNC MODE: period = %d", period); DebugP_log("\r\n SYNC MODE: ES = %d", ES); @@ -229,7 +225,12 @@ void sync_calculation(void) DebugP_log("\r\n SYNC MODE: extra_size_remainder = %d", extra_size_remainder); DebugP_log("\r\n SYNC MODE: stuffing_remainder = %d", stuffing_remainder); DebugP_log("\r\n ********************************************************************"); - sync_param_mem_start =sync_param_mem_start + (uint32_t)gPru_dramx; + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000) + sync_param_mem_start =sync_param_mem_start + (uint32_t)gPru_dramx; + #endif + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) + sync_param_mem_start =sync_param_mem_start + (uint32_t)hdslHandle->baseMemAddr; + #endif HWREGB(sync_param_mem_start) = extra_size; sync_param_mem_start = sync_param_mem_start + 1; HWREGB(sync_param_mem_start) = num_of_stuffing; @@ -392,7 +393,6 @@ void process_request(HDSL_Handle hdslHandle,int menu){ } void hdsl_pruss_init(void) { - #if (MULTICHANNEL==0) PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh0->icssCore); /* clear ICSS0 PRU data RAM */ @@ -419,27 +419,27 @@ void hdsl_pruss_init(void) /* enable cycle counter */ HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE), CTR_EN); - #endif - - #if(MULTICHANNEL==1) +} +void hdsl_pruss_init_300m(void) +{ PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh0->icssCore); PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh1->icssCore); - /* Clear PRU_DRAM0 and PRU_DRAM1 memory */ + + gPru_dramx_0 = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_RTU_PRU1)); + gPru_dramx_1 = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_PRU1)); + memset(gPru_dramx_0, 0, (4 * 1024)); + memset(gPru_dramx_1, 0, (4 * 1024)); memset((void *) CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, 0, (16 * 1024)); memset((void *) CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE, 0, (16 * 1024)); gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase); HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_GPCFG1, HDSL_EN); - HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, HDSL_TX_CFG); - HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1RXCFGREGISTER, HDSL_RX_CFG); - PRUICSS_intcInit(gPruIcss0Handle, &gPruss0_intc_initdata); - /* configure C28 to PRU_ICSS_CTRL and C29 to EDMA + 0x1000 */ /*6.4.14.1.1 ICSSG_PRU_CONTROL RegisterPRU_ICSSG0_PR1_PDSP0_IRAM 00B0 2400h*/ HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_PROG_PTR_0) = 0xF0000238; // Address = 0x30023828 @@ -457,15 +457,35 @@ void hdsl_pruss_init(void) HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE), CTR_EN); HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE), CTR_EN); // TX_PRU Core - #endif } void hdsl_pruss_load_run_fw(HDSL_Handle hdslHandle) { - #if (MULTICHANNEL==0) +#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000) PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_PRUx); - #endif - #if(MULTICHANNEL==1) + if(HDSL_get_sync_ctrl(hdslHandle) == 0) + { + /*free run*/ + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(PRUICSS_PRUx), + 0, (uint32_t *) Hiperface_DSL2_0_RTU_0, + sizeof(Hiperface_DSL2_0_RTU_0)); + } + else + { + /*sync_mode*/ + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(PRUICSS_PRUx), + 0, (uint32_t *) Hiperface_DSL_SYNC2_0_RTU_0, + sizeof(Hiperface_DSL_SYNC2_0_RTU_0)); + } + PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_PRUx); + /*Run firmware*/ + PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_PRUx); +#endif +} + +void hdsl_pruss_load_run_fw_300m(HDSL_Handle hdslHandle) +{ +#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_RTU_PRU1); // ch0 PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_PRU1); // ch1 @@ -473,46 +493,32 @@ void hdsl_pruss_load_run_fw(HDSL_Handle hdslHandle) gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase); hdsl_enable_load_share_mode(gPru_cfg,PRUICSS_PRUx); - #endif if(HDSL_get_sync_ctrl(hdslHandle) == 0) { /*free run*/ - #if (MULTICHANNEL==0) - PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(PRUICSS_PRUx), - 0, (uint32_t *) Hiperface_DSL2_0, - sizeof(Hiperface_DSL2_0)); - #endif - #if (MULTICHANNEL==1) PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_RTU_PRU(1), - 0, (uint32_t *) Hiperface_DSL2_0_RTU, - sizeof(Hiperface_DSL2_0_RTU)); + 0, (uint32_t *) Hiperface_DSL2_0_RTU_0, + sizeof(Hiperface_DSL2_0_RTU_0)); PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(1), - 0, (uint32_t *) Hiperface_DSL2_0_PRU, - sizeof(Hiperface_DSL2_0_PRU)); - #endif + 0, (uint32_t *) Hiperface_DSL2_0_PRU_0, + sizeof(Hiperface_DSL2_0_PRU_0)); } else { - #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ!=300000000) - /*sync_mode*/ - PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(PRUICSS_PRUx), - 0, (uint32_t *) Hiperface_DSL_SYNC2_0, - sizeof(Hiperface_DSL_SYNC2_0)); - #endif + /*Sync mode*/ + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_RTU_PRU(1), + 0, (uint32_t *) Hiperface_DSL_SYNC2_0_RTU_0, + sizeof(Hiperface_DSL_SYNC2_0_RTU_0)); + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(1), + 0, (uint32_t *) Hiperface_DSL_SYNC2_0_PRU_0, + sizeof(Hiperface_DSL_SYNC2_0_PRU_0)); } - #if (MULTICHANNEL==0) - PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_PRUx); - /*Run firmware*/ - PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_PRUx); - #endif - #if(MULTICHANNEL==1) PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_RTU_PRU1); PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_PRU1); /*Run firmware*/ PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_RTU_PRU1); PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_PRU1); - #endif - +#endif } void hdsl_init(void) @@ -521,7 +527,6 @@ void hdsl_init(void) uint32_t period; hdsl_pruss_init(); - HDSL_iep_init(gHdslHandleCh0); ClockP_usleep(5000); if(CONFIG_HDSL0_MODE==0) @@ -533,33 +538,71 @@ void hdsl_init(void) ES=1; } HDSL_set_sync_ctrl(gHdslHandleCh0, ES); - if (MULTICHANNEL==1) - { - HDSL_set_sync_ctrl(gHdslHandleCh1, ES); - } if(ES != 0) { - #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) - DebugP_log("\r\n Sync mode with 300 MHz is not available"); - while(1); - #endif DebugP_log("\r\nSYNC MODE\n"); DebugP_log("\r\nEnter period for SYNC PULSE in unit of cycles(1 cycle = 4.44ns):"); DebugP_scanf("%d",&period); - HDSL_enable_sync_signal(ES,period); HDSL_generate_memory_image(gHdslHandleCh0); - if (MULTICHANNEL==1) - { - HDSL_generate_memory_image(gHdslHandleCh1); - } - sync_calculation(); + sync_calculation(gHdslHandleCh0); } else { DebugP_log( "\r\nFREE RUN MODE\n"); HDSL_generate_memory_image(gHdslHandleCh0); - if (MULTICHANNEL==1) + } +} +void hdsl_init_300m(void) +{ + uint8_t ES; + uint32_t period; + + hdsl_pruss_init_300m(); + HDSL_iep_init(gHdslHandleCh0); + ClockP_usleep(5000); + if(CONFIG_HDSL0_MODE==0) + { + ES=0; + } + else + { + ES=1; + } + if (CONFIG_HDSL0_CHANNEL0==1) + { + HDSL_set_sync_ctrl(gHdslHandleCh0, ES); + } + if (CONFIG_HDSL0_CHANNEL1==1) + { + HDSL_set_sync_ctrl(gHdslHandleCh1, ES); + } + + if(ES != 0) + { + DebugP_log("\r\nSYNC MODE\n"); + DebugP_log("\r\nEnter period for SYNC PULSE in unit of cycles(1 cycle = 3.33ns):"); + DebugP_scanf("%d",&period); + HDSL_enable_sync_signal(ES,period); + if (CONFIG_HDSL0_CHANNEL0==1) + { + HDSL_generate_memory_image(gHdslHandleCh0); + sync_calculation(gHdslHandleCh0); + } + if (CONFIG_HDSL0_CHANNEL1==1) + { + HDSL_generate_memory_image(gHdslHandleCh1); + sync_calculation(gHdslHandleCh1); + } + } + else + { + DebugP_log( "\r\nFREE RUN MODE\n"); + if (CONFIG_HDSL0_CHANNEL0==1) + { + HDSL_generate_memory_image(gHdslHandleCh0); + } + if (CONFIG_HDSL0_CHANNEL1==1) { HDSL_generate_memory_image(gHdslHandleCh1); } @@ -1108,19 +1151,21 @@ void hdsl_diagnostic_main(void *arg) #endif gPruIcss0Handle = PRUICSS_open(CONFIG_PRU_ICSS0); // initialize hdsl handle - #if (MULTICHANNEL==0) - gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_PRUx,0); - #endif - #if(MULTICHANNEL==1) - gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_RTU_PRU1,1); - gHdslHandleCh1 = HDSL_open(gPruIcss0Handle, PRUICSS_PRU1,1); - #endif DebugP_log( "\n\n Hiperface DSL diagnostic\n"); + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000) + gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_PRUx,0); hdsl_init(); + hdsl_pruss_load_run_fw(gHdslHandleCh0); + #else + gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_RTU_PRU1,1); + gHdslHandleCh1 = HDSL_open(gPruIcss0Handle, PRUICSS_PRU1,1); + hdsl_init_300m(); + hdsl_pruss_load_run_fw_300m(gHdslHandleCh0); + #endif DebugP_log( "\r\n HDSL setup finished\n"); /*need some extra time for SYNC mode since frames are longer*/ - hdsl_pruss_load_run_fw(gHdslHandleCh0); - + #if (CONFIG_HDSL0_CHANNEL0==1) + //Channel 0 starts here: ClockP_usleep(1000); for (ureg = HDSL_get_master_qm(gHdslHandleCh0), val = 0; !(ureg & 0x80); ureg = HDSL_get_master_qm(gHdslHandleCh0), val++, ClockP_usleep(10)) { @@ -1172,8 +1217,9 @@ void hdsl_diagnostic_main(void *arg) { DebugP_log( "\r| Multi turn bits: %u\n", gHdslHandleCh0->multi_turn); } - if (MULTICHANNEL==1) - { + #endif + #if (CONFIG_HDSL0_CHANNEL1==1) + //Channel 1 starts here: ClockP_usleep(1000); for (ureg = HDSL_get_master_qm(gHdslHandleCh1), val = 0; !(ureg & 0x80); ureg = HDSL_get_master_qm(gHdslHandleCh1), val++, ClockP_usleep(10)) @@ -1222,20 +1268,25 @@ void hdsl_diagnostic_main(void *arg) { DebugP_log( "\r| Multi turn bits: %u\n", gHdslHandleCh1->multi_turn); } - } + #endif while(1) { int menu; display_menu(); menu = get_menu(); - DebugP_log( "|\r\n Channel 0 "); - process_request(gHdslHandleCh0, menu); - DebugP_log( "\r%s", gUart_buffer); - #if (MULTICHANNEL==1) + if (CONFIG_HDSL0_CHANNEL0==1) + { + DebugP_log( "|\r\n Channel 0 "); + process_request(gHdslHandleCh0, menu); + DebugP_log( "\r%s", gUart_buffer); + } + + if (CONFIG_HDSL0_CHANNEL1==1) + { DebugP_log( "|\r\n Channel 1"); process_request(gHdslHandleCh1, menu); DebugP_log( "\r%s", gUart_buffer); - #endif + } } Board_driversClose(); Drivers_close(); diff --git a/examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/example.syscfg b/examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/example.syscfg index 65260f4..6f89fbc 100644 --- a/examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/example.syscfg +++ b/examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/example.syscfg @@ -1,8 +1,8 @@ /** * These arguments were used when this file was generated. They will be automatically applied on subsequent loads * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. - * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01" - * @versions {"tool":"1.12.1+2446"} + * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK@09.00.00" + * @versions {"tool":"1.17.0+3128"} */ /** @@ -42,11 +42,13 @@ gpio2.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO17"; gpio3.$name = "CONFIG_GPIO_TEST_COPY"; gpio3.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO18"; + i2c1.$name = "CONFIG_I2C0"; i2c1.I2C.$assign = "I2C1"; -pruicss1.$name = "CONFIG_PRU_ICSS1"; -pruicss1.instance = "ICSSG1"; +pruicss1.$name = "CONFIG_PRU_ICSS1"; +pruicss1.instance = "ICSSG1"; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; udma1.$name = "CONFIG_UDMA0"; udma1.udmaBlkCopyChannel.create(1); @@ -89,11 +91,14 @@ mpu_armv76.baseAddr = 0x80000000; mpu_armv76.size = 31; hdsl1.$name = "CONFIG_HDSL0"; +hdsl1.coreClk = 300000000; hdsl1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; -const pruicss2 = pruicss.addInstance({}, false); -pruicss2.$name = "CONFIG_PRU_ICSS0"; -hdsl1.pru = pruicss2; +const pruicss2 = pruicss.addInstance({}, false); +pruicss2.$name = "CONFIG_PRU_ICSS0"; +pruicss2.instance = scripting.forceWrite("ICSSG0"); +hdsl1.pru = pruicss2; +pruicss2.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO2"; /** * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future diff --git a/examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/example.syscfg b/examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/example.syscfg index 0bbaf1d..ed79c4b 100644 --- a/examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/example.syscfg +++ b/examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/example.syscfg @@ -1,8 +1,8 @@ /** * These arguments were used when this file was generated. They will be automatically applied on subsequent loads * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments. - * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM64x@08.03.00" - * @versions {"tool":"1.13.0+2553"} + * @cliArgs --device "AM64x" --package "ALV" --part "Default" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK@09.00.00" + * @versions {"tool":"1.17.0+3128"} */ /** @@ -42,11 +42,13 @@ gpio2.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO17"; gpio3.$name = "CONFIG_GPIO_TEST_COPY"; gpio3.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO18"; + i2c1.$name = "CONFIG_I2C0"; i2c1.I2C.$assign = "I2C1"; -pruicss1.$name = "CONFIG_PRU_ICSS1"; -pruicss1.instance = "ICSSG1"; +pruicss1.$name = "CONFIG_PRU_ICSS1"; +pruicss1.instance = "ICSSG1"; +pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0"; udma1.$name = "CONFIG_UDMA0"; udma1.udmaBlkCopyChannel.create(1); @@ -89,11 +91,14 @@ mpu_armv76.baseAddr = 0x80000000; mpu_armv76.size = 31; hdsl1.$name = "CONFIG_HDSL0"; +hdsl1.coreClk = 300000000; hdsl1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1"; -const pruicss2 = pruicss.addInstance({}, false); -pruicss2.$name = "CONFIG_PRU_ICSS0"; -hdsl1.pru = pruicss2; +const pruicss2 = pruicss.addInstance({}, false); +pruicss2.$name = "CONFIG_PRU_ICSS0"; +pruicss2.instance = scripting.forceWrite("ICSSG0"); +hdsl1.pru = pruicss2; +pruicss2.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO2"; /** * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future diff --git a/examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c b/examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c index 6a1024d..c044382 100644 --- a/examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c +++ b/examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c @@ -57,17 +57,18 @@ #include #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000) -#include -#include +#include +#include /* Divide factor for normal clock (default value for 225 MHz=23) */ #define DIV_FACTOR_NORMAL 23 /* Divide factor for oversampled clock (default value for 225 MHz=2) */ #define DIV_FACTOR_OVERSAMPLED 2 #endif #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) -#include -//#include - +#include +#include +#include +#include /* Divide factor for normal clock (default value for 300 MHz=31) */ #define DIV_FACTOR_NORMAL 31 /* Divide factor for oversampled clock (default value for 300 MHz=3) */ @@ -130,12 +131,13 @@ PRUICSS_IntcInitData gPruss1_intc_initdata = PRU_ICSS1_INTC_INITDATA; HDSL_Handle gHdslHandleCh0; -static void *gPru_cfg, *gPru_ctrl; +static void *gPru_cfg; static char gUart_buffer[256]; void *gPru_dramx; - +void *gPru_dramx_0; +void *gPru_dramx_1; int get_pos=1; uint32_t gMulti_turn, gRes; @@ -162,18 +164,23 @@ static void App_udmaTrpdInit(Udma_ChHandle chHandle, const void *srcBuf, uint32_t length); -void sync_calculation(void) +void sync_calculation(HDSL_Handle hdslHandle) { uint8_t ES; uint16_t wait_before_start; uint32_t counter, period, index; volatile uint32_t cap6_rise0, cap6_rise1, cap6_fall0, cap6_fall1; uint8_t EXTRA_EDGE_ARR[8] = {0x00 ,0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC, 0xFE}; - uint32_t minm_bits = 112, cycle_per_bit = 24, max_stuffing = 26, stuffing_size = 6, cycle_per_overclock_bit =3, minm_extra_size = 4, sync_param_mem_start = 0xDC; - uint32_t cycles_left, additional_bits, minm_cycles, time_gRest, extra_edge, extra_size, num_of_stuffing, extra_size_remainder, stuffing_remainder, bottom_up_cycles; - + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000) + uint32_t minm_bits = 112, cycle_per_bit = 24, max_stuffing = 26, stuffing_size = 6, cycle_per_overclock_bit =3, minm_extra_size = 4, sync_param_mem_start = 0xDC; + uint32_t cycles_left, additional_bits, minm_cycles, time_gRest, extra_edge, extra_size, num_of_stuffing, extra_size_remainder, stuffing_remainder, bottom_up_cycles; + #endif + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) + uint32_t minm_bits = 112, cycle_per_bit = 32, max_stuffing = 26, stuffing_size = 6, cycle_per_overclock_bit =4, minm_extra_size = 4, sync_param_mem_start = 0xDC; + uint32_t cycles_left, additional_bits, minm_cycles, time_gRest, extra_edge, extra_size, num_of_stuffing, extra_size_remainder, stuffing_remainder, bottom_up_cycles; + #endif /*measure of SYNC period starts*/ - ES = HDSL_get_sync_ctrl(gHdslHandleCh0); + ES = HDSL_get_sync_ctrl(hdslHandle); volatile uint32_t* carp6_rise_addr = (uint32_t*)(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP1_SLV_REGS_BASE + CSL_ICSS_G_PR1_IEP0_SLV_CAPR6_REG0); volatile uint32_t* carp6_fall_addr = (uint32_t*)(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP1_SLV_REGS_BASE + CSL_ICSS_G_PR1_IEP0_SLV_CAPF6_REG0); cap6_rise0 = *(carp6_rise_addr); @@ -232,7 +239,9 @@ void sync_calculation(void) { DebugP_log("\r\n ERROR: ES or period selected is Invalid "); } - + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) + wait_before_start=4968; + #endif DebugP_log("\r\n ********************************************************************"); DebugP_log("\r\n SYNC MODE: period = %d", period); DebugP_log("\r\n SYNC MODE: ES = %d", ES); @@ -246,8 +255,12 @@ void sync_calculation(void) DebugP_log("\r\n SYNC MODE: extra_size_remainder = %d", extra_size_remainder); DebugP_log("\r\n SYNC MODE: stuffing_remainder = %d", stuffing_remainder); DebugP_log("\r\n ********************************************************************"); - - sync_param_mem_start =sync_param_mem_start + (uint32_t)gPru_dramx; + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000) + sync_param_mem_start =sync_param_mem_start + (uint32_t)gPru_dramx; + #endif + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) + sync_param_mem_start =sync_param_mem_start + (uint32_t)hdslHandle->baseMemAddr; + #endif HWREGB(sync_param_mem_start) = extra_size; sync_param_mem_start = sync_param_mem_start + 1; HWREGB(sync_param_mem_start) = num_of_stuffing; @@ -358,13 +371,13 @@ static void App_udmaTrpdInit(Udma_ChHandle chHandle, return; } -void process_request(int menu){ +void process_request(HDSL_Handle hdslHandle,int menu){ switch(menu) { case MENU_HDSL_REG_INTO_DDR: - traces_into_ddr(); + traces_into_ddr(hdslHandle); break; case MENU_HDSL_REG_INTO_DDR_GPIO: TC_input_start_copy(); @@ -377,7 +390,6 @@ void process_request(int menu){ void hdsl_pruss_init(void) { - PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh0->icssCore); /* clear ICSS0 PRU data RAM */ @@ -403,36 +415,105 @@ void hdsl_pruss_init(void) PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRUx, PRUICSS_CONST_TBL_ENTRY_C29, 0x0002F000); /* enable cycle counter */ - gPru_ctrl = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE); + HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE), CTR_EN); +} +void hdsl_pruss_init_300m(void) +{ + PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh0->icssCore); + /* Clear PRU_DRAM0 and PRU_DRAM1 memory */ - HW_WR_REG32(gPru_ctrl, CTR_EN); + gPru_dramx_0 = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_RTU_PRU1)); + gPru_dramx_1 = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_PRU1)); + memset(gPru_dramx_0, 0, (4 * 1024)); + memset(gPru_dramx_1, 0, (4 * 1024)); + memset((void *) CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, 0, (16 * 1024)); + memset((void *) CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE, 0, (16 * 1024)); + + gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase); + + HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_GPCFG1, HDSL_EN); + HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, HDSL_TX_CFG); + HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1RXCFGREGISTER, HDSL_RX_CFG); + PRUICSS_intcInit(gPruIcss0Handle, &gPruss0_intc_initdata); + + /* configure C28 to PRU_ICSS_CTRL and C29 to EDMA + 0x1000 */ + /*6.4.14.1.1 ICSSG_PRU_CONTROL RegisterPRU_ICSSG0_PR1_PDSP0_IRAM 00B0 2400h*/ + HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_PROG_PTR_0) = 0xF0000238; // Address = 0x30023828 + PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C28, 0x0240); + HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_PROG_PTR_0) = 0xF0000258; // Address = 0x30025828 + /*IEP1 base */ + PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C29, 0x0002F000); + + HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_BLOCK_INDEX_0) = 0x0000; // RTU Core + PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C24, 0x0007); // PRU Core + HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_BLOCK_INDEX_0) = 0x000E; // TX_PRU Core + + /* enable cycle counter */ + HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE), CTR_EN); // RTU_PRU Core + HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE), CTR_EN); + HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE), CTR_EN); // TX_PRU Core } void hdsl_pruss_load_run_fw(HDSL_Handle hdslHandle) { - PRUICSS_disableCore(gPruIcss0Handle, hdslHandle->icssCore); - - if(HDSL_get_sync_ctrl(hdslHandle) == 0) - { - /*free run*/ - PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(PRUICSS_PRUx), - 0, (uint32_t *) Hiperface_DSL2_0, - sizeof(Hiperface_DSL2_0)); - } - else - { - #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ!=300000000) + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000) + PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_PRUx); + if(HDSL_get_sync_ctrl(hdslHandle) == 0) + { + /*free run*/ + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(PRUICSS_PRUx), + 0, (uint32_t *) Hiperface_DSL2_0_RTU_0, + sizeof(Hiperface_DSL2_0_RTU_0)); + } + else + { /*sync_mode*/ PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(PRUICSS_PRUx), - 0, (uint32_t *) Hiperface_DSL_SYNC2_0, - sizeof(Hiperface_DSL_SYNC2_0)); - #endif - } + 0, (uint32_t *) Hiperface_DSL_SYNC2_0_RTU_0, + sizeof(Hiperface_DSL_SYNC2_0_RTU_0)); + } + PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_PRUx); + /*Run firmware*/ + PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_PRUx); + #endif +} - PRUICSS_resetCore(gPruIcss0Handle, hdslHandle->icssCore); - /*Run firmware*/ - PRUICSS_enableCore(gPruIcss0Handle, hdslHandle->icssCore); +void hdsl_pruss_load_run_fw_300m(HDSL_Handle hdslHandle) +{ + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) + PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_RTU_PRU1); // ch0 + PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_PRU1); // ch1 + + /* Enable Load Share mode */ + gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase); + hdsl_enable_load_share_mode(gPru_cfg,PRUICSS_PRUx); + if(HDSL_get_sync_ctrl(hdslHandle) == 0) + { + /*free run*/ + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_RTU_PRU(1), + 0, (uint32_t *) Hiperface_DSL2_0_RTU_0, + sizeof(Hiperface_DSL2_0_RTU_0)); + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(1), + 0, (uint32_t *) Hiperface_DSL2_0_PRU_0, + sizeof(Hiperface_DSL2_0_PRU_0)); + } + else + { + /*Sync mode*/ + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_RTU_PRU(1), + 0, (uint32_t *) Hiperface_DSL_SYNC2_0_RTU_0, + sizeof(Hiperface_DSL_SYNC2_0_RTU_0)); + PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(1), + 0, (uint32_t *) Hiperface_DSL_SYNC2_0_PRU_0, + sizeof(Hiperface_DSL_SYNC2_0_PRU_0)); + } + PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_RTU_PRU1); + PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_PRU1); + /*Run firmware*/ + PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_RTU_PRU1); + PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_PRU1); + #endif } void hdsl_init(void) @@ -453,30 +534,23 @@ void hdsl_init(void) HDSL_iep_init(gHdslHandleCh0); ClockP_usleep(5000); - if(CONFIG_HDSL0_MODE==0) { - ES=0; + ES=0; } else { - ES=1; + ES=1; } - HDSL_set_sync_ctrl(gHdslHandleCh0, ES); - if(ES != 0) { - #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000) - DebugP_log("\r\n Sync mode with 300 MHz is not available"); - while(1); - #endif - DebugP_log("\r\nSYNC MODE\n"); - DebugP_log("\r\nEnter period for SYNC PULSE in unit of cycles(1 cycle = 4.44ns):"); - DebugP_scanf("%d",&period); - HDSL_enable_sync_signal(ES,period); - HDSL_generate_memory_image(gHdslHandleCh0); - sync_calculation(); + DebugP_log("\r\nSYNC MODE\n"); + DebugP_log("\r\nEnter period for SYNC PULSE in unit of cycles(1 cycle = 4.44ns):"); + DebugP_scanf("%d",&period); + HDSL_enable_sync_signal(ES,period); + HDSL_generate_memory_image(gHdslHandleCh0); + sync_calculation(gHdslHandleCh0); } else { @@ -484,7 +558,57 @@ void hdsl_init(void) HDSL_generate_memory_image(gHdslHandleCh0); } } +void hdsl_init_300m(void) +{ + uint8_t ES; + uint32_t period; + HwiP_Params hwiPrms; + uint32_t intrNum; + intrNum = HDSL_DDR_TRACE_R5F_IRQ_NUM; + hdsl_pruss_init_300m(); + /* Register PRU interrupt */ + HwiP_Params_init(&hwiPrms); + hwiPrms.intNum = intrNum; + hwiPrms.callback = (void*)&HDSL_IsrFxn; + HwiP_construct(&gPRUHwiObject, &hwiPrms); + + HDSL_iep_init(gHdslHandleCh0); + ClockP_usleep(5000); + if(CONFIG_HDSL0_MODE==0) + { + ES=0; + } + else + { + ES=1; + } + if (CONFIG_HDSL0_CHANNEL0==1) + { + HDSL_set_sync_ctrl(gHdslHandleCh0, ES); + } + + if(ES != 0) + { + DebugP_log("\r\nSYNC MODE\n"); + DebugP_log("\r\nEnter period for SYNC PULSE in unit of cycles(1 cycle = 3.33ns):"); + DebugP_scanf("%d",&period); + HDSL_enable_sync_signal(ES,period); + if (CONFIG_HDSL0_CHANNEL0==1) + { + HDSL_generate_memory_image(gHdslHandleCh0); + sync_calculation(gHdslHandleCh0); + } + } + else + { + DebugP_log( "\r\nFREE RUN MODE\n"); + if (CONFIG_HDSL0_CHANNEL0==1) + { + HDSL_generate_memory_image(gHdslHandleCh0); + } + } +} static void HDSL_IsrFxn() { static uint64_t v_frames_count=0; @@ -532,11 +656,11 @@ static void display_menu(void) DebugP_log("\r\n Enter value: "); } -void traces_into_ddr(void) +void traces_into_ddr(HDSL_Handle hdslHandle) { int i= 0; uint32_t length; - length = HDSL_get_length(gHdslHandleCh0); + length = HDSL_get_length(hdslHandle); DebugP_log("\r\n sizeof(hdslInterface)_count = %u", length); DebugP_log("\r\n Start address of DDR location = %u", DDR_START_OFFSET); @@ -717,77 +841,85 @@ void hdsl_diagnostic_main(void *arg) HW_WR_REG32(0x000F41D4, 0x00050001); /* PRG0_PRU1_GPI9 as input */ hdsl_i2c_io_expander(NULL); #endif - + DebugP_log( "\n\n Hiperface DSL diagnostic\n"); gPruIcss0Handle = PRUICSS_open(CONFIG_PRU_ICSS0); - gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_PRUx,0); - - DebugP_log("\r\n Hiperface DSL Diagnostic"); - hdsl_init(); + #if (CONFIG_HDSL0_CHANNEL1==1) + DebugP_log("\r\n Channel 1 not supported in DDR Trace application"); + while(1); + #endif + #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000) + gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_PRUx,0); + hdsl_init(); + hdsl_pruss_load_run_fw(gHdslHandleCh0); + #else + gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_RTU_PRU1,1); + hdsl_init_300m(); + hdsl_pruss_load_run_fw_300m(gHdslHandleCh0); + #endif DebugP_log("\r\n HDSL Setup finished"); /*need some extra time for SYNC mode since frames are longer*/ hdsl_pruss_load_run_fw(gHdslHandleCh0); - ClockP_usleep(1000); - - for (ureg = HDSL_get_master_qm(gHdslHandleCh0), val = 0; !(ureg & 0x80); ureg = HDSL_get_master_qm(gHdslHandleCh0), val++, ClockP_usleep(10)) - { - if (val > 100) - { /* wait 1ms to detect, increase if reqd. */ - while(1) - { - DebugP_log( "\r\n Hiperface DSL encoder not detected\n"); - ClockP_usleep(5000); + #if (CONFIG_HDSL0_CHANNEL0==1) + //Channel 0 starts here: + ClockP_usleep(1000); + for (ureg = HDSL_get_master_qm(gHdslHandleCh0), val = 0; !(ureg & 0x80); ureg = HDSL_get_master_qm(gHdslHandleCh0), val++, ClockP_usleep(10)) + { + if (val > 100) + { /* wait 1ms to detect, increase if reqd. */ + while(1) + { + DebugP_log( "\r\n Hiperface DSL encoder not detected\n"); + ClockP_usleep(5000); + } } } - } + DebugP_log("\r\n "); + DebugP_log("\r\n |-------------------------------------------------------------------------------|"); + DebugP_log("\r\n | Hiperface DSL diagnostic |"); + DebugP_log("\r\n |-------------------------------------------------------------------------------|"); + DebugP_log("\r\n | Quality monitoring value: %u |", ureg & 0xF); + ureg = HDSL_get_edges(gHdslHandleCh0); + DebugP_log("\r\n | Edges: 0x%x |", ureg); + ureg = HDSL_get_delay(gHdslHandleCh0); + DebugP_log("\r\n | Cable delay: %u |", ureg & 0xF); + DebugP_log("\r\n | RSSI: %u |", (ureg & 0xF0) >> 4); - DebugP_log("\r\n "); - DebugP_log("\r\n |-------------------------------------------------------------------------------|"); - DebugP_log("\r\n | Hiperface DSL diagnostic |"); - DebugP_log("\r\n |-------------------------------------------------------------------------------|"); - DebugP_log("\r\n | Quality monitoring value: %u |", ureg & 0xF); - - ureg = HDSL_get_edges(gHdslHandleCh0); - DebugP_log("\r\n | Edges: 0x%x |", ureg); - - ureg = HDSL_get_delay(gHdslHandleCh0); - DebugP_log("\r\n | Cable delay: %u |", ureg & 0xF); - DebugP_log("\r\n | RSSI: %u |", (ureg & 0xF0) >> 4); - - val = HDSL_get_enc_id(gHdslHandleCh0, 0) | (HDSL_get_enc_id(gHdslHandleCh0, 1) << 8) | (HDSL_get_enc_id(gHdslHandleCh0, 2) << 16); - - acc_bits = val & 0xF; - acc_bits += 8; - pos_bits = (val & 0x3F0) >> 4; - pos_bits += acc_bits; - DebugP_log("\r\n | Encoder ID: 0x%x", val); - DebugP_log("("); - DebugP_log("Acceleration bits: %u, ", acc_bits); - DebugP_log("Position bits: %u,", pos_bits); - DebugP_log("%s", val & 0x400 ? " Bipolar position" : " Unipolar position"); - DebugP_log(")|"); - DebugP_log("\r\n |-------------------------------------------------------------------------------|"); - - DebugP_log("\r\n Enter single turn bits: "); - if((DebugP_scanf("%d", &gRes) < 0) || gRes > pos_bits) - { + val = HDSL_get_enc_id(gHdslHandleCh0, 0) | (HDSL_get_enc_id(gHdslHandleCh0, 1) << 8) | (HDSL_get_enc_id(gHdslHandleCh0, 2) << 16); + acc_bits = val & 0xF; + acc_bits += 8; + pos_bits = (val & 0x3F0) >> 4; + pos_bits += acc_bits; + DebugP_log("\r\n | Encoder ID: 0x%x", val); + DebugP_log("("); + DebugP_log("Acceleration bits: %u, ", acc_bits); + DebugP_log("Position bits: %u,", pos_bits); + DebugP_log("%s", val & 0x400 ? " Bipolar position" : " Unipolar position"); + DebugP_log(")|"); + DebugP_log("\r\n |-------------------------------------------------------------------------------|"); + DebugP_log("\r\n Enter single turn bits: "); + if((DebugP_scanf("%d", &gRes) < 0) || gRes > pos_bits) + { DebugP_log("\r\n WARNING: invalid single turn bits, assuming single turn encoder"); gRes = pos_bits; - } - gMulti_turn = pos_bits - gRes; - gMask = pow(2, gRes) - 1; - if (gMulti_turn) - { - DebugP_log("\r\n Multi turn bits: %u", gMulti_turn); - } + } + gMulti_turn = pos_bits - gRes; + gMask = pow(2, gRes) - 1; + if (gMulti_turn) + { + DebugP_log("\r\n Multi turn bits: %u", gMulti_turn); + } + #endif while(1) { - int menu; display_menu(); - menu = get_menu(); - process_request(menu); - DebugP_log( "\r%s", gUart_buffer); + if (CONFIG_HDSL0_CHANNEL0==1) + { + DebugP_log( "|\r\n Channel 0 "); + process_request(gHdslHandleCh0, menu); + DebugP_log( "\r%s", gUart_buffer); + } } Board_driversClose(); diff --git a/makefile.am243x b/makefile.am243x index f70fd92..2e39341 100644 --- a/makefile.am243x +++ b/makefile.am243x @@ -69,6 +69,8 @@ help: @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] @echo $(MAKE) -s -C source/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] @echo $(MAKE) -s -C source/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] @@ -199,6 +201,8 @@ BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am243x-evm_icssg0 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt @@ -278,6 +282,12 @@ examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL) hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt: $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt: $(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all @@ -320,6 +330,8 @@ BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_freerun_225_mhz_am243x-evm_ BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean @@ -399,6 +411,12 @@ examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL) hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: $(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean @@ -441,6 +459,8 @@ BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_freerun_225_mhz_am243x-evm_ BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub @@ -520,6 +540,12 @@ examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL) hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: $(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub diff --git a/makefile.am64x b/makefile.am64x index bfce17b..996fe0b 100644 --- a/makefile.am64x +++ b/makefile.am64x @@ -65,6 +65,8 @@ help: @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] + @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] @echo $(MAKE) -s -C source/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] @echo $(MAKE) -s -C source/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg] @@ -190,6 +192,8 @@ BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am64x-evm_icssg0- BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt +BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt @@ -256,6 +260,12 @@ examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL) hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt: $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + + hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all + hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt: $(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all @@ -291,6 +301,8 @@ BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_freerun_225_mhz_am64x-evm_i BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean @@ -357,6 +369,12 @@ examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL) hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + + hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean + hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: $(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean @@ -392,6 +410,8 @@ BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_freerun_225_mhz_am64x-evm_i BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub +BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub @@ -458,6 +478,12 @@ examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL) hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + + hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub + hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub: $(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub diff --git a/makefile_projectspec.am243x b/makefile_projectspec.am243x index bc449ba..d3deb29 100644 --- a/makefile_projectspec.am243x +++ b/makefile_projectspec.am243x @@ -34,6 +34,8 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_freerun_225_mhz BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build @@ -113,6 +115,12 @@ all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL) hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build: $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build: $(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all @@ -156,6 +164,8 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_freerun_225_mhz BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean @@ -235,6 +245,12 @@ clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL) hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: $(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean @@ -278,6 +294,8 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_freerun_225_mh BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export @@ -357,6 +375,12 @@ export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL) hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export: $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export: $(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export @@ -421,6 +445,8 @@ help: @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] @echo $(MAKE) -s -C source/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] @echo $(MAKE) -s -C source/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] diff --git a/makefile_projectspec.am64x b/makefile_projectspec.am64x index 50e2ab5..643e941 100644 --- a/makefile_projectspec.am64x +++ b/makefile_projectspec.am64x @@ -30,6 +30,8 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_freerun_225_mhz BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build +BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build @@ -96,6 +98,12 @@ all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL) hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build: $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + + hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all + hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build: $(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all @@ -132,6 +140,8 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_freerun_225_mhz BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean +BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean @@ -198,6 +208,12 @@ clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL) hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + + hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean + hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean: $(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean @@ -234,6 +250,8 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_freerun_225_mh BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export +BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export @@ -300,6 +318,12 @@ export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL) hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export: $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + + hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export: + $(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export + hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export: $(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export @@ -357,6 +381,8 @@ help: @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/freerun_300_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] + @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] @echo $(MAKE) -s -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] @echo $(MAKE) -s -C source/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] @echo $(MAKE) -s -C source/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean] diff --git a/source/position_sense/hdsl/.project/project_am243x.js b/source/position_sense/hdsl/.project/project_am243x.js index 1da169f..c6a7d3e 100644 --- a/source/position_sense/hdsl/.project/project_am243x.js +++ b/source/position_sense/hdsl/.project/project_am243x.js @@ -11,15 +11,13 @@ const files = { const filedirs = { common: [ - "driver", - //"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/driver", + "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/driver", ], }; const includes = { - common: [ - "include", - //"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/include", + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/include", ], }; diff --git a/source/position_sense/hdsl/.project/project_am64x.js b/source/position_sense/hdsl/.project/project_am64x.js index 5375061..3060c70 100644 --- a/source/position_sense/hdsl/.project/project_am64x.js +++ b/source/position_sense/hdsl/.project/project_am64x.js @@ -11,21 +11,20 @@ const files = { const filedirs = { common: [ - "driver", - // "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/driver", + + "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/driver", ], }; const includes = { common: [ - "include", - // "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/include", + + "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/include", ], }; const buildOptionCombos = [ { device: device, cpu: "r5f", cgt: "ti-arm-clang"}, - // { device: device, cpu: "r5f", cgt: "gcc-armv7"}, ]; function getComponentProperty() { diff --git a/source/position_sense/hdsl/firmware/datalink.asm b/source/position_sense/hdsl/firmware/datalink.asm index 6950c44..cfd79e1 100644 --- a/source/position_sense/hdsl/firmware/datalink.asm +++ b/source/position_sense/hdsl/firmware/datalink.asm @@ -48,15 +48,6 @@ .ref transport_layer_recv_msg .ref load_code .ref datalink_reset - .ref send_01 - .ref int_div - - .ref transport_on_v_frame_2 - .ref transport_layer_processing_1 - .ref transport_layer_processing_2 - - ;.ref transport_layer_assemble_msg - ;.global transport_layer_assemble_msg_done .global transport_layer_send_msg_done .global transport_layer_recv_msg_done .global transport_layer_done @@ -75,12 +66,20 @@ .global calc_rssi .global send_stuffing .global send_header + .global send_header_modified + .global send_header_300m .global send_trailer .global wait_delay .global datalink_loadfw .global recv_dec .global main .global datalink_wait_vsynch + .global send_01 + .global int_div + .global sync_pulse + .global check_test_pattern + .global datalink_abort_jmp + .global receive ;Initialize connection and state machine here datalink_init: @@ -88,59 +87,23 @@ datalink_init: .sect ".text" jmp main ;-------------------------------------------------------------------------------------------------- -;State LOADFW -;this state does not exist in the Hiperface DSL specification and is only used to gain time for loading PRU Code to intruction memory! -datalink_loadfw: - ldi LOOP_CNT.b1, NUM_LOADFW - zero &FAST_POSH, 4 - -datalink_loadfw_loop: - ldi REG_FNC.w0, (0x0000 | M_PAR_IDREQ) - CALL send_header - ;CALL recv_dec - WAIT_TX_DONE -;slave transmits answer here (61 bits) - READ_IEPCNT SPEED -;we switch to tx again - TX_EN -;wait 12bits - delay -;TODO: rm delay! - qbeq datalink_loadfw_no_wait, SLAVE_DELAY, 12 -;wait 61+1sw+12delay bits - slave delay -; ldi REG_TMP1, (74*CYCLES_BIT-26+4-3) - .if $defined("FREERUN_300_MHZ") - ldi REG_TMP1, (74*CYCLES_BIT+5-2) - .else - ldi REG_TMP1, (74*CYCLES_BIT+5) - .endif - READ_IEPCNT REG_TMP0 - sub REG_TMP0, REG_TMP0, SPEED - sub REG_TMP0, REG_TMP1, REG_TMP0 - WAIT REG_TMP0 -datalink_loadfw_no_wait: -;send TRAILER - CALL1 send_trailer - CALL1 send_stuffing - sub LOOP_CNT.b1, LOOP_CNT.b1, 1 - qbne datalink_loadfw_loop, LOOP_CNT.b1, 0 - zero &SPEED, (4*8) - ;-------------------------------------------------------------------------------------------------- -;State WAIT VSYNC -;Send M_PAR_IDLE and wait for VSYNC=1 - ldi LOOP_CNT.b1, 7 +;State RX 0-7 datalink_wait_vsynch: zero &SPEED, (4*8) ldi LOOP_CNT.b1, 7 ;send m_par_reset 8b/10b: 5b/6b and 3b/4b, first=1,vsync=0,reserved=0 ldi REG_FNC.w0, (0x0400 | M_PAR_INIT) + .if $defined("HDSL_MULTICHANNEL") + CALL send_header_300m + .else CALL send_header + .endif CALL recv_dec ;check for timeout sub LOOP_CNT.b1, LOOP_CNT.b1, 1 qbeq datalink_abort_jmp, LOOP_CNT.b1, 0 CALL1 send_stuffing - ;check for error in parameter channel (byte 1) qbbs datalink_wait_vsynch, BYTE_ERROR, BYTE_CH_PARAMETER ;try again if vsync is not set @@ -196,7 +159,11 @@ datalink_rx0_7_not_rx7: ;send m_par_reset 8b/10b: 5b/6b and 3b/4b, first=1,vsync=1,reserved=0 mov REG_FNC.b0, SEND_PARA qbeq modified_header, MODIFIED_HEADER_STARTED, 1 - CALL send_header + .if $defined("HDSL_MULTICHANNEL") + CALL send_header_300m + .else + CALL send_header + .endif ldi MODIFIED_HEADER_STARTED, 1 qba header_send_done modified_header: @@ -220,97 +187,23 @@ datalink_rx0_7_vsync_continue: ;reset flags clr H_FRAME.flags, H_FRAME.flags, FLAG_ERR_ACC CALL1 send_stuffing + + .if !$defined("HDSL_MULTICHANNEL") ;Single channel(225m) starts here ;sending sync and 2 bits of sample early to buy processing time for h frame processing qbeq modified_header_early_data_push_free_run, EXTRA_SIZE, 0 - .if $defined("HDSL_MULTICHANNEL") -; PUSH 8 bytes for 1 byte data (0x2f) in FIFO WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0x00 - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - ;qbeq modified_header_early_data_push_done, EXTRA_SIZE, 0 - ;PUSH 8 bytes for 1 byte data (0xff) in FIFO - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - .else - WAIT_TX_FIFO_FREE PUSH_FIFO_CONST 0x2f WAIT_TX_FIFO_FREE PUSH_FIFO_CONST 0xff - .endif RESET_CYCLCNT qba modified_header_early_data_push_done modified_header_early_data_push_free_run: - - .if $defined("HDSL_MULTICHANNEL") - ;;PUSH 8 bytes for 1 byte data (0x2f) in FIFO - ;;last 6 bytes not being pushed in continous manner(some PRU code being executed and then PUSH a byte to stop FIFO underrun issue) WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 -modified_header_early_data_push_done: - ;READ_CYCLCNT r19 -;go to H-Frame callback on transport layer (max. 120-50=70 cycles) - CALL transport_on_h_frame - sub LOOP_CNT.b2, LOOP_CNT.b2, 1 - qbeq Safety_fifo_push,LOOP_CNT.b2,7 - qblt Hframe_fifo_push, LOOP_CNT.b2, 0 - jmp Vframe_fifo_push - -Hframe_fifo_push: - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - qba datalink_rx0_7 -;V-Frame ends here -;reset BYTE_ERROR -Vframe_fifo_push: - ldi BYTE_ERROR, 0x00 - ldi LOOP_CNT.b2, 8 - set H_FRAME.flags, H_FRAME.flags, FLAG_NORMAL_FLOW - PUSH_FIFO_CONST 0xff - qba datalink_rx0_7 -Safety_fifo_push: - qbbc Hframe_fifo_push, H_FRAME.flags, FLAG_NORMAL_FLOW - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0x00 - qba datalink_rx0_7 - - .else ;not a multi channel - WAIT_TX_FIFO_FREE PUSH_FIFO_CONST 0x2f modified_header_early_data_push_done: ;READ_CYCLCNT r19 ;go to H-Frame callback on transport layer (max. 120-50=70 cycles) CALL transport_on_h_frame - ;READ_CYCLCNT REG_TMP2 - sub LOOP_CNT.b2, LOOP_CNT.b2, 1 qblt datalink_rx0_7, LOOP_CNT.b2, 0 ;V-Frame ends here @@ -321,8 +214,261 @@ modified_header_early_data_push_done: ldi LOOP_CNT.b2, 8 set H_FRAME.flags, H_FRAME.flags, FLAG_NORMAL_FLOW qba datalink_rx0_7 - .endif ;HDSL_MULTICHANNEL + .else ;Single channel ends here + ;Multi-channel starts here + +;sending sync and 2 bits of sample early to buy processing time for h frame processing + ;;PUSH 8 bytes for 1 byte data (0x2f) in FIFO + ;;last 6 bytes not being pushed in continous manner(some PRU code being executed and then PUSH a byte to stop FIFO underrun issue) + +modified_header_early_data_push_done: +;go to H-Frame callback on transport layer (max. 120-50=70 cycles) + CALL transport_on_h_frame + sub LOOP_CNT.b2, LOOP_CNT.b2, 1 + qbeq hframe_7_fifo_push,LOOP_CNT.b2,7 + qblt Hframe_fifo_push, LOOP_CNT.b2, 0 + jmp Vframe_fifo_push + +Hframe_fifo_push: + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + LOOP push_2b_0_0 ,2 + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff +push_2b_0_0: + qbeq free_run_mode_0, EXTRA_SIZE, 0 + PUSH_FIFO_CONST 0xff +free_run_mode_0: + RESET_CYCLCNT + qba datalink_rx0_7 +;V-Frame ends here +;reset BYTE_ERROR +Vframe_fifo_push: + ldi BYTE_ERROR, 0x00 + ldi LOOP_CNT.b2, 8 + set H_FRAME.flags, H_FRAME.flags, FLAG_NORMAL_FLOW + PUSH_FIFO_CONST 0xff + qba datalink_rx0_7 +hframe_7_fifo_push: + qbbc Hframe_fifo_push, H_FRAME.flags, FLAG_NORMAL_FLOW + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0x00 + qba datalink_rx0_7 + + .endif ;Multichannel ;-------------------------------------------------------------------------------------------------- + +;-------------------------------------------------------------------------------------------------- +;Function: receive +;This functions receives data without deocoding. +;output: +; r20-r19: data +;-------------------------------------------------------------------------------------------------- +receive: + ldi LOOP_CNT.b0, 32 + CALL1 wait_delay + ldi REG_TMP0.w0, 0 + ldi REG_TMP11, (PDMEM00+0x5a4);LUT_B2B) + zero &r18, (4*5) +datalink_receive_signal_0_31_1: + qbbc datalink_receive_signal_0_31_1, r31, RX_VALID_FLAG + POP_FIFO REG_TMP0.b0 + CLEAR_VAL + sub LOOP_CNT.b0, LOOP_CNT.b0, 1 + qbbc datalink_receive_signal_0_31_received_0_1, REG_TMP0.w0, SAMPLE_EDGE + set r20, r20, LOOP_CNT.b0 +datalink_receive_signal_0_31_received_0_1: + mov REG_TMP0.b1, REG_TMP0.b0 +;get edges + lsr REG_TMP1.b0, REG_TMP0.w0, 1 + xor CUR_EDGES, REG_TMP1.b0, REG_TMP0.b0 + CALL1 calc_rssi + qbne datalink_receive_signal_0_31_1, LOOP_CNT.b0, 0 +;receive next bits + ldi LOOP_CNT.b0, 29 +datalink_receive_signal_32_60_1: + qbbc datalink_receive_signal_32_60_1, r31, RX_VALID_FLAG ;changed here from 24 to 26 + POP_FIFO REG_TMP0.b0 + CLEAR_VAL + sub LOOP_CNT.b0, LOOP_CNT.b0, 1 + qbbc datalink_receive_signal_32_60_received_0_1, REG_TMP0.w0, SAMPLE_EDGE + set r19, r19, LOOP_CNT.b0 +datalink_receive_signal_32_60_received_0_1: + mov REG_TMP0.b1, REG_TMP0.b0 +;get edges + lsr REG_TMP1.b0, REG_TMP0.w0, 1 + xor CUR_EDGES, REG_TMP1.b0, REG_TMP0.b0 + CALL1 calc_rssi + qbne datalink_receive_signal_32_60_1, LOOP_CNT.b0, 1 +datalink_receive_signal_last_1: + qbbc datalink_receive_signal_last_1, r31, RX_VALID_FLAG ;changed here from 24 to 26 + POP_FIFO REG_TMP0.b0 + qbbc datalink_receive_signal_last_received_0_1, REG_TMP0.w0, SAMPLE_EDGE + set r19, r19, 0 +datalink_receive_signal_last_received_0_1: + lsl r19, r19, 3 + CLEAR_VAL +; same delay code as in learn + ldi REG_TMP1, (74*CYCLES_BIT+7-2);-7=14iters;-35 ;-34; -9 for 100 m + READ_CYCLCNT REG_TMP0 + qble receive_skip_wait, REG_TMP0, REG_TMP1 + sub REG_TMP0, REG_TMP1, REG_TMP0 + ;sub REG_TMP0,REG_TMP0,28 ;28- 13 + add r0,r0,1 + WAIT REG_TMP0 +receive_skip_wait: + TX_EN +; datalink_receive_signal_no_delay_wait_1: + CALL1 send_trailer + CALL1 send_stuffing + RET +;-------------------------------------------------------------------------------------------------- +;Function: sync_pulse (RET_ADDR1) +;functions bussy waits for sync pulse +;input: +;modifies: +;-------------------------------------------------------------------------------------------------- +;stores sync pulse period in R20 in unit of cycles +sync_pulse: + lbco ®_TMP1, c1, IEP_CAPR6_RISE, 4 +wait_next_pulse: + lbco &R20, c1, IEP_CAPR6_RISE, 4 + QBEQ wait_next_pulse, R20, REG_TMP1 + SUB R20, R20, REG_TMP1 + RET1 +;-------------------------------------------------------------------------------------------------- +;Function: int_div (RET_ADDR1) +;integer divides +;input: +; REG_FNC.w0: Number +; REG_FNC.w2: Divisor +;output: +; REG_FNC.w2: Result +; REG_FNC.w0: Rest +;modifies: +;-------------------------------------------------------------------------------------------------- +int_div: + ldi REG_TMP0, 0 +int_div_loop: + qbgt int_div_end, REG_FNC.w0, REG_FNC.w2 + sub REG_FNC.w0, REG_FNC.w0, REG_FNC.w2 + add REG_TMP0, REG_TMP0, 1 + qba int_div_loop +int_div_end: + mov REG_FNC.w2, REG_TMP0 + RET1 +;-------------------------------------------------------------------------------------------------- +;Function: check_test_pattern (RET_ADDR1) +;This function checks if the test pattern was received +;input: +; r18-r20: data +;output: +; REG_FNC.b0: 1 if true +;modifies: +; REG_TMP0, REG_FNC +;-------------------------------------------------------------------------------------------------- +check_test_pattern: +;load test pattern and mask from memory + + lbco ®_TMP0, MASTER_REGS_CONST, TEST_PATTERN0, 12 +;rm switch bit + and REG_TMP11, r19, REG_TMP2 + ldi REG_TMP2, 0xff8 + and REG_TMP2, r19, REG_TMP2 + lsl REG_TMP2, REG_TMP2, 1 + or REG_TMP11, REG_TMP2, REG_TMP11 +;if found go to next step + qbne check_test_pattern_false, r20, REG_TMP0 + qbne check_test_pattern_false, REG_TMP11, REG_TMP1 +check_test_pattern_true: + ldi REG_FNC.b0, 1 + RET1 +check_test_pattern_false: + ldi REG_FNC.b0, 0 + RET1 +;-------------------------------------------------------------------------------------------------- +;Function: send_01 (RET_ADDR1) +;This function sends 01 pattern in RESET and SYNC state +;input: +; REG_FNC.b2: last two bits of parameter channel +;output: +;modifies: +;-------------------------------------------------------------------------------------------------- +send_01: +;send 01 pattern +;2 para bits, 1 switch bit, 5 slave bit + or REG_FNC.b2, REG_FNC.b2, 0x15;0bPPS10101 + .if $defined("HDSL_MULTICHANNEL") + mov FIFO_L,REG_FNC.b2 + PUSH_FIFO_8x FIFO_L + .else + PUSH_FIFO REG_FNC.b2 + .endif +;56+12 line delay slave bits + ldi REG_TMP0.b0, 8 +send_header_send_01_pattern_loop: + ;;PUSH 8 bytes for 1 byte data (0x55) in FIFO + + .if $defined("HDSL_MULTICHANNEL") + LOOP push_2B_1 ,4 + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0xff +push_2B_1: + + .else + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x55 + .endif + sub REG_TMP0.b0, REG_TMP0.b0, 1 + qbne send_header_send_01_pattern_loop, REG_TMP0.b0, 0 +;send last 0101 (4 bits) + WAIT_TX_FIFO_FREE +;overclock(8x) + PUSH_FIFO_CONST 0x00 + ldi REG_TMP0, (9*(CLKDIV_NORMAL+1)-9) + .if !$defined("HDSL_MULTICHANNEL") + WAIT REG_TMP0 + TX_CLK_DIV CLKDIV_FAST, REG_TMP0 + .endif + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0xff +;push TRAILER + ;PUSH 8 bytes for 1 byte data (0x03) in FIFO + WAIT_TX_FIFO_FREE + .if $defined("HDSL_MULTICHANNEL") + LOOP push_2B_0 ,3 + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0x00 + WAIT_TX_FIFO_FREE +push_2B_0: + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff + .else + PUSH_FIFO_CONST 0x03 + .endif + .if $defined("FREERUN_300_MHZ") + ldi REG_TMP0, (6*(CLKDIV_FAST+1)-8+2) + .else + ldi REG_TMP0, (6*(CLKDIV_FAST+1)-8) + .endif + .if !$defined("HDSL_MULTICHANNEL") + WAIT REG_TMP0 + TX_CLK_DIV CLKDIV_NORMAL, REG_TMP0 + ;wait to have same timing as send_trailer + ldi REG_TMP0, 30 + WAIT REG_TMP0 + .endif + +;reset cyclecount + RESET_CYCLCNT + RET1 ;Reroute data link abort to avoid branching error. datalink_abort_jmp: jmp datalink_abort @@ -726,61 +872,20 @@ datalink_receive_signal_no_error_5: ;modifies: ; REG_TMP0, REG_FNC ;-------------------------------------------------------------------------------------------------- + .if !$defined("HDSL_MULTICHANNEL") send_header: ;push SYNC and first 2 bits of SAMPLE - .if $defined("HDSL_MULTICHANNEL") - ;PUSH 8 bytes for 1 byte data (0x2f) in FIFO - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - -;check if we have an EXTRA period -;if we have a EXTRA period: do TX FIFO synchronization here to gain processing time - qbeq send_header_no_extra_wait, EXTRA_SIZE, 0 -; PUSH 8 bytes for 1 byte data (0xff) in FIFO - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - .else - WAIT_TX_FIFO_FREE PUSH_FIFO_CONST 0x2f ;check if we have an EXTRA period ;if we have a EXTRA period: do TX FIFO synchronization here to gain processing time qbeq send_header_no_extra_wait, EXTRA_SIZE, 0 + WAIT_TX_FIFO_FREE PUSH_FIFO_CONST 0xff - .endif ;HDSL_MULTICHANNEL RESET_CYCLCNT send_header_modified: send_header_no_extra_wait: - - .if $defined("HDSL_MULTICHANNEL") - qbne dont_push_for_non7_hframe,LOOP_CNT.b2,7 - PUSH_FIFO_CONST 0xff -dont_push_for_non7_hframe: - .endif ;calculate EQUALIZATION add DISPARITY, DISPARITY, EXTRA_SIZE qbbs send_header_disp_neg, DISPARITY, 7 @@ -827,10 +932,6 @@ send_header_end_disp: ; V-frame processing is split into two parts : transport_on_v_frame and ; transport_on_v_frame_2. qbne datalink_transport_no_v_frame, LOOP_CNT.b2, 8 - .if $defined("HDSL_MULTICHANNEL") - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0xff - .endif jmp transport_on_v_frame datalink_transport_on_v_frame_done: @@ -838,12 +939,9 @@ datalink_transport_no_v_frame: ; Check if the first H-Frame is complete (and currently the header for second H-Frame ; is being sent). If yes, perform the remaining part of V-frame processing qbne datalink_transport_no_v_frame_2, LOOP_CNT.b2, 7 - .if $defined("HDSL_MULTICHANNEL") - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - .endif + qbbc dont_push_for_non7_hframe_1, H_FRAME.flags, FLAG_NORMAL_FLOW + +dont_push_for_non7_hframe_1: jmp transport_on_v_frame_2 datalink_transport_on_v_frame_done_2: @@ -880,7 +978,6 @@ send_header_extra_not_too_large: qbge send_header_no_cap_stuffing, NUM_STUFFING, MAX_STUFFING ldi NUM_STUFFING, MAX_STUFFING send_header_no_cap_stuffing: - ;qba send_header_encode .if $defined(EXT_SYNC_ENABLE_DEBUG) lbco ®_TMP0, c25, 0, 4 add REG_TMP0,REG_TMP0,4 @@ -905,39 +1002,29 @@ modified_header_wait_done: sub REG_TMP0, REG_TMP0, REG_TMP1 WAIT REG_TMP0 ;reset ECAP INT + send_header_extra_no_wait: - .if !$defined("HDSL_MULTICHANNEL") TX_CLK_DIV CLKDIV_FAST, REG_TMP0 - .endif sub REG_TMP1.b0, EXTRA_SIZE_SELF, 1 + send_header_extra_loop: - .if !$defined("HDSL_MULTICHANNEL") + WAIT_TX_FIFO_FREE - .endif PUSH_FIFO_CONST 0xff sub REG_TMP1.b0, REG_TMP1.b0, 1 qbne send_header_extra_loop, REG_TMP1.b0, 0 ldi REG_TMP0, (11*(CLKDIV_FAST+1)-0) -;send last extra with fine granularity - .if !$defined("HDSL_MULTICHANNEL") WAIT_TX_FIFO_FREE - .endif PUSH_FIFO EXTRA_EDGE_SELF send_header_extra_no_edge: ;reset clock to normal frequency - .if $defined("HDSL_MULTICHANNEL") - mov FIFO_L,REG_TMP11.b0 - PUSH_FIFO_8x FIFO_L - .else WAIT_TX_FIFO_FREE PUSH_FIFO REG_TMP11.b0 ;skip synch pulse measurement if we generate pulse ourself WAIT REG_TMP0 send_header_no_wait_after_synch: TX_CLK_DIV CLKDIV_NORMAL, REG_TMP0 - .endif ;HDSL_MULTICHANNEL - .if $defined(EXT_SYNC_ENABLE) ;**********************************************************************************************; @@ -990,7 +1077,7 @@ send_header_no_wait_after_synch: qbne num_pulses_is_not_one1, NUM_PULSES, 1 ;not the last frame of period lbco ®_TMP0, c1, 0x10, 4 - add REG_TMP0, REG_TMP0, 12 ;read offset + add REG_TMP0, REG_TMP0, 12 ;read offset qbeq adjustment_done, EXTRA_EDGE_SELF, 0xFF is_val_FE: @@ -1032,13 +1119,7 @@ send_header_extra_drive_cycle_check_end: qba send_header_encode send_header_no_extra: ;push last bit of SAMPLE, 3 bits of CYCLE RESET and 4 bits EQUALIZATION - .if $defined("HDSL_MULTICHANNEL") - mov FIFO_L,REG_TMP11.b0 - PUSH_FIFO_2B_8x - PUSH_FIFO_2B_8x - .else PUSH_FIFO REG_TMP11.b0 - .endif ;HDSL_MULTICHANNEL send_header_encode: ;encode data ldi REG_TMP11, (PDMEM00+LUT_5b6b_ENC) @@ -1074,26 +1155,13 @@ send_header_encode_sec_subblock_end: lsr REG_TMP0.b0, REG_FNC.b2, 2 or REG_FNC.b3, REG_FNC.b3, REG_TMP0.b0 lsl REG_FNC.b2, REG_FNC.b2, 6 - .if $defined("HDSL_MULTICHANNEL") - PUSH_FIFO_1_8x - PUSH_FIFO_2_8x - .endif ; transport_layer_send_msg sends short/long message (if pending) and also checks for QMLW/POS errors jmp transport_layer_send_msg -transport_layer_send_msg_done1: - .if $defined("HDSL_MULTICHANNEL") - PUSH_FIFO_2B_8x - PUSH_FIFO_2B_8x - .endif + transport_layer_send_msg_done: ;encoding end - .if $defined("HDSL_MULTICHANNEL") - mov FIFO_L,REG_FNC.b3 - PUSH_FIFO_8x FIFO_L - .else - WAIT_TX_FIFO_FREE + WAIT_TX_FIFO_FREE PUSH_FIFO REG_FNC.b3 - .endif ;HDSL_MULTICHANNEL ;check if we receive or send 01 pattern qbeq send_header_send_01_pattern, REG_FNC.b0, M_PAR_RESET qbeq send_header_send_01_pattern, REG_FNC.b0, M_PAR_SYNC @@ -1104,7 +1172,7 @@ send_header_send_01_pattern: qba send_header_end send_header_dont_send_01: ;send last 2 parameter bits - WAIT_TX_FIFO_FREE + WAIT_TX_FIFO_FREE ;overclock qbbs send_header_dont_send_01_send_1, REG_FNC.b2, 7 PUSH_FIFO_CONST 0x00 @@ -1113,212 +1181,22 @@ send_header_dont_send_01_send_1: PUSH_FIFO_CONST 0xff send_header_dont_send_01_send_next: RESET_CYCLCNT + jmp comp_logic_starts - .if $defined(EXT_SYNC_ENABLE_DEBUG) - lbco ®_TMP0, c25, 0, 4 - add REG_TMP0,REG_TMP0,4 - qble log_done1, REG_TMP0,255 - sbco ®_FNC, c25, REG_TMP0, 4 - sbco ®_TMP0, c25, 0, 4 -log_done1: - .endif +comp_logic_done_1: + qbeq send_header_end_1, REG_FNC.b0, M_PAR_RESET + qbeq send_header_end_1, REG_FNC.b0, M_PAR_SYNC -;HINT: we have some processing time here (~74 cycles) ;6-19:sorry, not anymore, used for ext. sync suppport - -;***********************************************************************************************************; -;pseudocode: -;This code takes care of two things -;1)overhead adjustment per frame -;2)compensation for any diff between the sync pulse captured from latch and extra -;edge fall time computed by PRU - -;/*push in fifo M_PAR data to get time for processing. -;store the default values of extra and stuffing calculated in the beginning, to this we will -;make adjustments as per need*/ -;EXTRA_EDGE_COMP = EXTRA_EDGE -;EXTRA_SIZE_COMP = EXTRA_SIZE -;NUM_STUFFING_COMP = NUM_STUFFING - -;/*note all the time here is in terms of PRU cycle(4.44ns) unless specified*/ -;sync_pulse_rise_time = read_latch1_iep1_capture_register(); -;extra_edge_fall_time = read(); //it was read and stored in memory earliar -;diff_for_compensation = (sync_pulse_rise_time - extra_edge_fall_time)/3; // we have also converted cycles to bit here, by dividing by 3, note these overclocked bits we are talking about -;overhead_adjustment = 8 - TIME_REST_COMP; //coming from last cycle, overhead of child is (8 - parents TIME_REST) -;total_adjustment = (diff_for_compensation + overhead_adjustment); // we take care of sign etc. -;EXTRA_EDGE_COMP = EXTRA_EDGE_COMP (-/+) total_adjustment; //extra size may vary here, if extra_edge is not able to compensate fully -;if(EXTRA_SIZE_COMP < 4) -;{ -; EXTRA_SIZE_COMP = EXTRA_SIZE_COMP + 1; -; NUM_STUFFING_COMP = NUM_STUFFING_COMP - 1; -;} -;if(EXTRA_SIZE_COMP > 9) -;{ -; EXTRA_SIZE_COMP = EXTRA_SIZE_COMP - 1; -; NUM_STUFFING_COMP = NUM_STUFFING_COMP + 1; -;} -;in next cycle these _COMP values will be pushed to fifo and new values will be calculated and so on. -;one point to note here is if you need to adjust num of stuffing you need to do it from one cycle before. -;since stuffng for current cycle is not pushed yet, we can do that. -;that's one strategic importance of keeping this code here. - -comp_logic_starts: - .if $defined(EXT_SYNC_ENABLE) - ;compensation logic for diff between sync signal and extra edge starts; - - qbne num_pulses_is_not_one2, NUM_PULSES, 1 ;not the last frame of period - .if $defined(EXT_SYNC_ENABLE_DEBUG) - lbco ®_TMP0, c25, 0, 4 - add REG_TMP0,REG_TMP0,4 - READ_CYCLCNT REG_TMP1 - sbco ®_TMP1, c25, REG_TMP0, 4 - sbco ®_TMP0, c25, 0, 4 - .endif - mov EXTRA_EDGE_COMP, EXTRA_EDGE - mov EXTRA_SIZE_COMP, EXTRA_SIZE - mov NUM_STUFFING_COMP, NUM_STUFFING - - lbco ®_TMP0, MASTER_REGS_CONST, EXTRA_EDGE_TIMESTAMP, 4 - lbco ®_TMP1, IEP1_BASE_CONST, 0x50, 4 - qbge extra_edge_ahead, REG_TMP1 ,REG_TMP0 - mov REG_TMP2, REG_TMP0 - sub REG_TMP0, REG_TMP1, REG_TMP0 - - .if $defined(EXT_SYNC_ENABLE_DEBUG) - lbco ®_TMP1, c25, 0, 4 - add REG_TMP1,REG_TMP1,4 - qble log_1_done, REG_TMP1, 255 - sbco ®_TMP0, c25, REG_TMP1, 4 - sbco ®_TMP1, c25, 0, 4 -log_1_done: - .endif - ldi REG_TMP2, MAX_ALLOWED_CYCLE_DIFF - qble cycle_diff_more_than_max_allowed, REG_TMP0 ,REG_TMP2 - qbge no_capping1, REG_TMP0 ,CAPPING_CYCLE_DIFF - ldi REG_TMP0 , CAPPING_CYCLE_DIFF - ;qbge compensation_not_needed_this_cycle, REG_TMP0 ,2 - -no_capping1: - mov REG_TMP1, REG_FNC ;taking backup - mov REG_FNC.w0, REG_TMP0 - ldi REG_FNC.w2, 3 - CALL1 int_div - mov REG_TMP0.b0, REG_FNC.b2 - qbeq no_reminder1, REG_FNC.w0, 0 - add REG_TMP0.b0, REG_TMP0.b0,1 -no_reminder1: - mov REG_FNC, REG_TMP1 ;reloading orig value - qba self_overhead_more1 -extra_edge_ahead: - mov REG_TMP2, REG_TMP0 - sub REG_TMP0, REG_TMP0, REG_TMP1 - .if $defined(EXT_SYNC_ENABLE_DEBUG) - lbco ®_TMP1, c25, 0, 4 - add REG_TMP1,REG_TMP1,4 - sbco ®_TMP0, c25, REG_TMP1, 4 - sbco ®_TMP1, c25, 0, 4 - .endif - ldi REG_TMP2, MAX_ALLOWED_CYCLE_DIFF - qble cycle_diff_more_than_max_allowed, REG_TMP0 ,REG_TMP2 - qbge no_capping2, REG_TMP0 ,CAPPING_CYCLE_DIFF - ldi REG_TMP0 , CAPPING_CYCLE_DIFF -no_capping2: - mov REG_TMP1, REG_FNC ;taking backup - mov REG_FNC.w0, REG_TMP0 - ldi REG_FNC.w2, 3 - CALL1 int_div - mov REG_TMP0.b0, REG_FNC.b2 - qbeq no_reminder2, REG_FNC.w0, 0 - add REG_TMP0.b0, REG_TMP0.b0, 1 -no_reminder2: - mov REG_FNC, REG_TMP1 ;reloading orig value - qba child_overhead_more1 -cycle_diff_more_than_max_allowed: - ;halt ;enable to debug jitter out of bound issues - ldi REG_TMP0.b0, 0 ;this is the case of iep wraparound between two readings. happens once in 3-4 hours, let's not waste cycles here - ;by taking care of wraparound calculation, let's just ignore this reading. - -child_overhead_more1: - ldi REG_TMP1.b0, 8 - sub REG_TMP1.b0, REG_TMP1.b0, TIME_REST_COMP - qbne time_rest_comp_not_8_1, REG_TMP1.b0, 8 - ldi REG_TMP1.b0, 0 -time_rest_comp_not_8_1: - mov TIME_REST_COMP, TIME_REST - - add TIME_REST_COMP, TIME_REST_COMP, 16 - sub EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 2 - sub TIME_REST_COMP, TIME_REST_COMP, REG_TMP0.b0 - sub TIME_REST_COMP, TIME_REST_COMP, REG_TMP1.b0 - qba check_time_rest_size_violation1 -self_overhead_more1: - ldi REG_TMP1.b0, 8 - sub REG_TMP1.b0, REG_TMP1.b0, TIME_REST_COMP - qbne time_rest_comp_not_8_2, REG_TMP1.b0, 8 - ldi REG_TMP1.b0, 0 -time_rest_comp_not_8_2: - mov TIME_REST_COMP, TIME_REST - - add TIME_REST_COMP, TIME_REST_COMP, 8 - sub EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 1 - add TIME_REST_COMP, TIME_REST_COMP, REG_TMP0.b0 - - sub TIME_REST_COMP, TIME_REST_COMP, REG_TMP1.b0 - -check_time_rest_size_violation1: - qbge comp_done1, TIME_REST_COMP, 7 - add EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 1 - sub TIME_REST_COMP, TIME_REST_COMP, 8 - qbge comp_done1, TIME_REST_COMP, 7 - add EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 1 - sub TIME_REST_COMP, TIME_REST_COMP, 8 -comp_done1: - mov REG_TMP0.b1, TIME_REST_COMP - ldi EXTRA_EDGE_COMP, 0 - qbeq extra_edge_bit_setting_loop_end1, REG_TMP0.b1, 0 - ldi REG_TMP0.b2, 7 -extra_edge_bit_setting1: - set EXTRA_EDGE_COMP, EXTRA_EDGE_COMP, REG_TMP0.b2 - sub REG_TMP0.b1, REG_TMP0.b1, 1 - sub REG_TMP0.b2, REG_TMP0.b2, 1 - qblt extra_edge_bit_setting1, REG_TMP0.b1, 0 -extra_edge_bit_setting_loop_end1: - mov REG_TMP0.b0, EXTRA_SIZE_COMP - qbeq check_if_extra_remainder, EXTRA_EDGE_COMP, 0 - add REG_TMP0.b0, REG_TMP0.b0, 1 -check_if_extra_remainder: - lbco ®_TMP0.b1, MASTER_REGS_CONST, SYNC_EXTRA_REMAINDER, 1 ;reload ES - qbeq send_header_extra_too_small1, REG_TMP0.b1, 0 - add REG_TMP0.b0, REG_TMP0.b0, 1 ;there is an extra remainder -send_header_extra_too_small1: - qble send_header_extra_not_too_small1, REG_TMP0.b0, 4 ;too small extra window - add EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 6 - sub NUM_STUFFING_COMP, NUM_STUFFING_COMP, 1 -send_header_extra_not_too_small1: - qbge extra_size_validation_done1, REG_TMP0.b0, 9 ;too large extra window - sub EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 6 - add NUM_STUFFING_COMP, NUM_STUFFING_COMP, 1 -extra_size_validation_done1: -num_pulses_is_not_one2: - ;compensation logic for diff between sync signal and extra edge ends; - .endif -;***********************************************************************************************************; -comp_logic_ends: - - qbeq send_header_end, REG_FNC.b0, M_PAR_RESET - qbeq send_header_end, REG_FNC.b0, M_PAR_SYNC - - .if !$defined("HDSL_MULTICHANNEL") qbbc transport_layer_recv_msg_done, H_FRAME.flags, FLAG_NORMAL_FLOW ;HINT: we have processing time here (~168 cycles) jmp transport_layer_recv_msg transport_layer_recv_msg_done: + READ_CYCLCNT REG_TMP1 ldi REG_TMP0, (9*(CLKDIV_NORMAL+1)-9) sub REG_TMP0, REG_TMP0, REG_TMP1 WAIT REG_TMP0 TX_CLK_DIV CLKDIV_FAST, r0 - .endif ;HDSL_MULTICHANNEL - qbbs send_header_dont_send_01_send_11, REG_FNC.b2, 6 PUSH_FIFO_CONST 0x00 ldi LAST_BIT_SENT, 0 @@ -1337,24 +1215,436 @@ send_header_dont_send_01_send_11: sbco ®_TMP2.b0, ICSS_CFGx, EDRXCFG, 1 .endif send_header_dont_send_01_send_next1: - .if $defined("HDSL_MULTICHANNEL") - qbbc transport_layer_recv_msg_done, H_FRAME.flags, FLAG_NORMAL_FLOW + +send_header_sync_wait: +send_header_end_1: + +send_header_end: + RET + .endif +;-------------------------------------------------------------------------------------------------- +;Function: send_header_300m (RET_ADDR) +;This function sends the header (data before slave answer) for 300m PRU clock +;input: +; REG_FNC.w0: parameter channel input +;output: +;modifies: +; REG_TMP0, REG_FNC +;-------------------------------------------------------------------------------------------------- + .if $defined("HDSL_MULTICHANNEL") +send_header_300m: +;push SYNC and first 2 bits of SAMPLE + + ;PUSH 8 bytes for 1 byte data (0x2f) in FIFO + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff +;check if we have an EXTRA period +;if we have a EXTRA period: do TX FIFO synchronization here to gain processing time + qbeq send_header_no_extra_wait, EXTRA_SIZE, 0 + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + RESET_CYCLCNT + +send_header_modified: +send_header_no_extra_wait: + +;calculate EQUALIZATION + add DISPARITY, DISPARITY, EXTRA_SIZE + qbbs send_header_disp_neg, DISPARITY, 7 +send_header_disp_pos: + qblt send_header_disp_pos0, DISPARITY, 1 + ldi REG_TMP11.b0, 0x60 ; 0x6a + qba send_header_end_disp +send_header_disp_pos0: + qblt send_header_disp_pos1, DISPARITY, 3 + ldi REG_TMP11.b0, 0x62 + sub DISPARITY, DISPARITY, 2 + qba send_header_end_disp +send_header_disp_pos1: + ldi REG_TMP11.b0, 0x60 + sub DISPARITY, DISPARITY, 4 + qba send_header_end_disp +send_header_disp_neg: + not REG_TMP11.b0, DISPARITY + add REG_TMP11.b0, REG_TMP11.b0, 1 + qblt send_header_disp_neg0, REG_TMP11.b0, 1 + ldi REG_TMP11.b0, 0x60; 0x6a + qba send_header_end_disp +send_header_disp_neg0: + qblt send_header_disp_neg1, REG_TMP11.b0, 3 + ldi REG_TMP11.b0, 0x6d + add DISPARITY, DISPARITY, 2 + qba send_header_end_disp +send_header_disp_neg1: + ldi REG_TMP11.b0, 0x6f + add DISPARITY, DISPARITY, 4 +send_header_end_disp: +;reset eCAP1 INT + ldi REG_TMP1.w0, (ECAP+ECAP_ECCLR) + ldi REG_TMP1.w2, 0xffff + sbco ®_TMP1.w2, PWMSS1_CONST, REG_TMP1.w0, 2 + ;sbco ®_TMP1.w2, PWMSS2_CONST, REG_TMP1.w0, 2 +;HINT: we have some processing time here (140 cycles) +;go to V-Frame callback on transport layer + qbbc datalink_transport_no_v_frame_2, H_FRAME.flags, FLAG_NORMAL_FLOW +; Check if it V-Frame is complete (and currently the header for first H-Frame is +; being sent) -> state rx0 since we wait for processing v-frame in beginning of +; next frame and not at end of frame in rx7. If yes, start the V-frame +; processing. It will be completed in next H-Frame (State rx1). Therefore the +; V-frame processing is split into two parts : transport_on_v_frame and +; transport_on_v_frame_2. + qbne datalink_transport_no_v_frame, LOOP_CNT.b2, 8 + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0xff + jmp transport_on_v_frame +datalink_transport_on_v_frame_done: + +datalink_transport_no_v_frame: +; Check if the first H-Frame is complete (and currently the header for second H-Frame +; is being sent). If yes, perform the remaining part of V-frame processing + qbne datalink_transport_no_v_frame_2, LOOP_CNT.b2, 7 + qbbc dont_push_for_non7_hframe_1, H_FRAME.flags, FLAG_NORMAL_FLOW + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff +dont_push_for_non7_hframe_1: + jmp transport_on_v_frame_2 + +datalink_transport_on_v_frame_done_2: +datalink_transport_no_v_frame_2: + +;check if we have an EXTRA period + qbeq send_header_no_extra, EXTRA_SIZE, 0 + +;********************************************************************************; + ;extra value decide starts + qbeq num_pulses_is_one3, NUM_PULSES, 1 + mov EXTRA_SIZE_SELF, EXTRA_SIZE + ldi EXTRA_EDGE_SELF, 0 + qba extra_value_decided +num_pulses_is_one3: + mov EXTRA_SIZE_SELF, EXTRA_SIZE_COMP + mov EXTRA_EDGE_SELF, EXTRA_EDGE_COMP +extra_value_decided: + ;extra value decide ends + ;remainder increament logic starts + lbco ®_TMP0.b0, MASTER_REGS_CONST, SYNC_EXTRA_REMAINDER, 1 ;reload ES + qbgt remainder_increament_done1, REG_TMP0.b0, NUM_PULSES + add EXTRA_SIZE_SELF, EXTRA_SIZE_SELF, 1 +remainder_increament_done1: + ;remainder increament logic ends + qbne extra_edge_calculation_for_self_done1, EXTRA_EDGE_SELF, 0 + sub EXTRA_SIZE_SELF, EXTRA_SIZE_SELF, 1 + ldi EXTRA_EDGE_SELF, 0xFF +extra_edge_calculation_for_self_done1: + qba send_header_extra_not_too_large + +send_header_extra_not_too_large: +;limit STUFFING + qbge send_header_no_cap_stuffing, NUM_STUFFING, MAX_STUFFING + ldi NUM_STUFFING, MAX_STUFFING +send_header_no_cap_stuffing: + .if $defined(EXT_SYNC_ENABLE_DEBUG) + lbco ®_TMP0, c25, 0, 4 + add REG_TMP0,REG_TMP0,4 + READ_CYCLCNT REG_TMP1 + ;lbco ®_TMP1, c1, 0x10, 4 + sbco ®_TMP1, c25, REG_TMP0, 4 + sbco ®_TMP0, c25, 0, 4 + .endif + +;read cyclecount + READ_CYCLCNT REG_TMP1 + .if $defined(EXT_SYNC_ENABLE) + qbeq modified_header_wait, MODIFIED_HEADER_STARTED, 1 + ldi REG_TMP0, (9*(CLKDIV_NORMAL+1)-9-4-10) + qba modified_header_wait_done +modified_header_wait: + ldi REG_TMP0, (11*(CLKDIV_NORMAL+1)) +modified_header_wait_done: + .else + ldi REG_TMP0, (9*(CLKDIV_NORMAL+1)-9-4-4) + .endif + sub REG_TMP0, REG_TMP0, REG_TMP1 + +;reset ECAP INT +send_header_extra_no_wait: +; TX_CLK_DIV CLKDIV_FAST, REG_TMP0 + sub REG_TMP1.b0, EXTRA_SIZE_SELF, 1 + +send_header_extra_loop: + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + sub REG_TMP1.b0, REG_TMP1.b0, 1 + qbne send_header_extra_loop, REG_TMP1.b0, 0 + + WAIT_TX_FIFO_FREE + PUSH_FIFO EXTRA_EDGE_SELF +send_header_extra_no_edge: +;reset clock to normal frequency + + .if $defined(EXT_SYNC_ENABLE) + mov FIFO_L,REG_TMP11.b0 + PUSH_FIFO_2B_8x + + .else + mov FIFO_L,REG_TMP11.b0 + PUSH_FIFO_8x FIFO_L + .endif + +send_header_no_wait_after_synch: + + .if $defined(EXT_SYNC_ENABLE) +;**********************************************************************************************; +;pseudo code: +;we just pushed the extra edge so now is the time to take the time capture. +;from the experiments 12 cycle latency for read so adjust for that. +;also one more thing to consider is that EXTRA_EDGE is not always 0xFF. +;It can take values, FF, FC,F8, F0, E0, C0, 80 etc. so we need to adjust for +;that also to get the exact timing of extra edge fall. +; +;iep_time = read_iep(); +;iep_time = iep_time + 12 ; //latency adjustment_done +;if(EXTRA_EDGE == 0xFF) +;{ +; ;do nothing +;} +;if(EXTRA_EDGE == 0xFE) +;{ +; ;each bit in extra edge is 3 pru cycle, simnce here +; ;extra edge came one bit early, so on from other possibilities. +; iep_time = iep_time - 3; +;} +;if(EXTRA_EDGE == 0xFC) +;{ +; iep_time = iep_time - 6; +;} +;if(EXTRA_EDGE == 0xF8) +;{ +; iep_time = iep_time - 9; +;} +;if(EXTRA_EDGE == 0xF0) +;{ +; iep_time = iep_time - 12; +;} +;if(EXTRA_EDGE == 0xE0) +;{ +; iep_time = iep_time - 15; +;} +;if(EXTRA_EDGE == 0xC0) +;{ +; iep_time = iep_time - 18; +;} +;if(EXTRA_EDGE == 0x80) +;{ +; iep_time = iep_time - 21; +;} +;extra_edge_fall_time = iep_time; + + + qbne num_pulses_is_not_one1, NUM_PULSES, 1 ;not the last frame of period + + lbco ®_TMP0, c1, 0x10, 4 + add REG_TMP0, REG_TMP0, 12 ;read offset + + qbeq adjustment_done, EXTRA_EDGE_SELF, 0xFF +is_val_FE: + qbne is_val_FC, EXTRA_EDGE_SELF, 0xFE + sub REG_TMP0, REG_TMP0, 4 + qba adjustment_done +is_val_FC: + qbne is_val_F8, EXTRA_EDGE_SELF, 0xFC + sub REG_TMP0, REG_TMP0, 8 + qba adjustment_done +is_val_F8: + qbne is_val_F0, EXTRA_EDGE_SELF, 0xF8 + sub REG_TMP0, REG_TMP0, 12 + qba adjustment_done +is_val_F0: + qbne is_val_E0, EXTRA_EDGE_SELF, 0xF0 + sub REG_TMP0, REG_TMP0, 16 + qba adjustment_done +is_val_E0: + qbne is_val_C0, EXTRA_EDGE_SELF, 0xE0 + sub REG_TMP0, REG_TMP0, 20 + qba adjustment_done +is_val_C0: + qbne is_val_80, EXTRA_EDGE_SELF, 0xC0 + sub REG_TMP0, REG_TMP0, 24 + qba adjustment_done +is_val_80: + qbne adjustment_done,EXTRA_EDGE_SELF, 0x80 + sub REG_TMP0, REG_TMP0, 28 + qba adjustment_done +adjustment_done: + sbco ®_TMP0, MASTER_REGS_CONST, EXTRA_EDGE_TIMESTAMP, 4 +num_pulses_is_not_one1: + qba send_header_extra_drive_cycle_check_end +;**********************************************************************************************; + .endif + +send_header_extra_drive_cycle_check_end: + qba send_header_encode +send_header_no_extra: +;push last bit of SAMPLE, 3 bits of CYCLE RESET and 4 bits EQUALIZATION + .if !$defined(EXT_SYNC_ENABLE) + mov FIFO_L,REG_TMP11.b0 + PUSH_FIFO_2B_8x + .endif +send_header_encode: + +;encode data + ldi REG_TMP11, (PDMEM00+LUT_5b6b_ENC) + lbbo ®_FNC.b3, REG_TMP11, REG_FNC.b0, 1 + LOOKUP_BITCNT REG_TMP0, REG_FNC.b3 + ldi REG_TMP11, (PDMEM00+LUT_3b4b_ENC) + lbbo ®_FNC.b2, REG_TMP11, REG_FNC.b1, 1 + LOOKUP_BITCNT REG_TMP1, REG_FNC.b2 +;check if subblock polarity is 0 + qbeq send_header_encode_first_subblock_end, REG_TMP0.b0, 3 +;calculate outcoming disparity (due to LUT structure, we lookup always neg. encodings->#0>=#1) +;calculate how many 0s are there more than 1s + lsl REG_TMP0.b0, REG_TMP0.b0, 1 + rsb REG_TMP0.b0, REG_TMP0.b0, 6 +;check line disparity for first block + qbbc send_header_encode_first_subblock_pos, DISPARITY, 7 + xor REG_FNC.b3, REG_FNC.b3, 0x3f + add DISPARITY, DISPARITY, REG_TMP0.b0 + qba send_header_encode_first_subblock_end +send_header_encode_first_subblock_pos: + sub DISPARITY, DISPARITY, REG_TMP0.b0 +send_header_encode_first_subblock_end: +;check line disparity for second block + qbbc send_header_encode_sec_subblock_pos, DISPARITY, 7 +;do not flip if subblock polarity is 0 + qbeq send_header_encode_sec_subblock_pos, REG_TMP1.b0, 2 + xor REG_FNC.b2, REG_FNC.b2, 0x0f + qba send_header_encode_sec_subblock_end +send_header_encode_sec_subblock_pos: +send_header_encode_sec_subblock_end: +;put together + lsl REG_FNC.b3, REG_FNC.b3, 2 + lsr REG_TMP0.b0, REG_FNC.b2, 2 + or REG_FNC.b3, REG_FNC.b3, REG_TMP0.b0 + lsl REG_FNC.b2, REG_FNC.b2, 6 + PUSH_FIFO_1_8x + PUSH_FIFO_2_8x + jmp transport_layer_send_msg + +transport_layer_send_msg_done: +;encoding end + PUSH_FIFO_2B_8x + ;check if we receive or send 01 pattern + qbeq send_header_send_01_pattern, REG_FNC.b0, M_PAR_RESET + qbeq send_header_send_01_pattern, REG_FNC.b0, M_PAR_SYNC + qba send_header_dont_send_01 +send_header_send_01_pattern: + mov FIFO_L,REG_FNC.b3 + PUSH_FIFO_8x FIFO_L +;send 01 pattern + CALL1 send_01 + qba send_header_end +send_header_dont_send_01: + .if $defined(EXT_SYNC_ENABLE_DEBUG) + lbco ®_TMP0, c25, 0, 4 + add REG_TMP0,REG_TMP0,4 + qble log_done1, REG_TMP0,255 + sbco ®_FNC, c25, REG_TMP0, 4 + sbco ®_TMP0, c25, 0, 4 +log_done1: + .endif + qbeq send_header_end_1, REG_FNC.b0, M_PAR_RESET + qbeq send_header_end_1, REG_FNC.b0, M_PAR_SYNC ;HINT: we have processing time here (~168 cycles) + ;check if we reset protocol + lbco &FIFO_L, MASTER_REGS_CONST, SYS_CTRL, 1 +;ERROR: qbbc datalink_abort2 is not working, though no compiler error + qbbc SYS_CTRL_PRST_cleared,FIFO_L, SYS_CTRL_PRST + jmp No_long_short_msg +SYS_CTRL_PRST_cleared: +;check if we reset protocol by reading SAFE_CTRL register + lbco &FIFO_L, MASTER_REGS_CONST, SAFE_CTRL, 1 + qbbc SAFE_CTRL_PRST_cleared, FIFO_L, SAFE_CTRL_PRST + jmp No_long_short_msg + +SAFE_CTRL_PRST_cleared: + mov FIFO_L,CHANNEL.ch_parah + lsr FIFO_L, FIFO_L, 3 + and FIFO_L, FIFO_L, 0x1f + qbeq No_long_short_msg, FIFO_L, S_PAR_IDLE + qbbs No_long_short_msg, H_FRAME.flags, FLAG_WAIT_IDLE + and FIFO_L, H_FRAME.s_par, 0x1f + mov FIFO_L,REG_FNC.b3 + ldi LEARN_STATE_STARTED , 3 + jmp comp_logic_starts +comp_logic_done1: + jmp Push_done + +No_long_short_msg: + mov FIFO_L,REG_FNC.b3 + ldi LEARN_STATE_STARTED , 2 + LOOP push_2B,2 + PUSH_FIFO_2B_8x +push_2B: + jmp comp_logic_starts +Push_done: jmp transport_layer_recv_msg + +comp_logic_done: transport_layer_recv_msg_done: +;send last 2 parameter bits + WAIT_TX_FIFO_FREE +;overclock + qbbs send_header_dont_send_01_send_1, REG_FNC.b2, 7 + PUSH_FIFO_CONST 0x00 + qba send_header_dont_send_01_send_next +send_header_dont_send_01_send_1: + PUSH_FIFO_CONST 0xff +send_header_dont_send_01_send_next: + RESET_CYCLCNT + READ_CYCLCNT REG_TMP1 ldi REG_TMP0, (9*(CLKDIV_NORMAL+1)-9) sub REG_TMP0, REG_TMP0, REG_TMP1 - ;WAIT REG_TMP0 - NOP_2 - NOP_2 - NOP_2 TX_CLK_DIV_WAIT CLKDIV_FAST, r0 -;leave overclocked to be able to reduce transmission delay - .endif ;single channel + qbbs send_header_dont_send_01_send_11, REG_FNC.b2, 6 + PUSH_FIFO_CONST 0x00 + ldi LAST_BIT_SENT, 0 + .if $defined(EXT_SYNC_ENABLE) + ldi REG_TMP2.b0, 0x1F + ;ldi REG_SCRATCH, P0EDRXCFG + sbco ®_TMP2.b0, ICSS_CFGx, EDRXCFG, 1 + .endif + qba send_header_dont_send_01_send_next1 +send_header_dont_send_01_send_11: + PUSH_FIFO_CONST 0xff + ldi LAST_BIT_SENT, 1 + .if $defined(EXT_SYNC_ENABLE) + ldi REG_TMP2.b0, 0x17 + ;ldi REG_SCRATCH, P0EDRXCFG + sbco ®_TMP2.b0, ICSS_CFGx, EDRXCFG, 1 + .endif +send_header_dont_send_01_send_next1: send_header_sync_wait: +send_header_end_1: send_header_end: RET + .endif ;MULTICHANNEL + + + ;-------------------------------------------------------------------------------------------------- ;Function: send_stuffing (RET_ADDR) ;This function sends the trailer (data after slave answer: STUFFING) @@ -1398,6 +1688,7 @@ learn_state_started: rsb REG_TMP2, REG_TMP0, (4*(CLKDIV_NORMAL+1)+4);(6*(CLKDIV_NORMAL+1)+4) calculation_for_wait_done: nop + .else mov REG_TMP11, RET_ADDR1 qbeq send_stuffing_no_stuffing, NUM_STUFFING, 0 @@ -1406,10 +1697,26 @@ calculation_for_wait_done: rsb REG_TMP2, REG_TMP0, (5*(CLKDIV_NORMAL+1)+4);(6*(CLKDIV_NORMAL+1)+4) mov REG_FNC.b3, NUM_STUFFING .endif;EXT_SYNC_ENABLE + .if $defined("HDSL_MULTICHANNEL") + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0x00 + + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0x00 + + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff + .else PUSH_FIFO_CONST 0x0b WAIT REG_TMP2 + .endif + ;send first 4 zeroes with double frequency ;synchronize with clock + .if !$defined("HDSL_MULTICHANNEL") send_stuffing_sync_clk: ;ldi REG_SCRATCH, P0EDTXCFG lbco ®_TMP1, ICSS_CFGx, EDTXCFG, 4 @@ -1422,19 +1729,38 @@ send_stuffing_sync_clk: .if $defined(CHANNEL_0) qbbc send_stuffing_sync_clk, REG_TMP1, 8 .endif + + .endif send_stuffing_first: - .if $defined("HDSL_MULTICHANNEL") - TX_CLK_DIV_WAIT CLKDIV_DOUBLE, REG_TMP1 - .else + .if !$defined("HDSL_MULTICHANNEL") TX_CLK_DIV CLKDIV_DOUBLE, REG_TMP1 - .endif ;HDSL_MULTICHANNEL ;wait 4 cycles ldi REG_FNC.w0, CLKDIV_NORMAL ldi REG_FNC.b2, 4 CALL1 switch_clk + .endif ;HDSL_MULTICHANNEL + sub REG_FNC.b3, REG_FNC.b3, 1 qbeq send_stuffing_no_stuffing, REG_FNC.b3, 0 + .if $defined("HDSL_MULTICHANNEL") +send_stuffing_loop_8x: + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0x00 + + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0x00 + + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0xff + PUSH_FIFO_CONST 0xff + + sub REG_FNC.b3, REG_FNC.b3, 1 + qbne send_stuffing_loop_8x, REG_FNC.b3, 0 + .else + send_stuffing_loop: WAIT_TX_FIFO_FREE PUSH_FIFO_CONST 0x0b @@ -1448,6 +1774,8 @@ send_stuffing_loop: CALL1 switch_clk sub REG_FNC.b3, REG_FNC.b3, 1 qbne send_stuffing_loop, REG_FNC.b3, 0 + + .endif send_stuffing_no_stuffing: mov RET_ADDR1, REG_TMP11 RET1 @@ -1482,10 +1810,11 @@ send_trailer: PUSH_FIFO_CONST 0x00 WAIT_TX_FIFO_FREE PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 PUSH_FIFO_CONST 0xff PUSH_FIFO_CONST 0xff + .else PUSH_FIFO_CONST 0x03 TX_CHANNEL @@ -1529,6 +1858,7 @@ send_trailer_dont_update_qm: .if !$defined("HDSL_MULTICHANNEL") WAIT_CLK_LOW REG_TMP0 .endif + RESET_CYCLCNT RET1 ;-------------------------------------------------------------------------------------------------- @@ -1684,4 +2014,206 @@ calc_rssi: mov RSSI, REG_TMP0.b0 calc_rssi_discard: RET1 + ;-------------------------------------------------------------------------------------------------- +;Function: comp_logic_starts +;Calculates 1)overhead adjustment per frame +; 2)compensation for any diff between the sync pulse captured from latch and extra +; edge fall time computed by PRU +;input: NUM_PULSES,EXTRA_EDGE,EXTRA_SIZE,NUM_STUFFING +;output: Modified EXTRA_SIZE_COMP and NUM_STUFFING_COMP +; +;-------------------------------------------------------------------------------------------------- + + +;HINT: we have some processing time here (~74 cycles) ;6-19:sorry, not anymore, used for ext. sync suppport + +;***********************************************************************************************************; +;pseudocode: +;This code takes care of two things +;1)overhead adjustment per frame +;2)compensation for any diff between the sync pulse captured from latch and extra +;edge fall time computed by PRU + +;/*push in fifo M_PAR data to get time for processing. +;store the default values of extra and stuffing calculated in the beginning, to this we will +;make adjustments as per need*/ +;EXTRA_EDGE_COMP = EXTRA_EDGE +;EXTRA_SIZE_COMP = EXTRA_SIZE +;NUM_STUFFING_COMP = NUM_STUFFING + +;/*note all the time here is in terms of PRU cycle(4.44ns) unless specified*/ +;sync_pulse_rise_time = read_latch1_iep1_capture_register(); +;extra_edge_fall_time = read(); //it was read and stored in memory earliar +;diff_for_compensation = (sync_pulse_rise_time - extra_edge_fall_time)/3; // we have also converted cycles to bit here, by dividing by 3, note these overclocked bits we are talking about +;overhead_adjustment = 8 - TIME_REST_COMP; //coming from last cycle, overhead of child is (8 - parents TIME_REST) +;total_adjustment = (diff_for_compensation + overhead_adjustment); // we take care of sign etc. +;EXTRA_EDGE_COMP = EXTRA_EDGE_COMP (-/+) total_adjustment; //extra size may vary here, if extra_edge is not able to compensate fully +;if(EXTRA_SIZE_COMP < 4) +;{ +; EXTRA_SIZE_COMP = EXTRA_SIZE_COMP + 1; +; NUM_STUFFING_COMP = NUM_STUFFING_COMP - 1; +;} +;if(EXTRA_SIZE_COMP > 9) +;{ +; EXTRA_SIZE_COMP = EXTRA_SIZE_COMP - 1; +; NUM_STUFFING_COMP = NUM_STUFFING_COMP + 1; +;} +;in next cycle these _COMP values will be pushed to fifo and new values will be calculated and so on. +;one point to note here is if you need to adjust num of stuffing you need to do it from one cycle before. +;since stuffng for current cycle is not pushed yet, we can do that. +;that's one strategic importance of keeping this code here. + +comp_logic_starts: + .if $defined(EXT_SYNC_ENABLE) + ;compensation logic for diff between sync signal and extra edge starts; + + qbne num_pulses_is_not_one2, NUM_PULSES, 1 ;not the last frame of period + + mov EXTRA_EDGE_COMP, EXTRA_EDGE + mov EXTRA_SIZE_COMP, EXTRA_SIZE + mov NUM_STUFFING_COMP, NUM_STUFFING + + lbco ®_TMP0, MASTER_REGS_CONST, EXTRA_EDGE_TIMESTAMP, 4 + lbco ®_TMP1, IEP1_BASE_CONST, 0x50, 4 + qbge extra_edge_ahead, REG_TMP1 ,REG_TMP0 + mov REG_TMP2, REG_TMP0 + sub REG_TMP0, REG_TMP1, REG_TMP0 + + + ldi REG_TMP2, MAX_ALLOWED_CYCLE_DIFF + qble cycle_diff_more_than_max_allowed, REG_TMP0 ,REG_TMP2 + qbge no_capping1, REG_TMP0 ,CAPPING_CYCLE_DIFF + ldi REG_TMP0 , CAPPING_CYCLE_DIFF + ;qbge compensation_not_needed_this_cycle, REG_TMP0 ,2 + +no_capping1: + mov REG_TMP1, REG_FNC ;taking backup + mov REG_FNC.w0, REG_TMP0 + ldi REG_FNC.w2, 4;3 + CALL1 int_div + mov REG_TMP0.b0, REG_FNC.b2 + qbeq no_reminder1, REG_FNC.w0, 0 + add REG_TMP0.b0, REG_TMP0.b0,1 +no_reminder1: + mov REG_FNC, REG_TMP1 ;reloading orig value + qba self_overhead_more1 +extra_edge_ahead: + mov REG_TMP2, REG_TMP0 + sub REG_TMP0, REG_TMP0, REG_TMP1 + + ldi REG_TMP2, MAX_ALLOWED_CYCLE_DIFF + qble cycle_diff_more_than_max_allowed, REG_TMP0 ,REG_TMP2 + qbge no_capping2, REG_TMP0 ,CAPPING_CYCLE_DIFF + ldi REG_TMP0 , CAPPING_CYCLE_DIFF +no_capping2: + mov REG_TMP1, REG_FNC ;taking backup + mov REG_FNC.w0, REG_TMP0 + ldi REG_FNC.w2, 4;3 + CALL1 int_div + mov REG_TMP0.b0, REG_FNC.b2 + qbeq no_reminder2, REG_FNC.w0, 0 + add REG_TMP0.b0, REG_TMP0.b0, 1 +no_reminder2: + mov REG_FNC, REG_TMP1 ;reloading orig value + qba child_overhead_more1 +cycle_diff_more_than_max_allowed: + ;halt ;enable to debug jitter out of bound issues + ldi REG_TMP0.b0, 0 ;this is the case of iep wraparound between two readings. happens once in 3-4 hours, let's not waste cycles here + ;by taking care of wraparound calculation, let's just ignore this reading. + +child_overhead_more1: + .if $defined("HDSL_MULTICHANNEL") + PUSH_FIFO_2B_8x + .endif + ldi REG_TMP1.b0, 8 + sub REG_TMP1.b0, REG_TMP1.b0, TIME_REST_COMP + qbne time_rest_comp_not_8_1, REG_TMP1.b0, 8 + ldi REG_TMP1.b0, 0 +time_rest_comp_not_8_1: + mov TIME_REST_COMP, TIME_REST + + add TIME_REST_COMP, TIME_REST_COMP, 16 + sub EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 2 + sub TIME_REST_COMP, TIME_REST_COMP, REG_TMP0.b0 + sub TIME_REST_COMP, TIME_REST_COMP, REG_TMP1.b0 + qba check_time_rest_size_violation1 +self_overhead_more1: + .if $defined("HDSL_MULTICHANNEL") + PUSH_FIFO_2B_8x + .endif + ldi REG_TMP1.b0, 8 + sub REG_TMP1.b0, REG_TMP1.b0, TIME_REST_COMP + qbne time_rest_comp_not_8_2, REG_TMP1.b0, 8 + ldi REG_TMP1.b0, 0 +time_rest_comp_not_8_2: + mov TIME_REST_COMP, TIME_REST + + add TIME_REST_COMP, TIME_REST_COMP, 8 + sub EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 1 + add TIME_REST_COMP, TIME_REST_COMP, REG_TMP0.b0 + + sub TIME_REST_COMP, TIME_REST_COMP, REG_TMP1.b0 + +check_time_rest_size_violation1: + qbge comp_done1, TIME_REST_COMP, 7 + add EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 1 + sub TIME_REST_COMP, TIME_REST_COMP, 8 + qbge comp_done1, TIME_REST_COMP, 7 + add EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 1 + sub TIME_REST_COMP, TIME_REST_COMP, 8 +comp_done1: + mov REG_TMP0.b1, TIME_REST_COMP + ldi EXTRA_EDGE_COMP, 0 + qbeq extra_edge_bit_setting_loop_end1, REG_TMP0.b1, 0 + ldi REG_TMP0.b2, 7 +extra_edge_bit_setting1: + set EXTRA_EDGE_COMP, EXTRA_EDGE_COMP, REG_TMP0.b2 + sub REG_TMP0.b1, REG_TMP0.b1, 1 + sub REG_TMP0.b2, REG_TMP0.b2, 1 + qblt extra_edge_bit_setting1, REG_TMP0.b1, 0 +extra_edge_bit_setting_loop_end1: + mov REG_TMP0.b0, EXTRA_SIZE_COMP + qbeq check_if_extra_remainder, EXTRA_EDGE_COMP, 0 + add REG_TMP0.b0, REG_TMP0.b0, 1 +check_if_extra_remainder: + lbco ®_TMP0.b1, MASTER_REGS_CONST, SYNC_EXTRA_REMAINDER, 1 ;reload ES + qbeq send_header_extra_too_small1, REG_TMP0.b1, 0 + add REG_TMP0.b0, REG_TMP0.b0, 1 ;there is an extra remainder +send_header_extra_too_small1: + qble send_header_extra_not_too_small1, REG_TMP0.b0, 4 ;too small extra window + add EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 6 + sub NUM_STUFFING_COMP, NUM_STUFFING_COMP, 1 +send_header_extra_not_too_small1: + qbge extra_size_validation_done1, REG_TMP0.b0, 9 ;too large extra window + sub EXTRA_SIZE_COMP, EXTRA_SIZE_COMP, 6 + add NUM_STUFFING_COMP, NUM_STUFFING_COMP, 1 +extra_size_validation_done1: +num_pulses_is_not_one2: + .if $defined("HDSL_MULTICHANNEL") + PUSH_FIFO_2B_8x + .endif + .if !$defined("HDSL_MULTICHANNEL") + jmp comp_logic_done_1 + .endif + ;compensation logic for diff between sync signal and extra edge ends; + .else ;free run mode starts + .if $defined("HDSL_MULTICHANNEL") + PUSH_FIFO_2B_8x + PUSH_FIFO_2B_8x + .else + jmp comp_logic_done_1 + .endif + .endif + .if $defined("HDSL_MULTICHANNEL") +comp_logic_ends: + qbeq comp1,LEARN_STATE_STARTED,2 + qbeq comp1,LEARN_STATE_STARTED,3 + ldi LEARN_STATE_STARTED , 1 + jmp comp_logic_done + +comp1: + ldi LEARN_STATE_STARTED , 1 + jmp transport_layer_recv_msg + .endif +;***********************************************************************************************************; diff --git a/source/position_sense/hdsl/firmware/datalink_init.asm b/source/position_sense/hdsl/firmware/datalink_init.asm index 640a3a0..85e00cb 100644 --- a/source/position_sense/hdsl/firmware/datalink_init.asm +++ b/source/position_sense/hdsl/firmware/datalink_init.asm @@ -38,16 +38,26 @@ .ref qm_add .ref calc_rssi .ref send_stuffing + .ref datalink_wait_vsynch + .if $defined("HDSL_MULTICHANNEL") + .ref send_header_300m + .else .ref send_header + .endif + .ref send_header_modified .ref send_trailer .ref wait_delay .ref datalink_loadfw .ref recv_dec - .ref datalink_wait_vsynch + .ref transport_on_h_frame + .ref sync_pulse + .ref check_test_pattern + .ref datalink_abort_jmp + .ref receive + .ref datalink_abort .global datalink_reset .global datalink_init_start - .global send_01 - .global int_div + .sect ".text" @@ -173,30 +183,15 @@ datalink_reset2: ;push first 4 bytes to fill fifo to max level then trigger channel for transmitting data ;later push further bytes in continous fifo load way .if $defined("HDSL_MULTICHANNEL") + LOOP push_1b_0,4 PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 +push_1b_0: TX_CHANNEL + LOOP push_2b_0,6 WAIT_TX_FIFO_FREE PUSH_FIFO_CONST 0x00 PUSH_FIFO_CONST 0x00 - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 - ;Push 8 bytes for single byte 0x00 - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 +push_2b_0: .else PUSH_FIFO_CONST 0x00 @@ -209,7 +204,11 @@ RESET_LOOP: ;loop datalink_reset2_end, 4 ;send m_par_reset 8b/10b: 5b/6b and 3b/4b, first=0,vsync=0,reserved=0 ldi REG_FNC.w0, (0x0000 | M_PAR_RESET) + .if $defined("HDSL_MULTICHANNEL") + CALL send_header_300m + .else CALL send_header + .endif CALL1 send_stuffing add LOOP_CNT_0, LOOP_CNT_0, 1 qbne RESET_LOOP,LOOP_CNT_0,2 @@ -224,7 +223,11 @@ SYNC_LOOP: datalink_sync: ;send m_par_reset 8b/10b: 5b/6b and 3b/4b, first=0,vsync=0,reserved=0 ldi REG_FNC.w0, (0x0000 | M_PAR_SYNC) + .if $defined("HDSL_MULTICHANNEL") + CALL send_header_300m + .else CALL send_header + .endif CALL1 send_stuffing ;TX_CHANNEL datalink_sync_end: @@ -247,7 +250,11 @@ datalink_learn: ;;WAIT_TX_FIFO_FREE ;send m_par_reset 8b/10b: 5b/6b and 3b/4b, first=0,vsync=0,reserved=0 ldi REG_FNC.w0, (0x0000 | M_PAR_START) + .if $defined("HDSL_MULTICHANNEL") + CALL send_header_300m + .else CALL send_header + .endif ; indication of TX_DONE comes about 53ns after wire timing WAIT_TX_DONE .if $defined("FREERUN_300_MHZ") @@ -389,7 +396,9 @@ datalink_learn_recv_loop_final: sub REG_TMP11, r3, REG_TMP2 MOV REG_TMP2.b0, REG_TMP11.b0 ; WAIT subracts -1 from parameter before compare. On 0 it wraps around!!! + WAIT REG_TMP11 + datalink_learn_skip_wait: TX_EN .if $defined("HDSL_MULTICHANNEL") @@ -408,11 +417,10 @@ datalink_learn_skip_wait: .if $defined("HDSL_MULTICHANNEL") PUSH_FIFO_CONST 0x00 TX_CHANNEL + LOOP push_3b_0,3 PUSH_FIFO_CONST 0x00 WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 - WAIT_TX_FIFO_FREE +push_3b_0: PUSH_FIFO_CONST 0xff PUSH_FIFO_CONST 0xff .else @@ -440,14 +448,10 @@ datalink_learn_skip_wait: ldi DISPARITY, 0 ;2 dummy cycles NOP_2 - .if $defined("HDSL_MULTICHANNEL") - TX_CLK_DIV_WAIT CLKDIV_NORMAL, REG_TMP2 - .else + .if !$defined("HDSL_MULTICHANNEL") TX_CLK_DIV CLKDIV_NORMAL, REG_TMP2 .endif -;syn with clock before resetting counter - WAIT_CLK_LOW REG_TMP2 ;reset cycle count RESET_CYCLCNT datalink_learn_pattern: @@ -527,9 +531,9 @@ datalink_learn_delay: or r19.b0, r19.b0, REG_TMP0.b0 lsl r18, r18, 1 ;check pattern + CALL1 check_test_pattern qbeq datalink_abort2, LOOP_CNT.b3, 14 -; qbeq datalink_learn_end_test, LOOP_CNT.b3, 14 qbne datalink_learn_delay, REG_FNC.b0, 1 datalink_learn_end_test: ; SLAVE_DELAY has no switch bit @@ -541,7 +545,6 @@ datalink_learn_end_test: datalink_learn_end: sub LOOP_CNT.b1, LOOP_CNT.b1, 1 qblt datalink_learn, LOOP_CNT.b1, 0 -; qba datalink_abort2_no_wait ;we need a rel. jump here qba datalink_learn2_before ;-------------------------------------------------------------------------------------------------- @@ -549,15 +552,9 @@ datalink_abort2: qbbs datalink_abort2_no_wait, r30, RX_ENABLE ;changed here from 24 to 26 WAIT_TX_DONE .if $defined("FREERUN_300_MHZ") + LOOP no_operation_2cycle,9 NOP_2 - NOP_2 - NOP_2 - NOP_2 - NOP_2 - NOP_2 - NOP_2 - NOP_2 - NOP_2 +no_operation_2cycle: .endif datalink_abort3: datalink_abort2_no_wait: @@ -594,7 +591,11 @@ datalink_learn2: .endif ;send m_par_reset 8b/10b: 5b/6b and 3b/4b, first=0,vsync=0,reserved=0 ldi REG_FNC.w0, (0x0000 | M_PAR_LEARN) + .if $defined("HDSL_MULTICHANNEL") + CALL send_header_300m + .else CALL send_header + .endif CALL receive .if $defined(EXT_SYNC_ENABLE_DEBUG) lbco ®_TMP2, c25, 0, 4 @@ -614,7 +615,11 @@ datalink_learn2_end: ldi LOOP_CNT.b1, 16 datalink_line_check: ldi REG_FNC.w0, (0x0000 | M_PAR_CHECK) + .if $defined("HDSL_MULTICHANNEL") + CALL send_header_300m + .else CALL send_header + .endif CALL receive ;check test pattern CALL1 check_test_pattern @@ -629,7 +634,11 @@ datalink_line_check_end: sbco &SLAVE_DELAY, MASTER_REGS_CONST, DELAY, 1 datalink_id_req: ldi REG_FNC.w0, (0x0000 | M_PAR_IDREQ) + .if $defined("HDSL_MULTICHANNEL") + CALL send_header_300m + .else CALL send_header + .endif CALL recv_dec ;-------------------------------------------------------------------------------------------------- ;State ID STORE @@ -677,219 +686,4 @@ datalink_id_compute: ;qba datalink_id_req CALL1 send_stuffing jmp datalink_wait_vsynch -;-------------------------------------------------------------------------------------------------- -;-------------------------------------------------------------------------------------------------- -;Function: -;This functions receives data without deocoding. -;output: -; r20-r19: data -;-------------------------------------------------------------------------------------------------- -receive: - ldi LOOP_CNT.b0, 32 - CALL1 wait_delay - ldi REG_TMP0.w0, 0 - ldi REG_TMP11, (PDMEM00+0x5a4);LUT_B2B) - zero &r18, (4*5) -datalink_receive_signal_0_31_1: - qbbc datalink_receive_signal_0_31_1, r31, RX_VALID_FLAG - POP_FIFO REG_TMP0.b0 - CLEAR_VAL - sub LOOP_CNT.b0, LOOP_CNT.b0, 1 - qbbc datalink_receive_signal_0_31_received_0_1, REG_TMP0.w0, SAMPLE_EDGE - set r20, r20, LOOP_CNT.b0 -datalink_receive_signal_0_31_received_0_1: - mov REG_TMP0.b1, REG_TMP0.b0 -;get edges - lsr REG_TMP1.b0, REG_TMP0.w0, 1 - xor CUR_EDGES, REG_TMP1.b0, REG_TMP0.b0 - CALL1 calc_rssi - qbne datalink_receive_signal_0_31_1, LOOP_CNT.b0, 0 -;receive next bits - ldi LOOP_CNT.b0, 29 -datalink_receive_signal_32_60_1: - qbbc datalink_receive_signal_32_60_1, r31, RX_VALID_FLAG ;changed here from 24 to 26 - POP_FIFO REG_TMP0.b0 - CLEAR_VAL - sub LOOP_CNT.b0, LOOP_CNT.b0, 1 - qbbc datalink_receive_signal_32_60_received_0_1, REG_TMP0.w0, SAMPLE_EDGE - set r19, r19, LOOP_CNT.b0 -datalink_receive_signal_32_60_received_0_1: - mov REG_TMP0.b1, REG_TMP0.b0 -;get edges - lsr REG_TMP1.b0, REG_TMP0.w0, 1 - xor CUR_EDGES, REG_TMP1.b0, REG_TMP0.b0 - CALL1 calc_rssi - qbne datalink_receive_signal_32_60_1, LOOP_CNT.b0, 1 -datalink_receive_signal_last_1: - qbbc datalink_receive_signal_last_1, r31, RX_VALID_FLAG ;changed here from 24 to 26 - POP_FIFO REG_TMP0.b0 - qbbc datalink_receive_signal_last_received_0_1, REG_TMP0.w0, SAMPLE_EDGE - set r19, r19, 0 -datalink_receive_signal_last_received_0_1: - lsl r19, r19, 3 - CLEAR_VAL -; same delay code as in learn - ldi REG_TMP1, (74*CYCLES_BIT+7) ; -9 for 100 m - READ_CYCLCNT REG_TMP0 - qble receive_skip_wait, REG_TMP0, REG_TMP1 - sub REG_TMP0, REG_TMP1, REG_TMP0 - add r0,r0,1 - WAIT REG_TMP0 -receive_skip_wait: - TX_EN -; datalink_receive_signal_no_delay_wait_1: - CALL1 send_trailer - CALL1 send_stuffing - RET -;-------------------------------------------------------------------------------------------------- -;Function: sync_pulse (RET_ADDR1) -;functions bussy waits for sync pulse -;input: -;modifies: -;-------------------------------------------------------------------------------------------------- -;stores sync pulse period in R20 in unit of cycles -sync_pulse: - lbco ®_TMP1, c1, IEP_CAPR6_RISE, 4 -wait_next_pulse: - lbco &R20, c1, IEP_CAPR6_RISE, 4 - QBEQ wait_next_pulse, R20, REG_TMP1 - SUB R20, R20, REG_TMP1 - RET1 -;-------------------------------------------------------------------------------------------------- -;Function: int_div (RET_ADDR1) -;integer divides -;input: -; REG_FNC.w0: Number -; REG_FNC.w2: Divisor -;output: -; REG_FNC.w2: Result -; REG_FNC.w0: Rest -;modifies: -;-------------------------------------------------------------------------------------------------- -int_div: - ldi REG_TMP0, 0 -int_div_loop: - qbgt int_div_end, REG_FNC.w0, REG_FNC.w2 - sub REG_FNC.w0, REG_FNC.w0, REG_FNC.w2 - add REG_TMP0, REG_TMP0, 1 - qba int_div_loop -int_div_end: - mov REG_FNC.w2, REG_TMP0 - RET1 -;-------------------------------------------------------------------------------------------------- -;Function: check_test_pattern (RET_ADDR1) -;This function checks if the test pattern was received -;input: -; r18-r20: data -;output: -; REG_FNC.b0: 1 if true -;modifies: -; REG_TMP0, REG_FNC -;-------------------------------------------------------------------------------------------------- -check_test_pattern: -;load test pattern and mask from memory - lbco ®_TMP0, MASTER_REGS_CONST, TEST_PATTERN0, 12 -;rm switch bit - and REG_TMP11, r19, REG_TMP2 - ldi REG_TMP2, 0xff8 - and REG_TMP2, r19, REG_TMP2 - lsl REG_TMP2, REG_TMP2, 1 - or REG_TMP11, REG_TMP2, REG_TMP11 -;if found go to next step - qbne check_test_pattern_false, r20, REG_TMP0 - qbne check_test_pattern_false, REG_TMP11, REG_TMP1 -check_test_pattern_true: - ldi REG_FNC.b0, 1 - RET1 -check_test_pattern_false: - ldi REG_FNC.b0, 0 - RET1 -;-------------------------------------------------------------------------------------------------- -;Function: send_01 (RET_ADDR1) -;This function sends 01 pattern in RESET and SYNC state -;input: -; REG_FNC.b2: last two bits of parameter channel -;output: -;modifies: -;-------------------------------------------------------------------------------------------------- -send_01: -;send 01 pattern -;2 para bits, 1 switch bit, 5 slave bit - or REG_FNC.b2, REG_FNC.b2, 0x15;0bPPS10101 - .if $defined("HDSL_MULTICHANNEL") - mov FIFO_L,REG_FNC.b2 - PUSH_FIFO_8x FIFO_L - .else - PUSH_FIFO REG_FNC.b2 - .endif -;56+12 line delay slave bits - ldi REG_TMP0.b0, 8 -send_header_send_01_pattern_loop: - ;;PUSH 8 bytes for 1 byte data (0x55) in FIFO - WAIT_TX_FIFO_FREE - .if $defined("HDSL_MULTICHANNEL") - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0xff - .else - PUSH_FIFO_CONST 0x55 - .endif - sub REG_TMP0.b0, REG_TMP0.b0, 1 - qbne send_header_send_01_pattern_loop, REG_TMP0.b0, 0 -;send last 0101 (4 bits) - WAIT_TX_FIFO_FREE -;overclock(8x) - PUSH_FIFO_CONST 0x00 - ldi REG_TMP0, (9*(CLKDIV_NORMAL+1)-9) - .if !$defined("HDSL_MULTICHANNEL") - WAIT REG_TMP0 - TX_CLK_DIV CLKDIV_FAST, REG_TMP0 - .endif - PUSH_FIFO_CONST 0xff - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0xff -;push TRAILER - ;PUSH 8 bytes for 1 byte data (0x03) in FIFO - WAIT_TX_FIFO_FREE - .if $defined("HDSL_MULTICHANNEL") - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0x00 - PUSH_FIFO_CONST 0x00 - WAIT_TX_FIFO_FREE - PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff - .else - PUSH_FIFO_CONST 0x03 - .endif - .if $defined("FREERUN_300_MHZ") - ldi REG_TMP0, (6*(CLKDIV_FAST+1)-8+2) - .else - ldi REG_TMP0, (6*(CLKDIV_FAST+1)-8) - .endif - .if !$defined("HDSL_MULTICHANNEL") - WAIT REG_TMP0 - TX_CLK_DIV CLKDIV_NORMAL, REG_TMP0 - ;wait to have same timing as send_trailer - ldi REG_TMP0, 30;6 - WAIT REG_TMP0 - .endif - - -;reset cyclecount - RESET_CYCLCNT - RET1 diff --git a/source/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am243x.js b/source/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am243x.js index 6041a21..b07467b 100644 --- a/source/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am243x.js +++ b/source/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am243x.js @@ -48,10 +48,10 @@ const lflags = { }; let postBuildSteps = [ - "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_bin.h Hiperface_DSL2_0 4; move hdsl_master_icssg_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_bin.h ;" - + "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_RTU -o hdsl_master_icssg_freerun_225_mhz_bin.h hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_freerun_225_mhz_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_freerun_225_mhz_bin.h" ]; + const readmeDoxygenPageTag = "HDSL_DESIGN"; const buildOptionCombos = [ diff --git a/source/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am64x.js b/source/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am64x.js index 67dac8b..c7560fd 100644 --- a/source/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am64x.js +++ b/source/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am64x.js @@ -48,8 +48,7 @@ const lflags = { }; let postBuildSteps = [ - "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_bin.h Hiperface_DSL2_0 4; move hdsl_master_icssg_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_bin.h ;" - + "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_RTU -o hdsl_master_icssg_freerun_225_mhz_bin.h hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_freerun_225_mhz_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_freerun_225_mhz_bin.h" ]; const readmeDoxygenPageTag = "HDSL_DESIGN"; diff --git a/source/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec index 27f02a9..f7c2821 100644 --- a/source/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec +++ b/source/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -46,7 +46,7 @@ " postBuildStep=" - $(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_bin.h Hiperface_DSL2_0 4; move hdsl_master_icssg_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_bin.h ; + $(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_RTU -o hdsl_master_icssg_freerun_225_mhz_bin.h hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_freerun_225_mhz_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_freerun_225_mhz_bin.h " description="A Hdsl Master Freerun 225 Mhz FW project"> diff --git a/source/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile index 7128962..6372397 100644 --- a/source/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile +++ b/source/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -108,7 +108,7 @@ clean: -@echo ' ' post-build: - -$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_bin.h Hiperface_DSL2_0 4; move hdsl_master_icssg_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_bin.h + -$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_RTU -o hdsl_master_icssg_freerun_225_mhz_bin.h hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_freerun_225_mhz_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_freerun_225_mhz_bin. -@echo ' ' .PHONY: all clean dependents diff --git a/source/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec index a0dc5f5..eb9d17a 100644 --- a/source/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec +++ b/source/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -46,7 +46,7 @@ " postBuildStep=" - $(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_bin.h Hiperface_DSL2_0 4; move hdsl_master_icssg_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_bin.h ; + $(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_RTU -o hdsl_master_icssg_freerun_225_mhz_bin.h hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_freerun_225_mhz_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_freerun_225_mhz_bin.h " description="A Hdsl Master Freerun 225 Mhz FW project"> diff --git a/source/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile index a1adbd2..3d080d3 100644 --- a/source/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile +++ b/source/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -108,7 +108,7 @@ clean: -@echo ' ' post-build: - -$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_bin.h Hiperface_DSL2_0 4; move hdsl_master_icssg_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_bin.h + -$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_RTU -o hdsl_master_icssg_freerun_225_mhz_bin.h hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_freerun_225_mhz_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_freerun_225_mhz_bin. -@echo ' ' .PHONY: all clean dependents diff --git a/source/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile deleted file mode 100644 index d8b8230..0000000 --- a/source/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile +++ /dev/null @@ -1,117 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -# Required input arguments: -# MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} sdk_dir_path -# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path -# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path - -SHELL = cmd.exe -CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include -CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 -SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg - -GEN_OPTS__FLAG := -GEN_CMDS__FLAG := - -ORDERED_OBJS += \ -"./main.obj" \ -"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd" \ -$(GEN_CMDS__FLAG) \ --llibc.a \ - --include ../makefile.init - -RM := DEL /F -RMDIR := RMDIR /S/Q - -# Every subdirectory with source files must be described here -SUBDIRS := \ -. \ - -# Add inputs and outputs from these tool invocations to the build variables -CMD_SRCS += \ -${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd \ - -ASM_SRCS += \ -${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/freerun_300_mhz/main.asm - -OBJS += \ -./main.obj - -ASM_DEPS += \ -./main.d - -OBJS__QUOTED += \ -"main.obj" - -ASM_DEPS__QUOTED += \ -"main.d" - -ASM_SRCS__QUOTED += \ -"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/freerun_300_mhz/main.asm" - -# Each subdirectory must supply rules for building sources it contributes -main.obj: ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/freerun_300_mhz/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) - @echo 'Building file: "$<"' - @echo 'Invoking: PRU Compiler' - "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( diff --git a/source/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile index 7a52579..5a710c3 100644 --- a/source/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile +++ b/source/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -108,7 +108,7 @@ clean: -@echo ' ' post-build: - -$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_multichannel_ch0_bin.h Hiperface_DSL2_0_RTU 4; move hdsl_master_icssg_multichannel_ch0_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h + -$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_RTU -o hdsl_master_icssg_multichannel_ch0_bin.h hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_multichannel_ch0_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin. -@echo ' ' .PHONY: all clean dependents diff --git a/source/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec index 277913c..1626357 100644 --- a/source/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec +++ b/source/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -48,7 +48,7 @@ " postBuildStep=" - $(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_multichannel_ch0_bin.h Hiperface_DSL2_0_RTU 4; move hdsl_master_icssg_multichannel_ch0_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h ; + $(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_RTU -o hdsl_master_icssg_multichannel_ch0_bin.h hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_multichannel_ch0_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h " description="A Hdsl Master Multichannel Ch0 FW project"> diff --git a/source/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile index 92d8f1f..3a06c56 100644 --- a/source/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile +++ b/source/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -108,7 +108,7 @@ clean: -@echo ' ' post-build: - -$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_multichannel_ch0_bin.h Hiperface_DSL2_0_RTU 4; move hdsl_master_icssg_multichannel_ch0_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h + -$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_RTU -o hdsl_master_icssg_multichannel_ch0_bin.h hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_multichannel_ch0_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin. -@echo ' ' .PHONY: all clean dependents diff --git a/source/position_sense/hdsl/firmware/freerun_300_mhz/.project/project.js b/source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project.js similarity index 100% rename from source/position_sense/hdsl/firmware/freerun_300_mhz/.project/project.js rename to source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project.js diff --git a/source/position_sense/hdsl/firmware/freerun_300_mhz/.project/project_am243x.js b/source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project_am243x.js similarity index 79% rename from source/position_sense/hdsl/firmware/freerun_300_mhz/.project/project_am243x.js rename to source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project_am243x.js index 0b1d9c8..18aba3e 100644 --- a/source/position_sense/hdsl/firmware/freerun_300_mhz/.project/project_am243x.js +++ b/source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project_am243x.js @@ -38,6 +38,8 @@ const defines = { "CHANNEL_0", "ICSS_G_V_1_0", "FREERUN_300_MHZ", + "HDSL_MULTICHANNEL", + "EXT_SYNC_ENABLE", ], }; @@ -49,8 +51,7 @@ const lflags = { }; let postBuildSteps = [ - "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_freerun_300_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_300_mhz_bin.h Hiperface_DSL2_0 4; move hdsl_master_icssg_300_mhz_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h ;" - + "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL_SYNC2_0_RTU -o hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h" ]; const readmeDoxygenPageTag = "HDSL_DESIGN"; @@ -65,7 +66,7 @@ function getComponentProperty() { property.dirPath = path.resolve(__dirname, ".."); property.type = "executable"; property.makefile = "pru"; - property.name = "hdsl_master_freerun_300_mhz"; + property.name = "hdsl_master_multichannel_ch0_sync_mode"; property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 300 MHz"; property.isInternal = false; property.buildOptionCombos = buildOptionCombos; diff --git a/source/position_sense/hdsl/firmware/freerun_300_mhz/.project/project_am64x.js b/source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project_am64x.js similarity index 79% rename from source/position_sense/hdsl/firmware/freerun_300_mhz/.project/project_am64x.js rename to source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project_am64x.js index 6c7e61c..37bd5ff 100644 --- a/source/position_sense/hdsl/firmware/freerun_300_mhz/.project/project_am64x.js +++ b/source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project_am64x.js @@ -38,6 +38,8 @@ const defines = { "CHANNEL_0", "ICSS_G_V_1_0", "FREERUN_300_MHZ", + "HDSL_MULTICHANNEL", + "EXT_SYNC_ENABLE", ], }; @@ -49,8 +51,7 @@ const lflags = { }; let postBuildSteps = [ - "$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_freerun_300_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_300_mhz_bin.h Hiperface_DSL2_0 4; move hdsl_master_icssg_300_mhz_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h ;" - + "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL_SYNC2_0_RTU -o hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h" ]; const readmeDoxygenPageTag = "HDSL_DESIGN"; @@ -65,7 +66,7 @@ function getComponentProperty() { property.dirPath = path.resolve(__dirname, ".."); property.type = "executable"; property.makefile = "pru"; - property.name = "hdsl_master_freerun_300_mhz"; + property.name = "hdsl_master_multichannel_ch0_sync_mode"; property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 300 MHz"; property.isInternal = false; property.buildOptionCombos = buildOptionCombos; diff --git a/source/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec similarity index 77% rename from source/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec rename to source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec index 314142b..3addc97 100644 --- a/source/position_sense/hdsl/firmware/freerun_300_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec +++ b/source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -10,8 +10,8 @@ + description="A Hdsl Master Multichannel Ch0 Sync Mode FW project"> + description="A Hdsl Master Multichannel Ch0 Sync Mode FW project"> diff --git a/source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile index e0e4dee..f21e157 100644 --- a/source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile +++ b/source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -108,7 +108,7 @@ clean: -@echo ' ' post-build: - -$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_multichannel_ch1_bin.h Hiperface_DSL2_0_PRU 4; move hdsl_master_icssg_multichannel_ch1_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h + -$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_PRU -o hdsl_master_icssg_multichannel_ch1_bin.h hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_multichannel_ch1_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin. -@echo ' ' .PHONY: all clean dependents diff --git a/source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec index 1def05b..e3338cc 100644 --- a/source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec +++ b/source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -48,7 +48,7 @@ " postBuildStep=" - $(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_multichannel_ch1_bin.h Hiperface_DSL2_0_PRU 4; move hdsl_master_icssg_multichannel_ch1_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h ; + $(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_PRU -o hdsl_master_icssg_multichannel_ch1_bin.h hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_multichannel_ch1_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h " description="A Hdsl Master Multichannel Ch1 FW project"> diff --git a/source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile index 3a0f379..5a57f2e 100644 --- a/source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile +++ b/source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -108,7 +108,7 @@ clean: -@echo ' ' post-build: - -$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_multichannel_ch1_bin.h Hiperface_DSL2_0_PRU 4; move hdsl_master_icssg_multichannel_ch1_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h + -$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_PRU -o hdsl_master_icssg_multichannel_ch1_bin.h hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_multichannel_ch1_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin. -@echo ' ' .PHONY: all clean dependents diff --git a/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project.js b/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project.js new file mode 100644 index 0000000..7522b8b --- /dev/null +++ b/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project.js @@ -0,0 +1,14 @@ +function getComponentProperty(device) +{ + return require(`./project_${device}`).getComponentProperty(); +}; + +function getComponentBuildProperty(buildOption) +{ + return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption); +}; + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; \ No newline at end of file diff --git a/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project_am243x.js b/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project_am243x.js new file mode 100644 index 0000000..9c4d8f2 --- /dev/null +++ b/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project_am243x.js @@ -0,0 +1,100 @@ +let path = require('path'); + +let device = "am243x"; + +const files = { + common: [ + "main.asm", + "datalink.asm", + "datalink_init.asm", + "transport.asm", + "utils.asm", + "hdsl_master_icssg_hexpru.cmd", + "hdsl_master_icssg.cmd", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware", + ], +}; + +const defines = { + common: [ + "icss1", + "PRU1", + "CHANNEL_1", + "ICSS_G_V_1_0", + "FREERUN_300_MHZ", + "HDSL_MULTICHANNEL", + "EXT_SYNC_ENABLE", + ], +}; + +const lflags = { + common: [ + "--disable_auto_rts", + "--entry_point=main", + ], +}; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL_SYNC2_0_PRU -o hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h" +]; + +const readmeDoxygenPageTag = "HDSL_DESIGN"; + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "hdsl_master_multichannel_ch1_sync_mode"; + property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 300 MHz"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "hdsl_master_icssg"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.postBuildSteps = postBuildSteps; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project_am64x.js b/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project_am64x.js new file mode 100644 index 0000000..f8f5f30 --- /dev/null +++ b/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project_am64x.js @@ -0,0 +1,100 @@ +let path = require('path'); + +let device = "am64x"; + +const files = { + common: [ + "main.asm", + "datalink.asm", + "datalink_init.asm", + "transport.asm", + "utils.asm", + "hdsl_master_icssg_hexpru.cmd", + "hdsl_master_icssg.cmd", + ], +}; + +/* Relative to where the makefile will be generated + * Typically at /// + */ +const filedirs = { + common: [ + "..", /* core_os_combo base */ + "../../..", /* Example base */ + "../../../..", + ], +}; + +const includes = { + common: [ + "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware", + ], +}; + +const defines = { + common: [ + "icss1", + "PRU1", + "CHANNEL_1", + "ICSS_G_V_1_0", + "FREERUN_300_MHZ", + "HDSL_MULTICHANNEL", + "EXT_SYNC_ENABLE", + ], +}; + +const lflags = { + common: [ + "--disable_auto_rts", + "--entry_point=main", + ], +}; + +let postBuildSteps = [ + "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL_SYNC2_0_PRU -o hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h" +]; + +const readmeDoxygenPageTag = "HDSL_DESIGN"; + +const buildOptionCombos = [ + { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"}, +]; + +function getComponentProperty() { + let property = {}; + + property.dirPath = path.resolve(__dirname, ".."); + property.type = "executable"; + property.makefile = "pru"; + property.name = "hdsl_master_multichannel_ch1_sync_mode"; + property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 300 MHz"; + property.isInternal = false; + property.buildOptionCombos = buildOptionCombos; + property.pru_main_file = "main"; + property.pru_linker_file = "hdsl_master_icssg"; + property.isSkipTopLevelBuild = true; + property.skipUpdatingTirex = true; + + return property; +} + +function getComponentBuildProperty(buildOption) { + let build_property = {}; + + build_property.files = files; + build_property.filedirs = filedirs; + build_property.includes = includes; + build_property.defines = defines; + build_property.lflags = lflags; + build_property.readmeDoxygenPageTag = readmeDoxygenPageTag; + build_property.postBuildSteps = postBuildSteps; + build_property.projecspecFileAction = "copy"; + build_property.skipMakefileCcsBootimageGen = true; + + return build_property; +} + +module.exports = { + getComponentProperty, + getComponentBuildProperty, +}; diff --git a/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec new file mode 100644 index 0000000..5433d96 --- /dev/null +++ b/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -0,0 +1,88 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..b843682 --- /dev/null +++ b/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd \ + +ASM_SRCS += \ +${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile new file mode 100644 index 0000000..94fa646 --- /dev/null +++ b/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -0,0 +1,117 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Required input arguments: +# MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} sdk_dir_path +# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path +# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path + +SHELL = cmd.exe +CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include +CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3 +SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./main.obj" \ +"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := DEL /F +RMDIR := RMDIR /S/Q + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + +# Add inputs and outputs from these tool invocations to the build variables +CMD_SRCS += \ +${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/hdsl_master_icssg.cmd \ + +ASM_SRCS += \ +${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/main.asm + +OBJS += \ +./main.obj + +ASM_DEPS += \ +./main.d + +OBJS__QUOTED += \ +"main.obj" + +ASM_DEPS__QUOTED += \ +"main.d" + +ASM_SRCS__QUOTED += \ +"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/main.asm" + +# Each subdirectory must supply rules for building sources it contributes +main.obj: ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: PRU Compiler' + "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $( diff --git a/source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile index 5401fce..2052567 100644 --- a/source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile +++ b/source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -108,7 +108,7 @@ clean: -@echo ' ' post-build: - -$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_sync_bin.h Hiperface_DSL_SYNC2_0 4; move hdsl_master_icssg_sync_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_sync_bin.h + -$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL_SYNC2_0_RTU -o hdsl_master_icssg_sync_225_mhz_bin.h hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_sync_225_mhz_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_sync_225_mhz_bin. -@echo ' ' .PHONY: all clean dependents diff --git a/source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec index 890f4f0..dfbb322 100644 --- a/source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec +++ b/source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec @@ -47,7 +47,7 @@ " postBuildStep=" - $(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_sync_bin.h Hiperface_DSL_SYNC2_0 4; move hdsl_master_icssg_sync_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_sync_bin.h ; + $(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL_SYNC2_0_RTU -o hdsl_master_icssg_sync_225_mhz_bin.h hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_sync_225_mhz_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_sync_225_mhz_bin.h " description="A Hdsl Master Sync 225 Mhz FW project"> diff --git a/source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile index d331752..bf990f5 100644 --- a/source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile +++ b/source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile @@ -108,7 +108,7 @@ clean: -@echo ' ' post-build: - -$(CG_TOOL_ROOT)/bin/hexpru.exe ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/tools/bin2header/bin2header.exe hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.b00 hdsl_master_icssg_sync_bin.h Hiperface_DSL_SYNC2_0 4; move hdsl_master_icssg_sync_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_sync_bin.h + -$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL_SYNC2_0_RTU -o hdsl_master_icssg_sync_225_mhz_bin.h hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out; move hdsl_master_icssg_sync_225_mhz_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_sync_225_mhz_bin. -@echo ' ' .PHONY: all clean dependents diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index 4bfc40a..ef8fa98 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -177,8 +177,10 @@ no_sub_carry: transport_on_v_frame_diff_pos: .if $defined("HDSL_MULTICHANNEL") + WAIT_TX_FIFO_FREE + LOOP push_1B,2 PUSH_FIFO_CONST 0xff - PUSH_FIFO_CONST 0xff +push_1B: .endif ;check for diff. is 0 -> estimate if not @@ -223,7 +225,11 @@ transport_on_v_frame_exit: ;reset rel. pos .if $defined("HDSL_MULTICHANNEL") PUSH_FIFO_CONST 0xff - .endif + qbeq free_run_mode1, EXTRA_SIZE, 0 + PUSH_FIFO_CONST 0xff + RESET_CYCLCNT +free_run_mode1: + .endif ldi REG_TMP0, 0 sbco ®_TMP0, MASTER_REGS_CONST, REL_POS0, 4 ;store last FAST_POS @@ -325,6 +331,20 @@ transport_on_v_frame_2_exit: ; generate interrupt PRU0_ARM_IRQ1 ldi r31.w0, PRU0_ARM_IRQ1 transport_skip_vpos_update: + qbne not_7th_hframe_0, LOOP_CNT.b2, 7 + qbbc not_7th_hframe_0, H_FRAME.flags, FLAG_NORMAL_FLOW + .if $defined("HDSL_MULTICHANNEL") + WAIT_TX_FIFO_FREE + LOOP push_1B_0 ,2 + PUSH_FIFO_CONST 0xff +push_1B_0: + qbeq free_run_mode2, EXTRA_SIZE, 0 + PUSH_FIFO_CONST 0xff + RESET_CYCLCNT +free_run_mode2: + .endif +not_7th_hframe_0: + ; Set POSTX to 3 ldi REG_TMP0.b0, 0x3 sbco ®_TMP0.b0, MASTER_REGS_CONST, POSTX, 1 @@ -419,8 +439,6 @@ transport_layer_recving_long_msg_data_high_nibble: lsl REG_TMP0.b0, REG_TMP2.b0, 4 sbco ®_TMP0.b0, MASTER_REGS_CONST, LONG_MSG_RECV.ptr, 1 - ;160 - qba transport_layer_recving_long_msg_data_nibble_end transport_layer_recving_long_msg_data_low_nibble: @@ -433,7 +451,6 @@ transport_layer_recving_long_msg_data_nibble_end: qba transport_layer_recving_long_msg_end transport_layer_recving_long_msg_crc: ;we are receiving crc - qbne transport_layer_recving_long_msg_end, LONG_MSG_RECV.bits_left, 4 ;set long msg channel to unbusy ; Set EVENT_FREL in EVENT register @@ -478,6 +495,7 @@ transport_layer_check_for_new_msg: qbeq transport_layer_recv_no_msg, REG_TMP0.b0, S_PAR_IDLE qbbs transport_layer_recv_msg_end, H_FRAME.flags, FLAG_WAIT_IDLE ;check for special character + qbbs transport_layer_recv_msg_check_for_nak, REG_TMP0.b0, 4 ;set flag to signalize that we need to wait for next S_PAR_IDLE again, so we do not parse data multiple times set H_FRAME.flags, H_FRAME.flags, FLAG_WAIT_IDLE @@ -501,12 +519,16 @@ transport_layer_check_for_new_msg: lsr REG_TMP2, REG_TMP2, 10 transport_layer_reassemble_msg_loop: ;identify message type - ;jmp transport_layer_received_long_msg qbbs transport_layer_received_long_msg, REG_TMP11.b3, 7 transport_layer_received_short_msg: ;check crc ldi REG_TMP1.b0, &r12.b0 ;read or write? + .if $defined("HDSL_MULTICHANNEL") + WAIT_TX_FIFO_FREE + PUSH_FIFO_1_8x + PUSH_FIFO_2_8x + .endif qbbs transport_layer_short_msg_recv_read, REG_TMP11.b3, 6 ;received write ack ldi REG_FNC.b0, 1 @@ -554,7 +576,6 @@ update_events_no_int10: sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 qba transport_layer_recv_msg_check_for_nak transport_layer_received_long_msg: - ;process long message ;calculate number of bits we still need to receive lsr REG_TMP0.b0, REG_TMP11.b3, 2 @@ -579,6 +600,7 @@ transport_layer_received_long_msg_no_loffset: sbco ®_TMP0.b0, MASTER_REGS_CONST, PC_ADD_H, 2 ;lower two bytes data or crc? ;if crc then dont save to PC_BUFFER + qbeq transport_layer_received_long_msg_no_loffset_crc, LONG_MSG_RECV.bits_left, 0 ;set ptr ldi LONG_MSG_RECV.ptr, 0x22 @@ -602,6 +624,10 @@ update_events_no_int11: sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 clr H_FRAME.flags, H_FRAME.flags, FLAG_PARA_BUSY transport_layer_received_long_msg_loffset_end: + .if $defined("HDSL_MULTICHANNEL") + PUSH_FIFO_1_8x + PUSH_FIFO_2_8x + .endif ;calculate CRC for already recevied bits ldi REG_FNC.b0, 4 ldi r1.b0, &r12.b0 @@ -610,6 +636,7 @@ transport_layer_received_long_msg_loffset_end: ;raise error if long message complete and error qbne transport_layer_resend_msg_end, LONG_MSG_RECV.bits_left, 0 qbeq transport_layer_resend_msg_end, LONG_MSG_RECV.crc, 0 + ; Set EVENT_ANS in EVENT register lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 4 set REG_TMP0.w0, REG_TMP0.w0, EVENT_ANS @@ -697,7 +724,6 @@ transport_layer_resend_msg: transport_layer_resend_msg_read: transport_layer_resend_msg_end: transport_layer_recv_msg_end: - jmp transport_layer_recv_msg_done ;---------------------------------------------------- ;transport_layer_send_msg @@ -968,6 +994,11 @@ transport_on_h_frame: sbco ®_TMP0.b0, MASTER_REGS_CONST, POSTX, 1 ;check for byte error in acceleration channel + .if $defined("HDSL_MULTICHANNEL") + WAIT_TX_FIFO_FREE + PUSH_FIFO_CONST 0x00 + PUSH_FIFO_CONST 0x00 + .endif qbbs transport_acc_err_inc, H_FRAME.flags, FLAG_ERR_ACC ;crc error verification ;CALL1 calc_acc_crc @@ -993,6 +1024,7 @@ transport_acc_err_inc: jmp datalink_abort transport_on_h_frame_no_reset: ;save return addr + mov REG_TMP11.w0, RET_ADDR0 ;CALL estimator_acc; Instead of calling the API, copy the code here to save PRU cycles. ;---------------------------------------------------- diff --git a/source/position_sense/hdsl/makefile.am243x.r5f.ti-arm-clang b/source/position_sense/hdsl/makefile.am243x.r5f.ti-arm-clang index 0ba3b90..4558a06 100644 --- a/source/position_sense/hdsl/makefile.am243x.r5f.ti-arm-clang +++ b/source/position_sense/hdsl/makefile.am243x.r5f.ti-arm-clang @@ -20,13 +20,13 @@ FILES_common := \ hdsl_lut.c \ FILES_PATH_common = \ - driver \ + ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/driver \ INCLUDES_common := \ -I${CG_TOOL_ROOT}/include/c \ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source \ -I${MOTOR_CONTROL_SDK_PATH}/source \ - -Iinclude \ + -I${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/include \ DEFINES_common := \ -DSOC_AM243X \ diff --git a/source/position_sense/hdsl/makefile.am64x.r5f.ti-arm-clang b/source/position_sense/hdsl/makefile.am64x.r5f.ti-arm-clang index 0b652e6..b517448 100644 --- a/source/position_sense/hdsl/makefile.am64x.r5f.ti-arm-clang +++ b/source/position_sense/hdsl/makefile.am64x.r5f.ti-arm-clang @@ -20,13 +20,13 @@ FILES_common := \ hdsl_lut.c \ FILES_PATH_common = \ - driver \ + ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/driver \ INCLUDES_common := \ -I${CG_TOOL_ROOT}/include/c \ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source \ -I${MOTOR_CONTROL_SDK_PATH}/source \ - -Iinclude \ + -I${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/include \ DEFINES_common := \ -DSOC_AM64X \