Pull request #64: am64x/am243x: SDFM: Clock Phase Compensation

Merge in PINDSW/motor_control_sdk from a0502729_PINDSW-5509_SDFM_clock_phase_compensation to next * commit 'fb8dd6371acb26455cf74aff57bee24b606fc9bc': am64x/am243x: SDFM: Clock Phase Compensation
2023-12-13 03:51:39 -06:00 · 2023-12-13 03:51:39 -06:00 · 3420efa0ae
commit 3420efa0ae
parent d7354bf892 fb8dd6371a
52 changed files with 4069 additions and 201 deletions
--- a/.metadata/.tirex/am243x.content.tirex.json
+++ b/.metadata/.tirex/am243x.content.tirex.json
@ -748,6 +748,70 @@
            ]
        ]
    },
+    {
+        "resourceType": "project.ccs",
+        "resourceClass": [
+            "example"
+        ],
+        "resourceSubClass": [
+            "example.general"
+        ],
+        "description": "A Icss Sdfm Three Channel With Phase Compensation Example. CPU is R5FSS0-0 running FREERTOS.",
+        "name": "icss_sdfm_three_channel_with_phase_compensation",
+        "location": "../../examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
+        "devtools": [
+            "AM243x_GP_EVM"
+        ],
+        "kernel": [
+            "freertos"
+        ],
+        "compiler": [
+            "ticlang"
+        ],
+        "subCategories": [
+            "current_sense",
+            "icss_sdfm_three_channel_with_phase_compensation",
+            "r5fss0-0_freertos"
+        ],
+        "mainCategories": [
+            [
+                "Examples",
+                "Development Tools"
+            ]
+        ]
+    },
+    {
+        "resourceType": "project.ccs",
+        "resourceClass": [
+            "example"
+        ],
+        "resourceSubClass": [
+            "example.general"
+        ],
+        "description": "A Icss Sdfm Three Channel With Phase Compensation Example. CPU is R5FSS0-0 running FREERTOS.",
+        "name": "icss_sdfm_three_channel_with_phase_compensation",
+        "location": "../../examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
+        "devtools": [
+            "AM243x_LAUNCHPAD"
+        ],
+        "kernel": [
+            "freertos"
+        ],
+        "compiler": [
+            "ticlang"
+        ],
+        "subCategories": [
+            "current_sense",
+            "icss_sdfm_three_channel_with_phase_compensation",
+            "r5fss0-0_freertos"
+        ],
+        "mainCategories": [
+            [
+                "Examples",
+                "Development Tools"
+            ]
+        ]
+    },
    {
        "resourceType": "project.ccs",
        "resourceClass": [
--- a/.metadata/.tirex/am64x.content.tirex.json
+++ b/.metadata/.tirex/am64x.content.tirex.json
@ -230,38 +230,6 @@
            ]
        ]
    },
-    {
-        "resourceType": "project.ccs",
-        "resourceClass": [
-            "example"
-        ],
-        "resourceSubClass": [
-            "example.general"
-        ],
-        "description": "A Icss Sdfm Example. CPU is R5FSS0-0 running FREERTOS.",
-        "name": "icss_sdfm",
-        "location": "../../examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
-        "devtools": [
-            "AM64x_GP_EVM"
-        ],
-        "kernel": [
-            "freertos"
-        ],
-        "compiler": [
-            "ticlang"
-        ],
-        "subCategories": [
-            "current_sense",
-            "icss_sdfm",
-            "r5fss0-0_freertos"
-        ],
-        "mainCategories": [
-            [
-                "Examples",
-                "Development Tools"
-            ]
-        ]
-    },
    {
        "resourceType": "project.ccs",
        "resourceClass": [
--- a/.project/device/project_am243x.js
+++ b/.project/device/project_am243x.js
@ -29,6 +29,7 @@ const example_file_list = [
    "examples/position_sense/bissc_diagnostic/multi_channel_load_share/.project/project.js",
    "examples/position_sense/bissc_diagnostic/multi_channel_single_pru/.project/project.js",
    "examples/current_sense/icss_sdfm/.project/project.js",
+    "examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/.project/project.js",
    "examples/pruicss_pwm/.project/project.js",
    "source/current_sense/sdfm/firmware/.project/project.js",
    "source/position_sense/endat/firmware/multi_channel_load_share/.project/project.js",
--- a/.project/device/project_am64x.js
+++ b/.project/device/project_am64x.js
@ -21,8 +21,7 @@ const example_file_list = [
    "examples/position_sense/hdsl_diagnostic/multi_channel/.project/project.js",
    "examples/position_sense/hdsl_diagnostic/single_channel/.project/project.js",
    "examples/position_sense/tamagawa_diagnostic/multi_channel/.project/project.js",
-    "examples/position_sense/tamagawa_diagnostic/single_channel/.project/project.js",
-    "examples/current_sense/icss_sdfm/.project/project.js",
+    "examples/position_sense/tamagawa_diagnostic/single_channel/.project/project.js",   
    "examples/pruicss_pwm/.project/project.js",
    "source/current_sense/sdfm/firmware/.project/project.js",
    "source/position_sense/endat/firmware/multi_channel_load_share/.project/project.js",
--- a/docs_src/docs/api_guide/components/current_sense/current_sense.md
+++ b/docs_src/docs/api_guide/components/current_sense/current_sense.md
@ -19,10 +19,10 @@ ICSS %SDFM is a sigma delta interface for phase current measurement in high perf
 - %SDFM Sync with EPWM 
 - Fast detect 
 - PWM Trip generation for overcurrent 
+ - Clock Phase Compensation 

 ## Features Not Supported
 - Zero cross comparator
- Clock phase compensation 
 - Multi-level threshold 

 ## System design considerations
--- a/docs_src/docs/api_guide/components/current_sense/sdfm_design.md
+++ b/docs_src/docs/api_guide/components/current_sense/sdfm_design.md
@ -107,6 +107,13 @@ Here ONE_SAMPLE_TIME is: OSR*(1/SD_CLK)
 The Fast Detect block is used for fast over current detection, it comparatively measures the number of zeros and ones presented in a programmable sliding window of 4 to 32 bits. It starts the comparison after the first 32 sample clocks. Based on the configured zero max/min count limits, it compares zero counter with these limits. If zero counter crosses limit then it sends a error signal to respective PWM Trip zone block.
 PWM TZ block receives this error signal and generates a Trip on TZ_OUT pin.

+#### Data/Clock Phase Compensation 
+Following points describe the process for measurement of phase difference between clock and data
+- Set PRU IO mode to GPIO mode (default) for direct capture of input data and clock pins 
+- First wait for rising edge on the SD data pin, then check the nearest upcoming edge to the SD clock pin. If the nearest edge of clock pin is falling, then it measures the time between the rising edge of the data pin and the falling edge of the SD clock. Otherwise it measures time between the rising edge of both data and clock pins.
+- Based on the clock polarity, phase delay is calculated. If clock polarity and upcoming nearest edge of clock pin for rising edge of data pin are same, then final phase delay will be half SD clock duty cycle time minus calculated time. Otherwise phase delay will be SD clock one cycle period time minus calculated time  
+
+
 #### AM64x/AM243x EVM Pin-Multiplexing
 <table>
 <tr>
@ -244,5 +251,15 @@ PWM TZ block receives this error signal and generates a Trip on TZ_OUT pin.
    <td>PIN_PRG0_PRU0_GPO19
 	<td>(J5.45)TZ output pin for Axis-1
 </tr>
+<tr>
+    <td>PRG1_IEP0_EDC_SYNC_OUT0
+    <td>PIN_PRG1_PRU0_GPO19
+	<td>(J7.63) SYNC_OUT0
+</tr>
+<tr>
+    <td>PRG1_IEP0_EDC_SYNC_OUT1
+    <td>PIN_PRG1_PRU0_GPO17
+	<td>(J7.65) SYNC_OUT1
+</tr>
 </table>
 \endcond
--- a/examples/current_sense/icss_sdfm/app_sdfm.c
+++ b/examples/current_sense/icss_sdfm/app_sdfm.c
@ -398,19 +398,14 @@ void pruSdfmIrqHandler(void *args)
    /* SDFM Output sample for Channel 2 */
    sdfm_ch2_samples[sdfm_ch2_idx++] = SDFM_getFilterData(gHPruSdfm, 2);

-
-     if(sdfm_ch0_idx >= MAX_SAMPLES)
+    if(sdfm_ch0_idx >= MAX_SAMPLES)
    {
        sdfm_ch0_idx = 0;
        sdfm_ch1_idx = 0;
        sdfm_ch2_idx = 0;
    }
-    
-
-
 }

-
 /* EPWM0 IRQ handler */
 static void epwmIrqHandler(void *args)
 {
@ -420,7 +415,7 @@ static void epwmIrqHandler(void *args)
    gEpwmIsrCnt++;

    status = EPWM_etIntrStatus(gEpwm0BaseAddr);
-    if (status & EPWM_ETFLG_INT_MASK) 
+    if(status & EPWM_ETFLG_INT_MASK) 
    {
        EPWM_etIntrClear(gEpwm0BaseAddr);
    }
--- a/examples/current_sense/icss_sdfm/epwm_dc.h
+++ b/examples/current_sense/icss_sdfm/epwm_dc.h
@ -96,9 +96,7 @@ typedef struct _EPwmObj_t
    uint32_t    epwmDutyCycle[EPWM_NUM_OUT_CH];

    uint32_t    epwmPrdVal;         /* EPWM period value */
-
-//    Bool        updateOut;        /* Flag indicates whether to update EPWM A/B outputs */
-
+    
    /* For handling up-down count alternating period
       when period isn't divisible by 2 */
    Bool        toggleEpwmPrd;      /* Flag for EPWM in alternating period mode */
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/.project/project.js
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/.project/project.js
@ -0,0 +1,14 @@
+function getComponentProperty(device)
+{
+    return require(`./project_${device}`).getComponentProperty();
+};
+
+function getComponentBuildProperty(buildOption)
+{
+    return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption);
+};
+
+module.exports = {
+    getComponentProperty,
+    getComponentBuildProperty,
+};
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/.project/project_am243x.js
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/.project/project_am243x.js
@ -1,6 +1,6 @@
 let path = require('path');

-let device = "am64x";
+let device = "am243x";

 const files = {
    common: [
@ -11,6 +11,7 @@ const files = {
        "sdfm.c",
        "cfg_pad.c",
        "main.c",
+        "mclk_iep0_sync.c",
    ],
 };

@ -37,23 +38,22 @@ const includes_freertos_r5f = {
    common: [
        "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include",
        "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F",
-        "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am64x/r5f",
+        "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f",
        "${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include",
-        "${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm",
+        "${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation",
    ],
 };

 const libs_freertos_r5f = {
    common: [
-        "freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
-        "drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
-        "board.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
-        "motorcontrol_sdfm.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
+        "freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+        "drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+        "board.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+        "motorcontrol_sdfm.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
    ],
 };


-
 const lnkfiles = {
    common: [
        "linker.cmd",
@ -67,7 +67,7 @@ const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_SDFM";
 const templates_freertos_r5f =
 [
    {
-        input: ".project/templates/am64x/freertos/main_freertos.c.xdt",
+        input: ".project/templates/am243x/freertos/main_freertos.c.xdt",
        output: "../main.c",
        options: {
            entryFunction: "sdfm_main",
@ -76,7 +76,8 @@ const templates_freertos_r5f =
 ];

 const buildOptionCombos = [
-    { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"},
+    { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-evm", os: "freertos"},
+    { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-lp", os: "freertos"},
 ];

 function getComponentProperty() {
@ -84,7 +85,7 @@ function getComponentProperty() {

    property.dirPath = path.resolve(__dirname, "..");
    property.type = "executable";
-    property.name = "icss_sdfm";
+    property.name = "icss_sdfm_three_channel_with_phase_compensation";
    property.isInternal = false;
    property.buildOptionCombos = buildOptionCombos;
    property.isSkipTopLevelBuild = false;
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/example.syscfg
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/example.syscfg
@ -1,7 +1,7 @@
 /**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
- * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK_AM64X@09.01.00"
+ * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK@09.01.00"
 * @versions {"tool":"1.18.0+3266"}
 */

@ -20,6 +20,7 @@ const gpio6      = gpio.addInstance();
 const gpio7      = gpio.addInstance();
 const pruicss    = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
 const pruicss1   = pruicss.addInstance();
+const pruicss2   = pruicss.addInstance();
 const debug_log  = scripting.addModule("/kernel/dpl/debug_log");
 const mpu_armv7  = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
 const mpu_armv71 = mpu_armv7.addInstance();
@ -34,58 +35,64 @@ const mpu_armv76 = mpu_armv7.addInstance();
 */
 epwm1.$name              = "CONFIG_EPWM0";
 epwm1.EPWM.$assign       = "EHRPWM0";
-epwm1.EPWM.A.$assign     = "ball.U20";
-epwm1.EPWM.B.$assign     = "ball.U18";
-epwm1.EPWM.SYNCO.$assign = "ball.U21";
+epwm1.EPWM.A.$assign     = "GPMC0_AD3";
+epwm1.EPWM.B.$assign     = "GPMC0_AD4";
+epwm1.EPWM.SYNCO.$assign = "GPMC0_AD1";
 epwm1.EPWM.SYNCI.$used   = false;

 gpio1.$name                = "GPIO_MTR_1_PWM_EN";
 gpio1.pinDir               = "OUTPUT";
 gpio1.GPIO.$assign         = "GPIO0";
 gpio1.GPIO.gpioPin.rx      = false;
-gpio1.GPIO.gpioPin.$assign = "ball.Y20";
+gpio1.GPIO.gpioPin.$assign = "GPMC0_AD15";

+gpio2.$name                    = "GPIO_HIGH_TH_CH0";
 gpio2.pinDir                   = "OUTPUT";
 gpio2.useMcuDomainPeripherals  = true;
-gpio2.$name                    = "GPIO_HIGH_TH_CH0";
+gpio2.MCU_GPIO.$assign         = "MCU_GPIO0";
 gpio2.MCU_GPIO.gpioPin.rx      = false;
-gpio2.MCU_GPIO.gpioPin.$assign = "ball.B6";
+gpio2.MCU_GPIO.gpioPin.$assign = "MCU_SPI0_D1";

-gpio3.pinDir                   = "OUTPUT";
 gpio3.$name                    = "GPIO_LOW_TH_CH0";
+gpio3.pinDir                   = "OUTPUT";
 gpio3.useMcuDomainPeripherals  = true;
 gpio3.MCU_GPIO.gpioPin.rx      = false;
-gpio3.MCU_GPIO.gpioPin.$assign = "ball.C7";
+gpio3.MCU_GPIO.gpioPin.$assign = "MCU_SPI1_D0";

 gpio4.$name                    = "GPIO_HIGH_TH_CH1";
 gpio4.pinDir                   = "OUTPUT";
 gpio4.useMcuDomainPeripherals  = true;
 gpio4.MCU_GPIO.gpioPin.rx      = false;
-gpio4.MCU_GPIO.gpioPin.$assign = "ball.A7";
+gpio4.MCU_GPIO.gpioPin.$assign = "MCU_SPI1_CS0";

 gpio5.$name                    = "GPIO_LOW_TH_CH1";
 gpio5.pinDir                   = "OUTPUT";
 gpio5.useMcuDomainPeripherals  = true;
 gpio5.MCU_GPIO.gpioPin.rx      = false;
-gpio5.MCU_GPIO.gpioPin.$assign = "ball.D7";
+gpio5.MCU_GPIO.gpioPin.$assign = "MCU_SPI1_CLK";

 gpio6.$name                    = "GPIO_HIGH_TH_CH2";
 gpio6.pinDir                   = "OUTPUT";
 gpio6.useMcuDomainPeripherals  = true;
-gpio6.MCU_GPIO.gpioPin.rx      = false;
-gpio6.MCU_GPIO.gpioPin.$assign = "ball.C8";
+gpio6.MCU_GPIO.gpioPin.$assign = "MCU_SPI1_D1";

 gpio7.$name                    = "GPIO_LOW_TH_CH2";
 gpio7.pinDir                   = "OUTPUT";
 gpio7.useMcuDomainPeripherals  = true;
 gpio7.MCU_GPIO.gpioPin.rx      = false;
-gpio7.MCU_GPIO.gpioPin.$assign = "ball.E6";
+gpio7.MCU_GPIO.gpioPin.$assign = "MCU_SPI0_CLK";

 pruicss1.$name                           = "CONFIG_PRU_ICSS0";
-pruicss1.iepClk                          = 300000000;
 pruicss1.coreClk                         = 300000000;
+pruicss1.iepClk                          = 300000000;
 pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";

+pruicss2.$name                           = "CONFIG_PRU_ICSS1";
+pruicss2.instance                        = "ICSSG1";
+pruicss2.coreClk                         = 300000000;
+pruicss2.iepClk                          = 300000000;
+pruicss2.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO1";
+
 debug_log.enableUartLog        = true;
 debug_log.uartLog.$name        = "CONFIG_UART_CONSOLE";
 debug_log.uartLog.UART.$assign = "USART0";
@ -124,11 +131,10 @@ mpu_armv76.size     = 31;
 * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
 * re-solve from scratch.
 */
-gpio2.MCU_GPIO.$suggestSolution             = "MCU_GPIO0";
 gpio3.MCU_GPIO.$suggestSolution             = "MCU_GPIO0";
 gpio4.MCU_GPIO.$suggestSolution             = "MCU_GPIO0";
 gpio5.MCU_GPIO.$suggestSolution             = "MCU_GPIO0";
 gpio6.MCU_GPIO.$suggestSolution             = "MCU_GPIO0";
 gpio7.MCU_GPIO.$suggestSolution             = "MCU_GPIO0";
-debug_log.uartLog.UART.RXD.$suggestSolution = "ball.D15";
-debug_log.uartLog.UART.TXD.$suggestSolution = "ball.C16";
+debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD";
+debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD";
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/main.c
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/main.c
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@ -0,0 +1,127 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectSpec>
+    <applicability>
+        <when>
+            <context
+                deviceFamily="ARM"
+                deviceId="Cortex R.AM2434_ALV"
+            />
+        </when>
+    </applicability>
+
+    <project
+        title="Icss Sdfm Three Channel With Phase Compensation"
+        name = "icss_sdfm_three_channel_with_phase_compensation_am243x-evm_r5fss0-0_freertos_ti-arm-clang"
+        products="sysconfig;com.ti.MOTOR_CONTROL_SDK_AMXXX;"
+        configurations="
+                Release,
+                Debug,
+        "
+        connection="TIXDS110_Connection.xml"
+        toolChain="TICLANG"
+        cgtVersion="3.2.0"
+        device="Cortex R.AM2434_ALV"
+        deviceCore="MAIN_PULSAR_Cortex_R5_0_0"
+        ignoreDefaultDeviceSettings="true"
+        ignoreDefaultCCSSettings="true"
+        endianness="little"
+        outputFormat="ELF"
+        outputType="executable"
+
+        compilerBuildOptions="
+            -I${CG_TOOL_ROOT}/include/c
+            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source
+            -I${MOTOR_CONTROL_SDK_PATH}/source
+            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include
+            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F
+            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f
+            -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include
+            -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation
+            -mcpu=cortex-r5
+            -mfloat-abi=hard
+            -mfpu=vfpv3-d16
+            -mthumb
+            -Wall
+            -Werror
+            -g
+            -Wno-gnu-variable-sized-type-not-at-end
+            -Wno-unused-function
+            -DSOC_AM243X
+        "
+        linkerBuildOptions="
+            -i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib
+            -i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib
+            -i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib
+            -i${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/lib
+            -i${CG_TOOL_ROOT}/lib
+            -m=icss_sdfm_three_channel_with_phase_compensation.${ConfigName}.map
+            --diag_suppress=10063
+            --ram_model
+            --reread_libs
+        "
+
+        postBuildStep="$(MAKE) -C ${CCS_PROJECT_DIR} -f makefile_ccs_bootimage_gen OUTNAME=${BuildArtifactFileBaseName} PROFILE=${ConfigName} MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} CG_TOOL_ROOT=${CG_TOOL_ROOT} CCS_INSTALL_DIR=${CCS_INSTALL_DIR} CCS_IDE_MODE=${CCS_IDE_MODE} DEVICE=am243x"
+
+        enableSysConfigTool="true"
+        sysConfigBuildOptions="
+            --context r5fss0-0 --part ALV --package ALV
+        "
+
+        description="A Icss Sdfm Three Channel With Phase Compensation FREERTOS project">
+
+        <configuration name="Release"
+            compilerBuildOptions="
+                -Os
+            "
+            linkerBuildOptions="
+                -lfreertos.am243x.r5f.ti-arm-clang.release.lib
+                -ldrivers.am243x.r5f.ti-arm-clang.release.lib
+                -lboard.am243x.r5f.ti-arm-clang.release.lib
+                -lmotorcontrol_sdfm.am243x.r5f.ti-arm-clang.release.lib
+                -llibc.a
+                -llibsysbm.a
+            "
+        ></configuration>
+        <configuration name="Debug"
+            compilerBuildOptions="
+                -D_DEBUG_=1
+            "
+            linkerBuildOptions="
+                -lfreertos.am243x.r5f.ti-arm-clang.debug.lib
+                -ldrivers.am243x.r5f.ti-arm-clang.debug.lib
+                -lboard.am243x.r5f.ti-arm-clang.debug.lib
+                -lmotorcontrol_sdfm.am243x.r5f.ti-arm-clang.debug.lib
+                -llibc.a
+                -llibsysbm.a
+            "
+        ></configuration>
+        <pathVariable name="MOTOR_CONTROL_SDK_PATH" path="${COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR}" scope="project" />
+        <file path="../../../app_sdfm.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../epwm_dc.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../epwm_drv_aux.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../epwm_mod.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../sdfm.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../cfg_pad.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../main.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../mclk_iep0_sync.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="linker.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../example.syscfg" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am243x/EXAMPLE_MOTORCONTROL_SDFM.html"
+                openOnCreation="false" excludeFromBuild="false" targetName="README.html" action="link">
+        </file>
+        <file path="syscfg_c.rov.xs" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="makefile_ccs_bootimage_gen" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+    </project>
+</projectSpec>
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@ -103,6 +103,9 @@ SECTIONS
    .bss.ipc_vring_mem   (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
    /* General purpose non cacheable memory, used in some examples */
    .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
+
+    /* TCM used by ICSS PRU to write sdfm sample output */
+    .gSdfmSampleOutput       			: {} align(4) > R5F_TCMB0
 }

 /*
@ -142,7 +145,7 @@ MEMORY
    /* On R5F,
     * - make sure there is a MPU entry which maps below regions as non-cache
     */
-    USER_SHM_MEM            : ORIGIN = 0x701D0000, LENGTH = 0x80
-    LOG_SHM_MEM             : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
+    USER_SHM_MEM            : ORIGIN = 0x701D0000, LENGTH = 0x180
+    LOG_SHM_MEM             : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180
    RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
 }
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile
@ -21,17 +21,17 @@ endif
 PROFILE?=release
 ConfigName:=$(PROFILE)

-OUTNAME:=icss_sdfm.$(PROFILE).out
+OUTNAME:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).out

 BOOTIMAGE_PATH=$(abspath .)
-BOOTIMAGE_NAME:=icss_sdfm.$(PROFILE).appimage
-BOOTIMAGE_NAME_XIP:=icss_sdfm.$(PROFILE).appimage_xip
-BOOTIMAGE_NAME_SIGNED:=icss_sdfm.$(PROFILE).appimage.signed
-BOOTIMAGE_RPRC_NAME:=icss_sdfm.$(PROFILE).rprc
-BOOTIMAGE_RPRC_NAME_XIP:=icss_sdfm.$(PROFILE).rprc_xip
-BOOTIMAGE_RPRC_NAME_TMP:=icss_sdfm.$(PROFILE).rprc_tmp
-BOOTIMAGE_NAME_HS:=icss_sdfm.$(PROFILE).appimage.hs
-BOOTIMAGE_NAME_HS_FS:=icss_sdfm.$(PROFILE).appimage.hs_fs
+BOOTIMAGE_NAME:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).appimage
+BOOTIMAGE_NAME_XIP:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).appimage.signed
+BOOTIMAGE_RPRC_NAME:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).rprc_tmp
+BOOTIMAGE_NAME_HS:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).appimage.hs
+BOOTIMAGE_NAME_HS_FS:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).appimage.hs_fs
 TARGETS := $(BOOTIMAGE_NAME)
 ifeq ($(DEVICE_TYPE), HS)
   TARGETS += $(BOOTIMAGE_NAME_HS)
@ -45,6 +45,7 @@ FILES_common := \
 	sdfm.c \
 	cfg_pad.c \
 	main.c \
+	mclk_iep0_sync.c \
 	ti_drivers_config.c \
 	ti_drivers_open_close.c \
 	ti_board_config.c \
@ -64,13 +65,13 @@ INCLUDES_common := \
 	-I${MOTOR_CONTROL_SDK_PATH}/source \
 	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include \
 	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
-	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am64x/r5f \
+	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \
 	-I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include \
-	-I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm \
+	-I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation \
 	-Igenerated \

 DEFINES_common := \
-	-DSOC_AM64X \
+	-DSOC_AM243X \

 CFLAGS_common := \
 	-mcpu=cortex-r5 \
@ -112,10 +113,10 @@ LIBS_PATH_common = \
 	-Wl,-i${CG_TOOL_ROOT}/lib \

 LIBS_common = \
-	-lfreertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-ldrivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-lboard.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
-	-lmotorcontrol_sdfm.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-lmotorcontrol_sdfm.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
 	-llibc.a \
 	-llibsysbm.a \

@ -126,10 +127,10 @@ LFLAGS_common = \


 LIBS_NAME = \
-	freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
-	drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
-	board.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
-	motorcontrol_sdfm.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
+	freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	motorcontrol_sdfm.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
 	libc.a \
 	libsysbm.a \

@ -164,11 +165,11 @@ vpath %.lib $(LIBS_PATH_NAME)
 vpath %.a $(LIBS_PATH_NAME)

 $(OBJDIR)/%.obj %.obj: %.c
-	@echo  Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $<
+	@echo  Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $<
 	$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<

 $(OBJDIR)/%.obj %.obj: %.S
-	@echo  Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $<
+	@echo  Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $<
 	$(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<

 all: $(TARGETS)
@ -182,13 +183,13 @@ SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.

 $(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME)
 	@echo  .
-	@echo  Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ ...
+	@echo  Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ...
 	$(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES)
-	@echo  Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
+	@echo  Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
 	@echo  .

 clean:
-	@echo  Cleaning: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
+	@echo  Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
 	$(RMDIR) $(OBJDIR)
 	$(RM) $(OUTNAME)
 	$(RM) $(BOOTIMAGE_NAME)
@ -201,7 +202,7 @@ clean:
 	$(RMDIR) generated/

 scrub:
-	@echo  Scrubing: am64x:r5fss0-0:freertos:ti-arm-clang icss_sdfm ...
+	@echo  Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang icss_sdfm_three_channel_with_phase_compensation ...
 	$(RMDIR) obj
 ifeq ($(OS),Windows_NT)
 	$(RM) \*.out
@ -233,10 +234,10 @@ $(SYSCFG_GEN_FILES): syscfg

 syscfg: ../example.syscfg
 	@echo Generating SysConfig files ...
-	$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg
+	$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg

 syscfg-gui:
-	$(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device AM64x --context r5fss0-0 --part Default --package ALV --output generated/  ../example.syscfg
+	$(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALV_beta --context r5fss0-0 --part ALV --package ALV --output generated/  ../example.syscfg

 #
 # Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
@ -253,7 +254,6 @@ BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt

 BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)

-BOOTIMAGE_CORE_ID_a53ss0-0 = 0
 BOOTIMAGE_CORE_ID_r5fss0-0 = 4
 BOOTIMAGE_CORE_ID_r5fss0-1 = 5
 BOOTIMAGE_CORE_ID_r5fss1-0 = 6
@ -279,7 +279,7 @@ MULTI_CORE_IMAGE_PARAMS_XIP = \
 	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \

 $(BOOTIMAGE_NAME): $(OUTNAME)
-	@echo  Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
 ifneq ($(OS),Windows_NT)
 	$(CHMOD) a+x $(XIPGEN_CMD)
 endif
@ -293,9 +293,9 @@ endif
 	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
 	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
 	$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
-	@echo  Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!!
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!!
 	@echo  .
-	@echo  Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
 	@echo  .

 $(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME)
@ -309,7 +309,7 @@ else
 	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
 	$(RM) $(BOOTIMAGE_NAME)-enc
 endif
-	@echo  Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
 	@echo  .
 endif
 -include $(addprefix $(OBJDIR)/, $(DEPS))
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@ -44,7 +44,6 @@ else
 endif
 BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt

-BOOTIMAGE_CORE_ID_a53ss0-0 = 0
 BOOTIMAGE_CORE_ID_r5fss0-0 = 4
 BOOTIMAGE_CORE_ID_r5fss0-1 = 5
 BOOTIMAGE_CORE_ID_r5fss1-0 = 6
@ -73,7 +72,7 @@ all:
 ifeq ($(CCS_IDE_MODE),cloud)
 #	No post build steps
 else
-	@echo  Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME)  ...
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME)  ...
 	$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
 	$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
 	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
@ -95,13 +94,13 @@ else
 endif
 endif
 	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
-	@echo  Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
 	@echo  .
 ifeq ($(DEVICE_TYPE),HS)
-	@echo  Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
 	@echo  .
 else
-	@echo  Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
 	@echo  .
 endif
 endif
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
@ -0,0 +1,20 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=icss_sdfm_three_channel_with_phase_compensation_am243x-evm_r5fss0-0_freertos_ti-arm-clang
+
+all:
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+	$(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
@ -4,5 +4,5 @@
 *  View (ROV) tool.
 */
 var crovFiles = [
-    "mcu_plus_sdk/kernel/freertos/rov/FreeRTOS.rov.js",
+    "kernel/freertos/rov/FreeRTOS.rov.js",
 ];
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/example.syscfg
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/example.syscfg
@ -0,0 +1,139 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM243x_ALX_beta" --package "ALX" --part "ALX" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK@09.01.00"
+ * @versions {"tool":"1.18.0+3266"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const epwm       = scripting.addModule("/drivers/epwm/epwm", {}, false);
+const epwm1      = epwm.addInstance();
+const epwm2      = epwm.addInstance();
+const gpio       = scripting.addModule("/drivers/gpio/gpio", {}, false);
+const gpio1      = gpio.addInstance();
+const gpio2      = gpio.addInstance();
+const gpio3      = gpio.addInstance();
+const gpio4      = gpio.addInstance();
+const gpio5      = gpio.addInstance();
+const gpio6      = gpio.addInstance();
+const gpio7      = gpio.addInstance();
+const pruicss    = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
+const pruicss1   = pruicss.addInstance();
+const pruicss2   = pruicss.addInstance();
+const debug_log  = scripting.addModule("/kernel/dpl/debug_log");
+const mpu_armv7  = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
+const mpu_armv71 = mpu_armv7.addInstance();
+const mpu_armv72 = mpu_armv7.addInstance();
+const mpu_armv73 = mpu_armv7.addInstance();
+const mpu_armv74 = mpu_armv7.addInstance();
+const mpu_armv75 = mpu_armv7.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+epwm1.$name            = "CONFIG_EPWM0";
+epwm1.EPWM.$assign     = "EHRPWM0";
+epwm1.EPWM.SYNCI.$used = false;
+
+epwm2.$name              = "CONFIG_EPWM1";
+epwm2.EPWM.SYNCO.$assign = "GPMC0_AD1";
+epwm2.EPWM.SYNCO.$used   = false;
+epwm2.EPWM.SYNCI.$used   = false;
+
+gpio1.$name                    = "GPIO_MTR_1_PWM_EN";
+gpio1.pinDir                   = "OUTPUT";
+gpio1.useMcuDomainPeripherals  = true;
+gpio1.MCU_GPIO.gpioPin.$assign = "MCU_UART0_RXD";
+
+gpio2.pinDir               = "OUTPUT";
+gpio2.$name                = "GPIO_HIGH_TH_CH0";
+gpio2.GPIO.$assign         = "GPIO0";
+gpio2.GPIO.gpioPin.rx      = false;
+gpio2.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO18";
+
+gpio3.$name                = "GPIO_LOW_TH_CH0";
+gpio3.pinDir               = "OUTPUT";
+gpio3.GPIO.gpioPin.rx      = false;
+gpio3.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO11";
+
+gpio4.pinDir               = "OUTPUT";
+gpio4.$name                = "GPIO_HIGH_TH_CH1";
+gpio4.GPIO.$assign         = "GPIO0";
+gpio4.GPIO.gpioPin.rx      = false;
+gpio4.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO17";
+
+gpio5.$name                = "GPIO_LOW_TH_CH1";
+gpio5.pinDir               = "OUTPUT";
+gpio5.GPIO.$assign         = "GPIO0";
+gpio5.GPIO.gpioPin.rx      = false;
+gpio5.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO7";
+
+gpio6.pinDir               = "OUTPUT";
+gpio6.$name                = "GPIO_HIGH_TH_CH2";
+gpio6.GPIO.gpioPin.rx      = false;
+gpio6.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO1";
+
+gpio7.$name                = "GPIO_LOW_TH_CH2";
+gpio7.pinDir               = "OUTPUT";
+gpio7.GPIO.gpioPin.rx      = false;
+gpio7.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO2";
+
+pruicss1.$name                           = "CONFIG_PRU_ICSS0";
+pruicss1.coreClk                         = 300000000;
+pruicss1.iepClk                          = 300000000;
+pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
+
+pruicss2.$name                           = "CONFIG_PRU_ICSS1";
+pruicss2.instance                        = "ICSSG1";
+pruicss2.coreClk                         = 300000000;
+pruicss2.iepClk                          = 300000000;
+pruicss2.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO1";
+
+debug_log.enableUartLog        = true;
+debug_log.uartLog.$name        = "CONFIG_UART_CONSOLE";
+debug_log.uartLog.UART.$assign = "USART0";
+
+mpu_armv71.$name             = "CONFIG_MPU_REGION0";
+mpu_armv71.size              = 31;
+mpu_armv71.attributes        = "Device";
+mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv71.allowExecute      = false;
+
+mpu_armv72.$name             = "CONFIG_MPU_REGION1";
+mpu_armv72.size              = 15;
+mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv73.$name             = "CONFIG_MPU_REGION2";
+mpu_armv73.baseAddr          = 0x41010000;
+mpu_armv73.size              = 15;
+mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv74.$name             = "CONFIG_MPU_REGION3";
+mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv74.baseAddr          = 0x70000000;
+mpu_armv74.size              = 21;
+
+mpu_armv75.$name             = "CONFIG_MPU_REGION4";
+mpu_armv75.baseAddr          = 0x60000000;
+mpu_armv75.size              = 28;
+mpu_armv75.accessPermissions = "Supervisor RD, User RD";
+
+/**
+ * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
+ * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
+ * re-solve from scratch.
+ */
+epwm1.EPWM.A.$suggestSolution               = "GPMC0_AD3";
+epwm1.EPWM.B.$suggestSolution               = "GPMC0_AD4";
+epwm1.EPWM.SYNCO.$suggestSolution           = "GPMC0_AD1";
+epwm2.EPWM.$suggestSolution                 = "EHRPWM1";
+epwm2.EPWM.A.$suggestSolution               = "GPMC0_AD5";
+epwm2.EPWM.B.$suggestSolution               = "GPMC0_AD6";
+gpio1.MCU_GPIO.$suggestSolution             = "MCU_GPIO0";
+gpio3.GPIO.$suggestSolution                 = "GPIO1";
+gpio6.GPIO.$suggestSolution                 = "GPIO1";
+gpio7.GPIO.$suggestSolution                 = "GPIO1";
+debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD";
+debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD";
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/main.c
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/main.c
@ -0,0 +1,84 @@
+/*
+ *  Copyright (C) 2018-2021 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdlib.h>
+#include <kernel/dpl/DebugP.h>
+#include "ti_drivers_config.h"
+#include "ti_board_config.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define MAIN_TASK_PRI  (configMAX_PRIORITIES-1)
+
+#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE))
+StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
+
+StaticTask_t gMainTaskObj;
+TaskHandle_t gMainTask;
+
+void sdfm_main(void *args);
+
+void freertos_main(void *args)
+{
+    sdfm_main(NULL);
+
+    vTaskDelete(NULL);
+}
+
+
+int main(void)
+{
+    /* init SOC specific modules */
+    System_init();
+    Board_init();
+
+    /* This task is created at highest priority, it should create more tasks and then delete itself */
+    gMainTask = xTaskCreateStatic( freertos_main,   /* Pointer to the function that implements the task. */
+                                  "freertos_main", /* Text name for the task.  This is to facilitate debugging only. */
+                                  MAIN_TASK_SIZE,  /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
+                                  NULL,            /* We are not using the task parameter. */
+                                  MAIN_TASK_PRI,   /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
+                                  gMainTaskStack,  /* pointer to stack base */
+                                  &gMainTaskObj ); /* pointer to statically allocated task object memory */
+    configASSERT(gMainTask != NULL);
+
+    /* Start the scheduler to start the tasks executing. */
+    vTaskStartScheduler();
+
+    /* The following line should never be reached because vTaskStartScheduler()
+    will only return if there was not enough FreeRTOS heap memory available to
+    create the Idle and (if configured) Timer tasks.  Heap management, and
+    techniques for trapping heap exhaustion, are described in the book text. */
+    DebugP_assertNoLog(0);
+
+    return 0;
+}
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@ -4,14 +4,14 @@
        <when>
            <context
                deviceFamily="ARM"
-                deviceId="Cortex R.AM64x"
+                deviceId="Cortex R.AM2434_ALX"
            />
        </when>
    </applicability>

    <project
-        title="Icss Sdfm"
-        name = "icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang"
+        title="Icss Sdfm Three Channel With Phase Compensation"
+        name = "icss_sdfm_three_channel_with_phase_compensation_am243x-lp_r5fss0-0_freertos_ti-arm-clang"
        products="sysconfig;com.ti.MOTOR_CONTROL_SDK_AMXXX;"
        configurations="
                Release,
@ -20,7 +20,7 @@
        connection="TIXDS110_Connection.xml"
        toolChain="TICLANG"
        cgtVersion="3.2.0"
-        device="Cortex R.AM64x"
+        device="Cortex R.AM2434_ALX"
        deviceCore="MAIN_PULSAR_Cortex_R5_0_0"
        ignoreDefaultDeviceSettings="true"
        ignoreDefaultCCSSettings="true"
@ -34,9 +34,9 @@
            -I${MOTOR_CONTROL_SDK_PATH}/source
            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include
            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F
-            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am64x/r5f
+            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f
            -I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include
-            -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm
+            -I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation
            -mcpu=cortex-r5
            -mfloat-abi=hard
            -mfpu=vfpv3-d16
@ -46,7 +46,7 @@
            -g
            -Wno-gnu-variable-sized-type-not-at-end
            -Wno-unused-function
-            -DSOC_AM64X
+            -DSOC_AM243X
        "
        linkerBuildOptions="
            -i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib
@ -54,30 +54,30 @@
            -i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib
            -i${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/lib
            -i${CG_TOOL_ROOT}/lib
-            -m=icss_sdfm.${ConfigName}.map
+            -m=icss_sdfm_three_channel_with_phase_compensation.${ConfigName}.map
            --diag_suppress=10063
            --ram_model
            --reread_libs
        "

-        postBuildStep="$(MAKE) -C ${CCS_PROJECT_DIR} -f makefile_ccs_bootimage_gen OUTNAME=${BuildArtifactFileBaseName} PROFILE=${ConfigName} MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} CG_TOOL_ROOT=${CG_TOOL_ROOT} CCS_INSTALL_DIR=${CCS_INSTALL_DIR} CCS_IDE_MODE=${CCS_IDE_MODE} DEVICE=am64x"
+        postBuildStep="$(MAKE) -C ${CCS_PROJECT_DIR} -f makefile_ccs_bootimage_gen OUTNAME=${BuildArtifactFileBaseName} PROFILE=${ConfigName} MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} CG_TOOL_ROOT=${CG_TOOL_ROOT} CCS_INSTALL_DIR=${CCS_INSTALL_DIR} CCS_IDE_MODE=${CCS_IDE_MODE} DEVICE=am243x"

        enableSysConfigTool="true"
        sysConfigBuildOptions="
-            --context r5fss0-0 --part Default --package ALV
+            --context r5fss0-0 --part ALX --package ALX
        "

-        description="A Icss Sdfm FREERTOS project">
+        description="A Icss Sdfm Three Channel With Phase Compensation FREERTOS project">

        <configuration name="Release"
            compilerBuildOptions="
                -Os
            "
            linkerBuildOptions="
-                -lfreertos.am64x.r5f.ti-arm-clang.release.lib
-                -ldrivers.am64x.r5f.ti-arm-clang.release.lib
-                -lboard.am64x.r5f.ti-arm-clang.release.lib
-                -lmotorcontrol_sdfm.am64x.r5f.ti-arm-clang.release.lib
+                -lfreertos.am243x.r5f.ti-arm-clang.release.lib
+                -ldrivers.am243x.r5f.ti-arm-clang.release.lib
+                -lboard.am243x.r5f.ti-arm-clang.release.lib
+                -lmotorcontrol_sdfm.am243x.r5f.ti-arm-clang.release.lib
                -llibc.a
                -llibsysbm.a
            "
@ -87,10 +87,10 @@
                -D_DEBUG_=1
            "
            linkerBuildOptions="
-                -lfreertos.am64x.r5f.ti-arm-clang.debug.lib
-                -ldrivers.am64x.r5f.ti-arm-clang.debug.lib
-                -lboard.am64x.r5f.ti-arm-clang.debug.lib
-                -lmotorcontrol_sdfm.am64x.r5f.ti-arm-clang.debug.lib
+                -lfreertos.am243x.r5f.ti-arm-clang.debug.lib
+                -ldrivers.am243x.r5f.ti-arm-clang.debug.lib
+                -lboard.am243x.r5f.ti-arm-clang.debug.lib
+                -lmotorcontrol_sdfm.am243x.r5f.ti-arm-clang.debug.lib
                -llibc.a
                -llibsysbm.a
            "
@ -110,11 +110,13 @@
        </file>
        <file path="../main.c" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
+        <file path="../../../mclk_iep0_sync.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
        <file path="linker.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
        <file path="../example.syscfg" openOnCreation="false" excludeFromBuild="false" action="copy">
        </file>
-        <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am64x/EXAMPLE_MOTORCONTROL_SDFM.html"
+        <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am243x/EXAMPLE_MOTORCONTROL_SDFM.html"
                openOnCreation="false" excludeFromBuild="false" targetName="README.html" action="link">
        </file>
        <file path="syscfg_c.rov.xs" openOnCreation="false" excludeFromBuild="false" action="copy">
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@ -0,0 +1,151 @@
+
+/* This is the stack that is used by code running within main()
+ * In case of NORTOS,
+ * - This means all the code outside of ISR uses this stack
+ * In case of FreeRTOS
+ * - This means all the code until vTaskStartScheduler() is called in main()
+ *   uses this stack.
+ * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
+ */
+--stack_size=16384
+/* This is the heap size for malloc() API in NORTOS and FreeRTOS
+ * This is also the heap used by pvPortMalloc in FreeRTOS
+ */
+--heap_size=32768
+-e_vectors  /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
+
+/* This is the size of stack when R5 is in IRQ mode
+ * In NORTOS,
+ * - Here interrupt nesting is enabled
+ * - This is the stack used by ISRs registered as type IRQ
+ * In FreeRTOS,
+ * - Here interrupt nesting is disabled
+ * - This is stack that is used initally when a IRQ is received
+ * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
+ * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
+ */
+__IRQ_STACK_SIZE = 256;
+/* This is the size of stack when R5 is in IRQ mode
+ * - In both NORTOS and FreeRTOS nesting is disabled for FIQ
+ */
+__FIQ_STACK_SIZE = 256;
+__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
+__ABORT_STACK_SIZE = 256;  /* This is the size of stack when R5 is in ABORT mode */
+__UNDEFINED_STACK_SIZE = 256;  /* This is the size of stack when R5 is in UNDEF mode */
+
+SECTIONS
+{
+    /* This has the R5F entry point and vector table, this MUST be at 0x0 */
+    .vectors:{} palign(8) > R5F_VECS
+
+    /* This has the R5F boot code until MPU is enabled,  this MUST be at a address < 0x80000000
+     * i.e this cannot be placed in DDR
+     */
+    GROUP {
+        .text.hwi: palign(8)
+        .text.cache: palign(8)
+        .text.mpu: palign(8)
+        .text.boot: palign(8)
+        .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
+    } > MSRAM
+
+    /* This is rest of code. This can be placed in DDR if DDR is available and needed */
+    GROUP {
+        .text:   {} palign(8)   /* This is where code resides */
+        .rodata: {} palign(8)   /* This is where const's go */
+    } > MSRAM
+
+    /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
+    GROUP {
+        .data:   {} palign(8)   /* This is where initialized globals and static go */
+    } > MSRAM
+
+    /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
+    GROUP {
+        .bss:    {} palign(8)   /* This is where uninitialized globals go */
+        RUN_START(__BSS_START)
+        RUN_END(__BSS_END)
+        .sysmem: {} palign(8)   /* This is where the malloc heap goes */
+        .stack:  {} palign(8)   /* This is where the main() stack goes */
+    } > MSRAM
+
+    /* This is where the stacks for different R5F modes go */
+    GROUP {
+        .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
+        RUN_START(__IRQ_STACK_START)
+        RUN_END(__IRQ_STACK_END)
+        .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
+        RUN_START(__FIQ_STACK_START)
+        RUN_END(__FIQ_STACK_END)
+        .svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
+        RUN_START(__SVC_STACK_START)
+        RUN_END(__SVC_STACK_END)
+        .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
+        RUN_START(__ABORT_STACK_START)
+        RUN_END(__ABORT_STACK_END)
+        .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
+        RUN_START(__UNDEFINED_STACK_START)
+        RUN_END(__UNDEFINED_STACK_END)
+    } > MSRAM
+
+    /* Sections needed for C++ projects */
+    GROUP {
+        .ARM.exidx:  {} palign(8)   /* Needed for C++ exception handling */
+        .init_array: {} palign(8)   /* Contains function pointers called before main */
+        .fini_array: {} palign(8)   /* Contains function pointers called after main */
+    } > MSRAM
+
+    /* General purpose user shared memory, used in some examples */
+    .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
+    /* this is used when Debug log's to shared memory are enabled, else this is not used */
+    .bss.log_shared_mem  (NOLOAD) : {} > LOG_SHM_MEM
+    /* this is used only when IPC RPMessage is enabled, else this is not used */
+    .bss.ipc_vring_mem   (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
+    /* General purpose non cacheable memory, used in some examples */
+    .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
+
+    /* TCM used by ICSS PRU to write sdfm sample output */
+    .gSdfmSampleOutput       			: {} align(4) > R5F_TCMB0
+}
+
+/*
+NOTE: Below memory is reserved for DMSC usage
+ - During Boot till security handoff is complete
+   0x701E0000 - 0x701FFFFF (128KB)
+ - After "Security Handoff" is complete (i.e at run time)
+   0x701F4000 - 0x701FFFFF (48KB)
+
+ Security handoff is complete when this message is sent to the DMSC,
+   TISCI_MSG_SEC_HANDOVER
+
+ This should be sent once all cores are loaded and all application
+ specific firewall calls are setup.
+*/
+
+MEMORY
+{
+    R5F_VECS  : ORIGIN = 0x00000000 , LENGTH = 0x00000040
+    R5F_TCMA  : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
+    R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+
+    /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
+    NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
+
+    /* when using multi-core application's i.e more than one R5F/M4F active, make sure
+     * this memory does not overlap with other R5F's
+     */
+    MSRAM     : ORIGIN = 0x70080000 , LENGTH = 0x40000
+
+    /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
+     * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
+     */
+    FLASH     : ORIGIN = 0x60100000 , LENGTH = 0x80000
+
+    /* shared memory segments */
+    /* On R5F,
+     * - make sure there is a MPU entry which maps below regions as non-cache
+     */
+    USER_SHM_MEM            : ORIGIN = 0x701D0000, LENGTH = 0x180
+    LOG_SHM_MEM             : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180
+    RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
+}
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
@ -0,0 +1,315 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak
+
+CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
+
+CC=$(CG_TOOL_ROOT)/bin/tiarmclang
+LNK=$(CG_TOOL_ROOT)/bin/tiarmclang
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+	PYTHON=python
+else
+	PYTHON=python3
+endif
+
+PROFILE?=release
+ConfigName:=$(PROFILE)
+
+OUTNAME:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).out
+
+BOOTIMAGE_PATH=$(abspath .)
+BOOTIMAGE_NAME:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).appimage
+BOOTIMAGE_NAME_XIP:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).appimage.signed
+BOOTIMAGE_RPRC_NAME:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).rprc_tmp
+BOOTIMAGE_NAME_HS:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).appimage.hs
+BOOTIMAGE_NAME_HS_FS:=icss_sdfm_three_channel_with_phase_compensation.$(PROFILE).appimage.hs_fs
+TARGETS := $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_HS)
+endif
+
+FILES_common := \
+	app_sdfm.c \
+	epwm_dc.c \
+	epwm_drv_aux.c \
+	epwm_mod.c \
+	sdfm.c \
+	cfg_pad.c \
+	main.c \
+	mclk_iep0_sync.c \
+	ti_drivers_config.c \
+	ti_drivers_open_close.c \
+	ti_board_config.c \
+	ti_board_open_close.c \
+	ti_dpl_config.c \
+	ti_pinmux_config.c \
+	ti_power_clock_config.c \
+
+FILES_PATH_common = \
+	.. \
+	../../.. \
+	generated \
+
+INCLUDES_common := \
+	-I${CG_TOOL_ROOT}/include/c \
+	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source \
+	-I${MOTOR_CONTROL_SDK_PATH}/source \
+	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include \
+	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
+	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \
+	-I${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/include \
+	-I${MOTOR_CONTROL_SDK_PATH}/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation \
+	-Igenerated \
+
+DEFINES_common := \
+	-DSOC_AM243X \
+
+CFLAGS_common := \
+	-mcpu=cortex-r5 \
+	-mfloat-abi=hard \
+	-mfpu=vfpv3-d16 \
+	-mthumb \
+	-Wall \
+	-Werror \
+	-g \
+	-Wno-gnu-variable-sized-type-not-at-end \
+	-Wno-unused-function \
+
+CFLAGS_cpp_common := \
+	-Wno-c99-designator \
+	-Wno-extern-c-compat \
+	-Wno-c++11-narrowing \
+	-Wno-reorder-init-list \
+	-Wno-deprecated-register \
+	-Wno-writable-strings \
+	-Wno-enum-compare \
+	-Wno-reserved-user-defined-literal \
+	-Wno-unused-const-variable \
+	-x c++ \
+
+CFLAGS_debug := \
+	-D_DEBUG_=1 \
+
+CFLAGS_release := \
+	-Os \
+
+LNK_FILES_common = \
+	linker.cmd \
+
+LIBS_PATH_common = \
+	-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+	-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+	-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+	-Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/lib \
+	-Wl,-i${CG_TOOL_ROOT}/lib \
+
+LIBS_common = \
+	-lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-lmotorcontrol_sdfm.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-llibc.a \
+	-llibsysbm.a \
+
+LFLAGS_common = \
+	-Wl,--diag_suppress=10063 \
+	-Wl,--ram_model \
+	-Wl,--reread_libs \
+
+
+LIBS_NAME = \
+	freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	motorcontrol_sdfm.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	libc.a \
+	libsysbm.a \
+
+LIBS_PATH_NAME = \
+	${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+	${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+	${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+	${MOTOR_CONTROL_SDK_PATH}/source/current_sense/sdfm/lib \
+	${CG_TOOL_ROOT}/lib \
+
+FILES := $(FILES_common) $(FILES_$(PROFILE))
+ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
+FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
+CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
+INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
+LIBS := $(LIBS_common) $(LIBS_$(PROFILE))
+LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE))
+LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE))
+LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE))
+LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE))
+
+OBJDIR := obj/$(PROFILE)/
+OBJS := $(FILES:%.c=%.obj)
+OBJS += $(ASMFILES:%.S=%.obj)
+DEPS := $(FILES:%.c=%.d)
+
+vpath %.obj $(OBJDIR)
+vpath %.c $(FILES_PATH)
+vpath %.S $(FILES_PATH)
+vpath %.lib $(LIBS_PATH_NAME)
+vpath %.a $(LIBS_PATH_NAME)
+
+$(OBJDIR)/%.obj %.obj: %.c
+	@echo  Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $<
+	$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.S
+	@echo  Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $<
+	$(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
+
+all: $(TARGETS)
+
+SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h
+SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h
+SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h
+SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c
+SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h
+SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h
+
+$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME)
+	@echo  .
+	@echo  Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ...
+	$(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES)
+	@echo  Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
+	@echo  .
+
+clean:
+	@echo  Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
+	$(RMDIR) $(OBJDIR)
+	$(RM) $(OUTNAME)
+	$(RM) $(BOOTIMAGE_NAME)
+	$(RM) $(BOOTIMAGE_NAME_XIP)
+	$(RM) $(BOOTIMAGE_NAME_SIGNED)
+	$(RM) $(BOOTIMAGE_NAME_HS)
+	$(RM) $(BOOTIMAGE_NAME_HS_FS)
+	$(RM) $(BOOTIMAGE_RPRC_NAME)
+	$(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+	$(RMDIR) generated/
+
+scrub:
+	@echo  Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang icss_sdfm_three_channel_with_phase_compensation ...
+	$(RMDIR) obj
+ifeq ($(OS),Windows_NT)
+	$(RM) \*.out
+	$(RM) \*.map
+	$(RM) \*.appimage*
+	$(RM) \*.rprc*
+	$(RM) \*.tiimage*
+	$(RM) \*.bin
+else
+	$(RM) *.out
+	$(RM) *.map
+	$(RM) *.appimage*
+	$(RM) *.rprc*
+	$(RM) *.tiimage*
+	$(RM) *.bin
+endif
+	$(RMDIR) generated
+
+$(OBJS): | $(OBJDIR)
+
+$(OBJDIR):
+	$(MKDIR) $@
+
+
+.NOTPARALLEL:
+
+.INTERMEDIATE: syscfg
+$(SYSCFG_GEN_FILES): syscfg
+
+syscfg: ../example.syscfg
+	@echo Generating SysConfig files ...
+	$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg
+
+syscfg-gui:
+	$(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALX_beta --context r5fss0-0 --part ALX --package ALX --output generated/  ../example.syscfg
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+  BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+  BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+  XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+  XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+$(BOOTIMAGE_NAME): $(OUTNAME)
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
+ifneq ($(OS),Windows_NT)
+	$(CHMOD) a+x $(XIPGEN_CMD)
+endif
+	$(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+	$(RM) $(BOOTIMAGE_RPRC_NAME)
+	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
+	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+	$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!!
+	@echo  .
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+	@echo  .
+
+$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+	@echo Boot image signing: Encryption is disabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+else
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
+	$(RM) $(BOOTIMAGE_NAME)-enc
+endif
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
+	@echo  .
+endif
+-include $(addprefix $(OBJDIR)/, $(DEPS))
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@ -0,0 +1,106 @@
+#
+# Auto generated makefile
+#
+
+# Below variables need to be defined outside this file or via command line
+# - MOTOR_CONTROL_SDK_PATH
+# - PROFILE
+# - CG_TOOL_ROOT
+# - OUTNAME
+# - CCS_INSTALL_DIR
+# - CCS_IDE_MODE
+
+CCS_PATH=$(CCS_INSTALL_DIR)
+include ${MOTOR_CONTROL_SDK_PATH}/imports.mak
+include ${MOTOR_CONTROL_SDK_PATH}/devconfig/devconfig.mak
+
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+	PYTHON=python
+else
+	PYTHON=python3
+endif
+
+OUTFILE=$(PROFILE)/$(OUTNAME).out
+BOOTIMAGE_PATH=$(abspath ${PROFILE})
+BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
+BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
+BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+  BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+  BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+  XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+  XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0)  \
+
+all:
+ifeq ($(CCS_IDE_MODE),cloud)
+#	No post build steps
+else
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME)  ...
+	$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
+	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+	$(RM) $(BOOTIMAGE_RPRC_NAME)
+	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
+ifeq ($(DEVICE_TYPE),HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+	@echo Boot image signing: Encryption is disabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
+else
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
+	$(RM) $(BOOTIMAGE_NAME)-enc
+endif
+endif
+	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
+	@echo  .
+ifeq ($(DEVICE_TYPE),HS)
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
+	@echo  .
+else
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+	@echo  .
+endif
+endif
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
@ -7,7 +7,7 @@ include $(MOTOR_CONTROL_SDK_PATH)/imports.mak

 PROFILE?=Release

-PROJECT_NAME=icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang
+PROJECT_NAME=icss_sdfm_three_channel_with_phase_compensation_am243x-lp_r5fss0-0_freertos_ti-arm-clang

 all:
 	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
@ -0,0 +1,8 @@
+/*
+ *  ======== syscfg_c.rov.xs ========
+ *  This file contains the information needed by the Runtime Object
+ *  View (ROV) tool.
+ */
+var crovFiles = [
+    "kernel/freertos/rov/FreeRTOS.rov.js",
+];
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/app_sdfm.c
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/app_sdfm.c
@ -0,0 +1,455 @@
+/*
+ *  Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <kernel/dpl/DebugP.h>
+#include <kernel/dpl/AddrTranslateP.h>
+#include <kernel/dpl/HwiP.h>
+#include <drivers/epwm.h>
+#include "ti_drivers_config.h"
+#include "ti_drivers_open_close.h"
+#include "ti_board_open_close.h"
+
+#include "epwm_dc.h"
+#include "cfg_pad.h"
+#include "sdfm.h"
+#include "mclk_iep0_sync.h"
+
+/*EPWM1 configuration for sigma delta clock generation: */
+#define APP_EPWM1_ENABLE  0 /*make sure EPWM1 is added in sysconfig before making true this macro */
+/* Output channel - A or B */
+#define APP_EPWM_OUT_CH_EN              ( 0x1 ) /* ChA enabled */
+
+/* EPWM functional clock */
+/* Functional clock is the same for all EPWMs */
+#define APP_EPWM_FCLK                   ( CONFIG_EPWM0_FCLK )
+
+/* EPWM functional clock dividers */
+#define APP_EPWM_FCLK_HSPCLKDIV         ( 0x0 ) /* EPWM_TBCTL:HSPCLKDIV, High-Speed Time-base Clock Prescale Bits */
+#define APP_EPWM_FCLK_CLKDIV            ( 0x0 ) /* EPWM_TBCTL:CLKDIV, Time-base Clock Prescale Bits */
+
+#if (APP_EPWM_FCLK_HSPCLKDIV != 0x0)
+/* EPWM Time Base clock -- all EPWM TB clocks set the same */
+#define APP_EPWM_TB_FREQ               ( APP_EPWM_FCLK / ( 2*APP_EPWM_FCLK_HSPCLKDIV * (1 << APP_EPWM_FCLK_CLKDIV)))
+#else
+/* EPWM Time Base clock -- all EPWM TB clocks set the same */
+#define APP_EPWM_TB_FREQ               ( APP_EPWM_FCLK / ( 1 * (1 << APP_EPWM_FCLK_CLKDIV)))
+#endif
+
+/* Initial Duty Cycle of PWM output signal in %, 0 to 100 */
+#define APP_EPWM0_DUTY_CYCLE            ( 50U )
+
+/* Frequency of PWM output signal in Hz */
+#define APP_EPWM_OUTPUT_FREQ_4K         ( 1U * 4000U )
+#define APP_EPWM_OUTPUT_FREQ_8K         ( 1U * 8000U )
+#define APP_EPWM_OUTPUT_FREQ_16K        ( 1U * 16000U )
+#define APP_EPWM_OUTPUT_FREQ_20K        ( 1U * 20000U )
+#define APP_EPWM_OUTPUT_FREQ            ( APP_EPWM_OUTPUT_FREQ_8K ) /* init freq */
+
+/*sample Read time */
+#define FIRST_SAMPLE_TRIGGER_TIME                ((float)((float)1000000/(4*APP_EPWM_OUTPUT_FREQ))) /*sample trigger time for Single Update */
+
+#define SECOND_SAMPLE_TRIGGER_TIME               ((float)((float)3000000/(4*APP_EPWM_OUTPUT_FREQ))) /*Sample trigger time for double update*/
+
+/* PWM count direction (Up, Down, Up/Down) */
+#define APP_EPWM_TB_COUNTER_DIR         ( EPWM_TB_COUNTER_DIR_UP_DOWN )
+
+/* Test ICSSG instance ID */
+#define TEST_ICSSG_INST_ID              ( CONFIG_PRU_ICSS0 )
+/* Test ICSSG slice ID */
+#define TEST_ICSSG_SLICE_ID             ( ICSSG_SLICE_ID_0 )
+/* Test PRU core instance IDs */
+#define TEST_PRU_INST_ID                ( PRUICSS_PRU0 )
+#define TEST_RTU_INST_ID                ( PRUICSS_RTU_PRU0 )
+
+/* R5F interrupt settings for ICSSG */
+#define ICSSG_PRU_SDFM_INT_NUM          ( CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_0 )  /* VIM interrupt number */
+#define ICSSG_RTU_SDFM_INT_NUM          ( CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_1 )  /* VIM interrupt number */
+
+/* EPWM0 IRQ handler */
+static void epwmIrqHandler(void *handle);
+
+/* EPWM1 IRQ handler */
+static void epwmIrqHandler1(void *handle);
+
+/* HWI global variables */
+static HwiP_Object gIcssgPruSdfmHwiObject;  /* ICSSG PRU SDFM FW HWI */
+
+#if APP_EPWM1_ENABLE
+#define APP_EPWM_OUTPUT_FREQ1            (1U*20000000 )
+static HwiP_Object gIcssgRtuSDFMHwiObject;  /* ICSSG RTU SDFM FW HWI */
+
+static HwiP_Object gEpwm1HwiObject;         /* EPWM1 HWI */
+
+uint32_t gEpwm1BaseAddr;    /* EPWM1 base address */
+EPwmObj_t gEpwm1Obj;        /* EPWM1 object */
+Epwm_Handle hEpwm1;         /* EPWM1 handle */
+
+volatile uint32_t gEpwmOutFreq1 = APP_EPWM_OUTPUT_FREQ1; /*EPWM1 output freq. */
+
+#endif
+
+static HwiP_Object gEpwm0HwiObject;         /* EPWM0 HWI */
+
+/* EPWM global variables */
+uint32_t gEpwm0BaseAddr;    /* EPWM0 base address */
+EPwmObj_t gEpwm0Obj;        /* EPWM0 object */
+Epwm_Handle hEpwm0;         /* EPWM0 handle */
+
+
+
+volatile uint32_t gEpwmOutFreq = APP_EPWM_OUTPUT_FREQ; /* EPWM output frequency */
+
+
+/* ICSSG PRU SDFM FW IRQ handler */
+static void pruSdfmIrqHandler(void *handle);
+
+
+/* Test ICSSG handle */
+PRUICSS_Handle gPruIcssHandle;
+
+/* Test Sdfm handles */
+sdfm_handle gHPruSdfm;
+
+/* Sdfm output samples, written by PRU cores */
+__attribute__((section(".gSdfmSampleOutput"))) uint32_t gSdfm_sampleOutput[NUM_CH_SUPPORTED];
+
+/* Test Sdfm parameters */
+SdfmPrms gTestSdfmPrms = {
+    300000000,    /*PRU Core clock*/
+    300000000,   /*Value of ICSSG0_IEP clock*/
+    300000000,   /*ICSSG1_IEP_CLOCK*/
+    20000000,    /*Value of SD clock (It should be exact equal to sd clock value)*/
+    0,                        /*enable double update*/
+    FIRST_SAMPLE_TRIGGER_TIME,       /*first sample  trigger time*/
+    SECOND_SAMPLE_TRIGGER_TIME,       /*second sample trigger time*/
+    APP_EPWM_OUTPUT_FREQ,     /*PWM output frequency*/
+    {{3500, 1000,0},    /*threshold parameters(High, low & reserevd)*/
+    {3500, 1000,0},
+    {3500, 1000,0}},
+    {{0,0},                /*clock sourse & clock inversion for all channels*/
+    {0,0},
+    {0,0}},
+    15,   /*Over current osr: The effect count is OSR + 1*/
+    128,   /*Normal current osr */
+    1,   /*comparator enable*/
+    (uint32_t)&gSdfm_sampleOutput,/*Output samples base address*/
+    0,    /*Fast detect enable*/
+    {{4, 18, 2},
+    {4, 18, 2},
+    {4, 18, 2}},   /*Fast detect fields {Window size, zero count max, zero count min}*/
+    1, /*Phase delay enable*/
+};
+
+#define PRUICSS_G_MUX_EN    ( 0x1 ) /* ICSSG_SA_MX_REG:G_MUX_EN */
+
+/* GPIO enable signal for EPWM0-2 on 3-axis breakout board */
+uint32_t gMtr1PwnEnGpioBaseAddr = GPIO_MTR_1_PWM_EN_BASE_ADDR;
+uint32_t gMtr1PwnEnGpioPin      = GPIO_MTR_1_PWM_EN_PIN;
+uint32_t gMtr1PwnEnGpioPinDir   = GPIO_MTR_1_PWM_EN_DIR;
+
+/* Flag for continuing to execute test */
+volatile Bool gRunFlag = TRUE;
+
+
+/* SDFM Output sample for Channel 0 */
+/*Sample size*/
+#define MAX_SAMPLES (128)
+uint32_t sdfm_ch0_samples[MAX_SAMPLES] = {0};
+uint32_t sdfm_ch0_idx = 0;
+/* SDFM Output sample for Channel 1 */
+uint32_t sdfm_ch1_samples[MAX_SAMPLES] = {0};
+uint32_t sdfm_ch1_idx = 0;
+/* SDFM Output sample for Channel 2 */
+uint32_t sdfm_ch2_samples[MAX_SAMPLES] = {0};
+uint32_t sdfm_ch2_idx = 0;
+
+
+/* IRQ counters */
+volatile uint32_t gPruSdfmIrqCnt=0; /* PRU Sdfm FW IRQ count */
+volatile uint32_t gEpwmIsrCnt=0;    /* EPWM0 IRQ count */
+volatile uint32_t gEpwmIsrCnt1=0;
+/*PWM Parameters*/
+HwiP_Params hwiPrms;
+HwiP_Params hwiPrms1;
+EPwmCfgPrms_t epwmCfgPrms;
+EPwmCfgPrms_t epwm1CfgPrms;
+
+void init_pwm()
+{
+    int32_t status;
+    /* Initialize EPWM0 base address, perform address translation */
+    gEpwm0BaseAddr = (uint32_t)AddrTranslateP_getLocalAddr(CONFIG_EPWM0_BASE_ADDR);
+
+    /* Register & enable EPWM0 interrupt */
+    HwiP_Params_init(&hwiPrms);
+    hwiPrms.intNum      = CONFIG_EPWM0_INTR;
+    hwiPrms.callback    = &epwmIrqHandler;
+    hwiPrms.args        = 0;
+    hwiPrms.isPulse     = CONFIG_EPWM0_INTR_IS_PULSE;
+    hwiPrms.isFIQ       = FALSE;
+    status              = HwiP_construct(&gEpwm0HwiObject, &hwiPrms);
+    DebugP_assert(status == SystemP_SUCCESS);
+
+    /* Configure EPWM0 */
+    epwmCfgPrms.epwmId = EPWM_ID_0;
+    epwmCfgPrms.epwmBaseAddr = gEpwm0BaseAddr;
+    epwmCfgPrms.epwmOutChEn = APP_EPWM_OUT_CH_EN;
+    epwmCfgPrms.hspClkDiv = APP_EPWM_FCLK_HSPCLKDIV;
+    epwmCfgPrms.clkDiv = APP_EPWM_FCLK_CLKDIV;
+    epwmCfgPrms.epwmTbFreq = APP_EPWM_TB_FREQ;
+    epwmCfgPrms.epwmOutFreq = gEpwmOutFreq;
+    epwmCfgPrms.epwmDutyCycle[EPWM_OUTPUT_CH_A] = APP_EPWM0_DUTY_CYCLE;
+    epwmCfgPrms.epwmTbCounterDir = APP_EPWM_TB_COUNTER_DIR;
+    epwmCfgPrms.cfgTbSyncIn = TRUE;
+    epwmCfgPrms.tbPhsValue = 0;
+    epwmCfgPrms.tbSyncInCounterDir = EPWM_TB_COUNTER_DIR_UP;
+    epwmCfgPrms.cfgTbSyncOut = TRUE;
+    epwmCfgPrms.tbSyncOutMode = EPWM_TB_SYNC_OUT_EVT_CNT_EQ_ZERO;
+    epwmCfgPrms.aqCfg[EPWM_OUTPUT_CH_A].zeroAction = EPWM_AQ_ACTION_DONOTHING;
+    epwmCfgPrms.aqCfg[EPWM_OUTPUT_CH_A].prdAction = EPWM_AQ_ACTION_DONOTHING;
+    epwmCfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpAUpAction = EPWM_AQ_ACTION_HIGH;
+    epwmCfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpADownAction = EPWM_AQ_ACTION_LOW;
+    epwmCfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpBUpAction = EPWM_AQ_ACTION_DONOTHING;
+    epwmCfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpBDownAction = EPWM_AQ_ACTION_DONOTHING;
+    epwmCfgPrms.cfgDb = FALSE;
+    epwmCfgPrms.cfgEt = TRUE;
+    epwmCfgPrms.intSel = EPWM_ET_INTR_EVT_CNT_EQ_ZRO;
+    epwmCfgPrms.intPrd = EPWM_ET_INTR_PERIOD_FIRST_EVT;
+    hEpwm0 = epwmInit(&epwmCfgPrms, &gEpwm0Obj);
+    DebugP_assert(hEpwm0 != NULL);
+
+#if APP_EPWM1_ENABLE  // DEBUG code for SDFM clock generation from EPWM1
+    /* EPWM1 for SD clock generation */
+    /* Initialize EPWM1 base address, perform address translation */
+    gEpwm1BaseAddr = (uint32_t)AddrTranslateP_getLocalAddr(CONFIG_EPWM1_BASE_ADDR);
+    /* Register & enable EPWM0 interrupt */
+    HwiP_Params_init(&hwiPrms1);
+    hwiPrms1.intNum      = CONFIG_EPWM1_INTR;
+    hwiPrms1.callback    = &epwmIrqHandler1;
+    hwiPrms1.args        = 0;
+    hwiPrms1.isPulse     = CONFIG_EPWM1_INTR_IS_PULSE;
+    hwiPrms1.isFIQ       = FALSE;
+    status              = HwiP_construct(&gEpwm1HwiObject, &hwiPrms1);
+    DebugP_assert(status == SystemP_SUCCESS);
+    /* Configure EPWM0 */
+    epwm1CfgPrms.epwmId = EPWM_ID_1;
+    epwm1CfgPrms.epwmBaseAddr = gEpwm1BaseAddr;
+    epwm1CfgPrms.epwmOutChEn = APP_EPWM_OUT_CH_EN;
+    epwm1CfgPrms.hspClkDiv = APP_EPWM_FCLK_HSPCLKDIV;
+    epwm1CfgPrms.clkDiv = APP_EPWM_FCLK_CLKDIV;
+    epwm1CfgPrms.epwmTbFreq = APP_EPWM_TB_FREQ;
+    epwm1CfgPrms.epwmOutFreq = gEpwmOutFreq1;
+    epwm1CfgPrms.epwmDutyCycle[EPWM_OUTPUT_CH_A] = APP_EPWM0_DUTY_CYCLE;
+    epwm1CfgPrms.epwmTbCounterDir = APP_EPWM_TB_COUNTER_DIR;
+    epwm1CfgPrms.cfgTbSyncIn = FALSE;
+    epwm1CfgPrms.tbPhsValue = 0;
+    epwm1CfgPrms.cfgTbSyncOut = FALSE;
+    epwm1CfgPrms.tbSyncOutMode = EPWM_TB_SYNC_OUT_EVT_CNT_EQ_ZERO;
+    epwm1CfgPrms.aqCfg[EPWM_OUTPUT_CH_A].zeroAction = EPWM_AQ_ACTION_DONOTHING;
+    epwm1CfgPrms.aqCfg[EPWM_OUTPUT_CH_A].prdAction = EPWM_AQ_ACTION_DONOTHING;
+    epwm1CfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpAUpAction = EPWM_AQ_ACTION_HIGH;
+    epwm1CfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpADownAction = EPWM_AQ_ACTION_LOW;
+    epwm1CfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpBUpAction = EPWM_AQ_ACTION_DONOTHING;
+    epwm1CfgPrms.aqCfg[EPWM_OUTPUT_CH_A].cmpBDownAction = EPWM_AQ_ACTION_DONOTHING;
+    epwm1CfgPrms.cfgDb = FALSE;
+    epwm1CfgPrms.cfgEt = FALSE;
+    epwm1CfgPrms.intSel = EPWM_ET_INTR_EVT_CNT_EQ_ZRO;
+    epwm1CfgPrms.intPrd = EPWM_ET_INTR_PERIOD_FIRST_EVT;
+    hEpwm1 = epwmInit(&epwm1CfgPrms, &gEpwm1Obj);
+    DebugP_assert(hEpwm1 != NULL);
+#endif 
+}
+
+void init_sdfm()
+{
+    int32_t status;
+    /* Initialize ICSSG */
+    status = initIcss(TEST_ICSSG_INST_ID, TEST_ICSSG_SLICE_ID, PRUICSS_G_MUX_EN, &gPruIcssHandle);
+    if (status != SDFM_ERR_NERR) {
+        DebugP_log("Error: initIcss() fail.\r\n");
+        return;
+    }
+
+    /* Register & enable ICSSG PRU SDFM FW interrupt */
+    HwiP_Params_init(&hwiPrms);
+    hwiPrms.intNum      = ICSSG_PRU_SDFM_INT_NUM;
+    hwiPrms.callback    = &pruSdfmIrqHandler;
+    hwiPrms.args        = 0;
+    hwiPrms.isPulse     = FALSE;
+    hwiPrms.isFIQ       = FALSE;
+    status              = HwiP_construct(&gIcssgPruSdfmHwiObject, &hwiPrms);
+    DebugP_assert(status == SystemP_SUCCESS);
+
+    /* Initialize PRU core for SDFM */
+    status = initPruSdfm(gPruIcssHandle, TEST_PRU_INST_ID, &gTestSdfmPrms, &gHPruSdfm);
+    if (status != SDFM_ERR_NERR) 
+    {
+        DebugP_log("Error: initPruSdfm() fail.\r\n");
+        return;
+    }
+
+}
+void sdfm_main(void *args)
+{
+
+    /* Open drivers to open the UART driver for console */
+    Drivers_open();
+    Board_driversOpen();
+
+    DebugP_log("Sample SDFM example running!...\r\n");
+
+    /* Output build time */
+    DebugP_log("Build timestamp      : %s %s\r\n", __DATE__, __TIME__);
+
+
+    /* Enable EPWM0-2 on 3-axis Breakout Board */
+    GPIO_setDirMode(gMtr1PwnEnGpioBaseAddr, gMtr1PwnEnGpioPin, gMtr1PwnEnGpioPinDir);
+    GPIO_pinWriteHigh(gMtr1PwnEnGpioBaseAddr, gMtr1PwnEnGpioPin);
+    GPIO_pinWriteLow(gMtr1PwnEnGpioBaseAddr, gMtr1PwnEnGpioPin);
+
+    /*
+     *  Configure EPWM0
+     */
+    init_pwm();
+    DebugP_log("EPWM Configured!\r\n");
+    /*
+     *  Configure SDFM
+     */
+
+    /* Configure SOC pads for SDFM.
+       Normally handled via Pinmux_init(),
+       but currently no way to pads for ICSSG from Sysconfig. */
+    cfgPad();
+    
+    /*Configure IEP for SD clock when phase delay calculaton is enabled*/
+    if(gTestSdfmPrms.phase_delay)
+    {
+        /*config ICSSG1 IEP0 */
+        init_IEP0_SYNC();
+        /*start ICSSG1 IEP */
+        start_IEP0();
+
+    }
+    
+     /* Configure SDFM */
+    init_sdfm();
+    DebugP_log("SDFM Configured!\r\n");
+    
+    /* Start EPWM0 clock */
+    CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_EPWM_TB_CLKEN, 1);
+
+    /* Force SW sync for EPWM0 */
+    EPWM_tbTriggerSwSync(gEpwm0BaseAddr);
+
+    while(gRunFlag == TRUE)
+    {
+        ;
+    }
+
+    /* Disable and clear interrupts for EPWM0 */
+    EPWM_etIntrDisable(gEpwm0BaseAddr); /* Disable interrupts */
+    EPWM_etIntrClear(gEpwm0BaseAddr);   /* Clear pending interrupts */
+
+    /* Destroy EPWM0 HWI */
+    HwiP_destruct(&gEpwm0HwiObject);
+
+    /* Destroy PRU SDFM HWI */
+    HwiP_destruct(&gIcssgPruSdfmHwiObject);
+
+    DebugP_log("All tests have passed!!\r\n");
+
+    Board_driversClose();
+    Drivers_close();
+}
+
+/* PRU SDFM FW IRQ handler */
+void pruSdfmIrqHandler(void *args)
+{
+    /* debug, inncrement PRU SDFM IRQ count */
+    gPruSdfmIrqCnt++;
+    /* Clear interrupt at source */
+    /* Write 18 to ICSSG_STATUS_CLR_INDEX_REG
+        Firmware:   TRIGGER_HOST_SDFM_IRQ defined as 18
+        18 = 16+2, 2 is Host Interrupt Number. See AM64x TRM.
+    */
+    PRUICSS_clearEvent(gPruIcssHandle, PRU_TRIGGER_HOST_SDFM_EVT);
+
+   /* SDFM Output sample for Channel 0 */
+    sdfm_ch0_samples[sdfm_ch0_idx++] = SDFM_getFilterData(gHPruSdfm, 0);
+    /* SDFM Output sample for Channel 1 */
+    sdfm_ch1_samples[sdfm_ch1_idx++] = SDFM_getFilterData(gHPruSdfm, 1);
+    /* SDFM Output sample for Channel 2 */
+    sdfm_ch2_samples[sdfm_ch2_idx++] = SDFM_getFilterData(gHPruSdfm, 2);
+
+    if(sdfm_ch0_idx >= MAX_SAMPLES)
+    {
+        sdfm_ch0_idx = 0;
+        sdfm_ch1_idx = 0;
+        sdfm_ch2_idx = 0;
+    }
+}
+
+
+/* EPWM0 IRQ handler */
+static void epwmIrqHandler(void *args)
+{
+    volatile uint16_t status;
+
+    /* debug, inncrement EPWM0 IRQ count */
+    gEpwmIsrCnt++;
+
+    status = EPWM_etIntrStatus(gEpwm0BaseAddr);
+    if (status & EPWM_ETFLG_INT_MASK) 
+    {
+        EPWM_etIntrClear(gEpwm0BaseAddr);
+    }
+    return;
+}
+
+#if APP_EPWM1_ENABLE //DEBUG code for EPWM1
+/* EPWM0 IRQ handler */
+static void epwmIrqHandler1(void *args)
+{
+    volatile uint16_t status;
+
+    /* debug, inncrement EPWM0 IRQ count */
+    gEpwmIsrCnt1++;
+
+    status = EPWM_etIntrStatus(gEpwm1BaseAddr);
+    if (status & EPWM_ETFLG_INT_MASK) 
+    {
+        EPWM_etIntrClear(gEpwm0BaseAddr);
+    }
+    return;
+}
+#endif
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/cfg_pad.c
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/cfg_pad.c
@ -0,0 +1,95 @@
+/*
+ *  Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <drivers/pinmux.h>
+#include "cfg_pad.h"
+
+static Pinmux_PerCfg_t gPinMuxMainDomainCfgsdfm[] = {
+
+    /* PRG0_ECAP0_IN_APWM_OUT,
+       PRG0_PRU1_GPO15, PRG0_ECAP0_IN_APWM_OUT, U5, J2.C11  */
+    {
+        PIN_PRG0_PRU1_GPO15,
+        ( PIN_MODE(10) | PIN_PULL_DISABLE )
+    },
+    /* SD8_CLK,
+       PRG0_PRU0_GPI16, SD8_CLK,    U4, J2E:P9 */
+    {
+        PIN_PRG0_PRU0_GPO16,
+        ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
+    },
+    /* SD0_D,
+      PRG0_PRU0_GPI1,   SD0_D,      R4, J2E:P8 */
+    {
+        PIN_PRG0_PRU0_GPO1,
+        ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
+    },
+    /* SD1_D,
+       PRG0_PRU0_GPI3, SD1_D,      V2, J2A:P9  */
+    {
+        PIN_PRG0_PRU0_GPO3,
+        ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
+    },
+    /* SD2_D,
+       PRG0_PRU0_GPI5,  SD2_D,      R3, J2C:P6  */
+    {
+        PIN_PRG0_PRU0_GPO5,
+        ( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
+    },
+    /* ICSSG1_IEP0_SYNC_OUT0,
+       PRG1_IEP0_EDC_SYNC_OUT0,  SYNC_OUT0,      R3, J7.63  */
+    {
+        PIN_PRG1_PRU0_GPO19,
+        ( PIN_MODE(2) | PIN_PULL_DISABLE )
+    },
+    /* ICSSG1_IEP0_SYNC_OUT1,
+       PRG1_IEP0_EDC_SYNC_OUT0,  SYNC_OUT1,      R3, J7.65  */
+    {
+        PIN_PRG1_PRU0_GPO17,
+        ( PIN_MODE(2) | PIN_PULL_DISABLE )
+    },
+    
+    /* PWM0_TZ_OUT,
+       PRG0_PWM0_TZ_OUT, TZ_OUT,      R3, J2C:P6  */
+    {
+        PIN_PRG0_PRU0_GPO19,
+        ( PIN_MODE(3) | PIN_PULL_DISABLE )
+    },
+
+    {PINMUX_END, PINMUX_END}
+};
+
+/* Configure SOC pads */
+void cfgPad(void)
+{
+    Pinmux_config(gPinMuxMainDomainCfgsdfm, PINMUX_DOMAIN_ID_MAIN);
+}
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/cfg_pad.h
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/cfg_pad.h
@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CFG_PAD_H_
+#define _CFG_PAD_H_
+
+/* Configure SOC pads.
+   Normally handled via Pinmux_init(),
+   but currently no way to pads for ICSSG from Sysconfig. */
+void cfgPad(void);
+
+#endif /* _CFG_PAD_H_ */
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_dc.c
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_dc.c
@ -0,0 +1,306 @@
+/*
+ *  Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <math.h>
+#include <drivers/epwm.h>
+#include "epwm_drv_aux.h"
+#include "epwm_mod.h"
+#include "epwm_dc.h"
+
+Epwm_Handle epwmInit(
+    EPwmCfgPrms_t *pEpwmCfgPrms,
+    EPwmObj_t *pEpwmObj
+)
+{
+    Epwm_Handle hEpwm;              /* EPWM handle */
+    uint32_t epwmBaseAddr;          /* EPWM base address */
+    uint32_t epwmOutChEn;           /* EPWM output channel (A/B) enable bit mask */
+    uint32_t epwmTbFreq;            /* EPWM time base clock */
+    uint32_t epwmOutFreq;           /* EPWM output frequency */
+    uint32_t epwmTbCounterDir;      /* EPWM TB counter direction */
+    uint32_t epwmPrdVal;
+    uint32_t epwmCmpAVal, epwmCmpBVal;
+
+    /* Get configuration parameters */
+    epwmBaseAddr = pEpwmCfgPrms->epwmBaseAddr;
+    epwmOutChEn = pEpwmCfgPrms->epwmOutChEn;
+    epwmTbFreq = pEpwmCfgPrms->epwmTbFreq;
+    epwmOutFreq = pEpwmCfgPrms->epwmOutFreq;
+    epwmTbCounterDir = pEpwmCfgPrms->epwmTbCounterDir;
+
+    /* Configure Time Base submodule */
+    writeTbClkDiv(epwmBaseAddr, pEpwmCfgPrms->hspClkDiv, pEpwmCfgPrms->clkDiv);
+    tbPwmFreqCfg(epwmBaseAddr, epwmTbFreq, epwmOutFreq,
+        epwmTbCounterDir, EPWM_SHADOW_REG_CTRL_ENABLE, &epwmPrdVal);
+
+    /* Configure TB Sync In Mode */
+    if (pEpwmCfgPrms->cfgTbSyncIn == FALSE) {
+        EPWM_tbSyncDisable(epwmBaseAddr);
+    }
+    else {
+        EPWM_tbSyncEnable(epwmBaseAddr, pEpwmCfgPrms->tbPhsValue, pEpwmCfgPrms->tbSyncInCounterDir);
+    }
+
+    /* Configure TB Sync Out Mode */
+    if (pEpwmCfgPrms->cfgTbSyncOut == FALSE) {
+        EPWM_tbSetSyncOutMode(epwmBaseAddr, EPWM_TB_SYNC_OUT_EVT_DISABLE );
+    }
+    else {
+        EPWM_tbSetSyncOutMode(epwmBaseAddr, pEpwmCfgPrms->tbSyncOutMode);
+    }
+
+    /* Configure emulation mode */
+    EPWM_tbSetEmulationMode(epwmBaseAddr, EPWM_TB_EMU_MODE_FREE_RUN);
+
+    if ((epwmOutChEn >> 0) & 0x1) {
+        /*
+         *  COMPA value - this determines the duty cycle
+         *  COMPA = (PRD - ((dutycycle * PRD) / 100)
+         */
+        epwmCmpAVal = (epwmPrdVal - ((pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_A] * epwmPrdVal) / 100U));
+        //epwmCmpAVal = 1; // FL: force max duty cycle just before 100% DC to see where EPWM period occurs
+
+        /* Configure counter compare submodule */
+        EPWM_counterComparatorCfg(epwmBaseAddr, EPWM_CC_CMP_A,
+            epwmCmpAVal, EPWM_SHADOW_REG_CTRL_ENABLE,
+                EPWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO, TRUE);
+        /* Configure Action Qualifier Submodule */
+        EPWM_aqActionOnOutputCfg(epwmBaseAddr, EPWM_OUTPUT_CH_A,
+            &pEpwmCfgPrms->aqCfg[EPWM_OUTPUT_CH_A]);
+    }
+
+    if ((epwmOutChEn >> 1) & 0x1) {
+        /*
+         *  COMPB value - this determines the duty cycle
+         *  COMPB = (PRD - ((dutycycle * PRD) / 100)
+         */
+        epwmCmpBVal = (epwmPrdVal - ((pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_B] * epwmPrdVal) / 100U));
+
+        /* Configure counter compare submodule */
+        EPWM_counterComparatorCfg(epwmBaseAddr, EPWM_CC_CMP_B,
+            epwmCmpBVal, EPWM_SHADOW_REG_CTRL_ENABLE,
+                EPWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO, TRUE);
+        /* Configure Action Qualifier Submodule */
+        EPWM_aqActionOnOutputCfg(epwmBaseAddr, EPWM_OUTPUT_CH_B,
+            &pEpwmCfgPrms->aqCfg[EPWM_OUTPUT_CH_B]);
+    }
+
+    if (pEpwmCfgPrms->cfgDb == TRUE) {
+        /* Configure Dead Band Submodule */
+        EPWM_deadbandCfg(epwmBaseAddr, &pEpwmCfgPrms->dbCfg);
+    }
+    else {
+        /* Configure Dead Band Submodule */
+        EPWM_deadbandBypass(epwmBaseAddr);
+    }
+
+    /* Configure Chopper Submodule */
+    EPWM_chopperEnable(epwmBaseAddr, FALSE);
+
+    /* Configure trip zone Submodule */
+    EPWM_tzTripEventDisable(epwmBaseAddr, EPWM_TZ_EVENT_ONE_SHOT, 0U);
+    EPWM_tzTripEventDisable(epwmBaseAddr, EPWM_TZ_EVENT_CYCLE_BY_CYCLE, 0U);
+
+    if (pEpwmCfgPrms->cfgEt == TRUE) {
+        /* Configure event trigger Submodule */
+        EPWM_etIntrCfg(epwmBaseAddr, pEpwmCfgPrms->intSel,
+            pEpwmCfgPrms->intPrd);
+        EPWM_etIntrEnable(epwmBaseAddr);
+    }
+
+    /* Init PWM object */
+    hEpwm = (Epwm_Handle)pEpwmObj;
+    hEpwm->epwmId = pEpwmCfgPrms->epwmId;
+    hEpwm->epwmBaseAddr = pEpwmCfgPrms->epwmBaseAddr;
+    hEpwm->epwmOutChEn = pEpwmCfgPrms->epwmOutChEn;
+    hEpwm->hspClkDiv = pEpwmCfgPrms->hspClkDiv;
+    hEpwm->clkDiv = pEpwmCfgPrms->clkDiv;
+    hEpwm->epwmTbFreq = pEpwmCfgPrms->epwmTbFreq;
+    hEpwm->epwmOutFreq = pEpwmCfgPrms->epwmOutFreq;
+    hEpwm->epwmPrdVal = epwmPrdVal;
+    hEpwm->toggleEpwmPrd = FALSE;
+    hEpwm->toggleEpwmPrdState = 0;
+    hEpwm->epwmPrdValL = 0;
+    hEpwm->epwmPrdValU = 0;
+    if ((epwmOutChEn >> 0) & 0x1) {
+        hEpwm->epwmDutyCycle[EPWM_OUTPUT_CH_A] = pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_A];
+        hEpwm->cmpAVal = epwmCmpAVal;
+        hEpwm->cmpANzToZ = FALSE;
+        hEpwm->cmpAZToNz = FALSE;
+    }
+    if ((epwmOutChEn >> 1) & 0x1) {
+        hEpwm->epwmDutyCycle[EPWM_OUTPUT_CH_B] = pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_B];
+        hEpwm->cmpBVal = epwmCmpBVal;
+        hEpwm->cmpBNzToZ = FALSE;
+        hEpwm->cmpBZToNz = FALSE;
+    }
+
+    return hEpwm;
+}
+
+/* Update EPWM period */
+int32_t epwmUpdatePrd(
+    Epwm_Handle hEpwm,
+    uint32_t epwmOutFreqSet
+)
+{
+    float epwmPrdVal_f;
+    uint32_t epwmPrdVal;
+    uint32_t rem;
+
+    /* Check for EPWM period toggle */
+    if (hEpwm->toggleEpwmPrd == TRUE) {
+        hEpwm->epwmPrdVal = (hEpwm->toggleEpwmPrdState == 0) ? hEpwm->epwmPrdValL : hEpwm->epwmPrdValU;
+        hEpwm->toggleEpwmPrdState ^= 0x1;
+
+        /* Write next period count */
+        writeTbPrd(hEpwm->epwmBaseAddr, hEpwm->epwmPrdVal);
+    }
+
+    /* Check for PWM frequency change */
+    if (hEpwm->epwmOutFreq != epwmOutFreqSet) {
+        epwmPrdVal_f = (float)hEpwm->epwmTbFreq / epwmOutFreqSet;
+        epwmPrdVal_f = roundf(epwmPrdVal_f);
+
+        epwmPrdVal = (uint32_t)epwmPrdVal_f;
+        rem = epwmPrdVal - epwmPrdVal/2*2;
+        if (rem == 0) {
+            /* Period is divisible by 2,
+               alternating period not employed */
+            hEpwm->toggleEpwmPrd = FALSE;
+            hEpwm->toggleEpwmPrdState = 0;
+            hEpwm->epwmPrdValL = 0;
+            hEpwm->epwmPrdValU = 0;
+            hEpwm->epwmPrdVal = epwmPrdVal/2;
+        } else {
+            /* Period is not divisible by 2,
+               alternating period employed to provide correct average EPWM frequency:
+                EPWM period 2*n     : TBPRD <- 'Lower' period
+                EPWM period 2*n+1   : TBPRD <- 'Upper' period
+            */
+            hEpwm->toggleEpwmPrd = TRUE;
+            hEpwm->toggleEpwmPrdState = 1;
+            hEpwm->epwmPrdValL = epwmPrdVal/2;
+            hEpwm->epwmPrdValU = epwmPrdVal/2+1;
+            hEpwm->epwmPrdVal = hEpwm->epwmPrdValL;
+        }
+
+        /* Write next period count */
+        writeTbPrd(hEpwm->epwmBaseAddr, hEpwm->epwmPrdVal);
+
+        hEpwm->epwmOutFreq = epwmOutFreqSet;
+    }
+
+    return EPWM_DC_SOK;
+}
+
+/* Update EPWM A/B outputs */
+int32_t epwmUpdateOut(
+    Epwm_Handle hEpwm,
+    float VrefA,
+    float VrefB
+)
+{
+    float dcVal;        /* EPWM duty cycle value */
+    uint16_t cmpVal;    /* EPWM CMP value */
+
+    if ((hEpwm->epwmOutChEn >> 0) & 0x1) {
+        /* Compute next Duty Cycle and CMP values */
+        computeCmpx(VrefA, hEpwm->epwmPrdVal, &dcVal, &cmpVal);
+
+        /* Write next CMPA value */
+        writeCmpA(hEpwm->epwmBaseAddr, cmpVal);
+
+        /* EPWM 100% Duty Cycle */
+        /* Handle transition to 100% Duty Cycle */
+        if (hEpwm->cmpANzToZ == TRUE) {
+            /* restore original AQ */
+            cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING);
+            hEpwm->cmpANzToZ = FALSE;
+        }
+        if ((hEpwm->cmpAVal != 0) && (cmpVal == 0)) {
+            /* set AQ to set for next period */
+            cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_HIGH);
+            hEpwm->cmpANzToZ = TRUE;
+        }
+
+        /* Handle transition from 100% Duty Cycle */
+        if (hEpwm->cmpAZToNz == TRUE) {
+            /* restore original AQ */
+            cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING);
+            hEpwm->cmpAZToNz = FALSE;
+        }
+        if ((hEpwm->cmpAVal == 0) && (cmpVal != 0)) {
+            /* set AQ to clear for next period */
+            cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_LOW);
+            hEpwm->cmpAZToNz = TRUE;
+        }
+        hEpwm->cmpAVal = cmpVal;
+    }
+
+    if ((hEpwm->epwmOutChEn >> 1) & 0x1) {
+        /* Compute next Duty Cycle and CMP values */
+        computeCmpx(VrefB, hEpwm->epwmPrdVal, &dcVal, &cmpVal);
+
+        /* Write next CMPB value */
+        writeCmpB(hEpwm->epwmBaseAddr, cmpVal);
+
+        /* EPWM 100% Duty Cycle */
+        /* Handle transition to 100% Duty Cycle */
+        if (hEpwm->cmpBNzToZ == TRUE) {
+            /* restore original AQ */
+            cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING);
+            hEpwm->cmpBNzToZ = FALSE;
+        }
+        if ((hEpwm->cmpBVal != 0) && (cmpVal == 0)) {
+            /* set AQ to set for next period */
+            cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_HIGH);
+            hEpwm->cmpBNzToZ = TRUE;
+        }
+
+        /* Handle transition from 100% Duty Cycle */
+        if (hEpwm->cmpBZToNz == TRUE) {
+            /* restore original AQ */
+            cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING);
+            hEpwm->cmpBZToNz = FALSE;
+        }
+        if ((hEpwm->cmpBVal == 0) && (cmpVal != 0)) {
+            /* set AQ to clear for next period */
+            cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_LOW);
+            hEpwm->cmpBZToNz = TRUE;
+        }
+        hEpwm->cmpBVal = cmpVal;
+    }
+
+    return EPWM_DC_SOK;
+}
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_dc.h
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_dc.h
@ -0,0 +1,141 @@
+/*
+ *  Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _EPWM_DC_H_
+#define _EPWM_DC_H_
+
+#include <stdint.h>
+#include <drivers/hw_include/hw_types.h>
+#include <drivers/epwm.h>
+
+/* Status return values */
+#define EPWM_DC_SOK         ( 0 )
+
+#define EPWM_ID_0           ( 0 )
+#define EPWM_ID_1           ( 1 )
+#define EPWM_ID_2           ( 2 )
+
+#define EPWM_NUM_OUT_CH     ( EPWM_OUTPUT_CH_MAX + 1 )
+
+/* EPWM configuration parameters */
+typedef struct _EPwmCfgPrms_t
+{
+    uint32_t    epwmId;             /* EPWM ID */
+    uint32_t    epwmBaseAddr;       /* EPWM base address */
+    uint32_t    epwmOutChEn;        /* EPWM output channel (A/B) enable bit mask */
+    uint32_t    hspClkDiv;          /* EPWM High-Speed Time-base Clock Prescale Bits */
+    uint32_t    clkDiv;             /* EPWM Time-base Clock Prescale Bits */
+    uint32_t    epwmTbFreq;         /* EPWM timebase clock */
+    uint32_t    epwmOutFreq;        /* EPWM output frequency */
+    /* EPWM duty cycle */
+    uint32_t    epwmDutyCycle[EPWM_NUM_OUT_CH];
+    uint32_t    epwmTbCounterDir;   /* EPWM counter direction (Up, Down, Up/Down) */
+
+    /* TB sync in config */
+    Bool        cfgTbSyncIn;        /* config TB sync in flag (true/false) */
+    uint32_t 	tbPhsValue;         /* cfgTbSyncIn==TRUE: timer phase value to load on Sync In event */
+    uint32_t 	tbSyncInCounterDir; /* cfgTbSyncIn==TRUE: counter direction on Sync In event */
+
+    /* TB sync out config */
+    Bool        cfgTbSyncOut;       /* config TB sync output flag (true/false) */
+    uint32_t 	tbSyncOutMode;      /* cfgTbSyncOut==TRUE: Sync Out mode */
+
+    /* AQ config */
+    EPWM_AqActionCfg aqCfg[EPWM_NUM_OUT_CH];
+
+    /* DB config */
+    Bool        cfgDb;              /* config DB flag (true/false) */
+    EPWM_DeadbandCfg dbCfg;       /* Deadband config */
+
+    /* ET config */
+    Bool        cfgEt;              /* config ET module */
+    uint32_t    intSel;             /* ET interrupt select */
+    uint32_t    intPrd;             /* ET interrupt period */
+} EPwmCfgPrms_t;
+
+/* EPWM object */
+typedef struct _EPwmObj_t
+{
+    uint32_t    epwmId;             /* EPWM ID */
+    uint32_t    epwmBaseAddr;       /* EPWM base address */
+    uint32_t    epwmOutChEn;        /* EPWM output channel (A/B) enable bit mask */
+    uint32_t    hspClkDiv;          /* EPWM High-Speed Time-base Clock Prescale Bits */
+    uint32_t    clkDiv;             /* EPWM Time-base Clock Prescale Bits */
+    uint32_t    epwmTbFreq;         /* EPWM timebase clock */
+    uint32_t    epwmOutFreq;        /* EPWM output frequency */
+    /* EPWM duty cycle */
+    uint32_t    epwmDutyCycle[EPWM_NUM_OUT_CH];
+
+    uint32_t    epwmPrdVal;         /* EPWM period value */
+
+    /* For handling up-down count alternating period
+       when period isn't divisible by 2 */
+    Bool        toggleEpwmPrd;      /* Flag for EPWM in alternating period mode */
+    uint8_t     toggleEpwmPrdState; /* Alternating period state:
+                                       'Lower' or 'Upper' period written on alternate ISRs */
+    uint32_t    epwmPrdValL;        /* 'Lower' EPWM period value written in 'Lower' state */
+    uint32_t    epwmPrdValU;        /* 'Upper' EPWM period value written in 'Upper' state */
+
+    /* For handling ChA 100% Duty Cycle */
+    uint32_t    cmpAVal;            /* Current CMPA value */
+    Bool        cmpANzToZ;          /* Flag for EPWM transition CMPA!=0 to CMPA=0 */
+    Bool        cmpAZToNz;          /* Flag for EPWM transition CMPA=0 to CMPA!=0 */
+
+    /* For handling ChB 100% Duty Cycle */
+    uint32_t    cmpBVal;            /* Current CMPB value */
+    Bool        cmpBNzToZ;          /* Flag for EPWM transition CMPB!=0 to CMPB=0 */
+    Bool        cmpBZToNz;          /* Flag for EPWM transition CMPB=0 to CMPB!=0 */
+} EPwmObj_t;
+
+/* EPWM Handle */
+typedef EPwmObj_t * Epwm_Handle;
+
+/* Initialize EPWM */
+Epwm_Handle epwmInit(
+    EPwmCfgPrms_t *pEpwmCfgPrms,
+    EPwmObj_t *pEpwmObj
+);
+
+/* Update EPWM period */
+int32_t epwmUpdatePrd(
+    Epwm_Handle hEpwm,
+    uint32_t epwmOutFreqSet
+);
+
+/* Update EPWM A/B outputs */
+int32_t epwmUpdateOut(
+    Epwm_Handle hEpwm,
+    float VrefA,
+    float VrefB
+);
+
+#endif /* _EPWM_DC_H_ */
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_drv_aux.c
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_drv_aux.c
@ -0,0 +1,86 @@
+/*
+ *  Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <drivers/epwm.h>
+#include <drivers/hw_include/hw_types.h>
+#include <drivers/hw_include/csl_types.h>
+#include "epwm_drv_aux.h"
+
+#include <math.h>
+
+/* Configure PWM Time base counter Frequency/Period */
+void tbPwmFreqCfg(
+    uint32_t baseAddr,
+    uint32_t tbClk,
+    uint32_t pwmFreq,
+    uint32_t counterDir,
+    uint32_t enableShadowWrite,
+    uint32_t *pPeriodCount
+)
+{
+    uint32_t tbPeriodCount;
+    float tbPeriodCount_f;
+    uint32_t regVal = 0U;
+
+    regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_TBCTL);
+    HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_PRDLD, enableShadowWrite);
+    HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_CTRMODE, counterDir);
+    HW_WR_REG16((baseAddr + PWMSS_EPWM_TBCTL),
+        (uint16_t)regVal);
+
+    /* compute period using floating point */
+    tbPeriodCount_f = (float)tbClk / pwmFreq;
+    if (EPWM_TB_COUNTER_DIR_UP_DOWN == counterDir) {
+        tbPeriodCount_f = tbPeriodCount_f / 2.0;
+    }
+    tbPeriodCount_f = roundf(tbPeriodCount_f);
+    tbPeriodCount = (uint32_t)tbPeriodCount_f;
+
+#if 0 /* use this in case there is some reason not to use floating point */
+    /* compute period using fixed point */
+    tbPeriodCount = tbClk << 4; /* U32Q4 */
+    tbPeriodCount /= pwmFreq;
+    if (EPWM_TB_COUNTER_DIR_UP_DOWN == counterDir) {
+        tbPeriodCount /= 2;
+    }
+    tbPeriodCount += 1<<3;      /* biased rouding to 0.5 */
+    tbPeriodCount >>= 4;        /* U32Q0 */
+#endif
+
+    regVal = (counterDir == EPWM_TB_COUNTER_DIR_UP_DOWN) ?
+        tbPeriodCount : tbPeriodCount-1;
+    HW_WR_REG16((baseAddr + PWMSS_EPWM_TBPRD),
+        (uint16_t)regVal);
+
+    *pPeriodCount = tbPeriodCount;
+}
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_drv_aux.h
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_drv_aux.h
@ -0,0 +1,197 @@
+/*
+ *  Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _EPWM_DRV_AUX_H_
+#define _EPWM_DRV_AUX_H_
+
+#include <stdint.h>
+#include <drivers/hw_include/hw_types.h>
+#include <drivers/epwm.h>
+
+/* Write EPWM CMPA */
+static inline void writeCmpA(
+    uint32_t baseAddr,
+    uint32_t cmpVal
+)
+{
+    HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPA), PWMSS_EPWM_CMPA,
+        (uint16_t)cmpVal);
+}
+
+/* Write EPWM CMPB */
+static inline void writeCmpB(
+    uint32_t baseAddr,
+    uint32_t cmpVal
+)
+{
+    HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPB), PWMSS_EPWM_CMPB,
+        (uint16_t)cmpVal);
+}
+
+/* Write EPWM CMPA/CMPB */
+static inline void writeCmpAB(
+    uint32_t baseAddr,
+    uint32_t cmpAVal,
+    uint32_t cmpBVal
+)
+{
+    /* Write CMPA */
+    HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPA), PWMSS_EPWM_CMPA,
+        (uint16_t)cmpAVal);
+
+    /* Write CMPB */
+    HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPB), PWMSS_EPWM_CMPB,
+        (uint16_t)cmpBVal);
+}
+
+/* Configure Output ChannelA AQ Zero  */
+static inline void cfgOutChAAqZero(
+    uint32_t baseAddr,
+    uint32_t zeroAction
+)
+{
+    uint32_t regVal = 0U;
+
+    regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA);
+    HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_ZRO, zeroAction);
+    HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal);
+}
+
+/* Configure Output ChannelA AQ CMPA Up  */
+static inline void cfgOutChAAqCAU(
+    uint32_t baseAddr,
+    uint32_t cmpAUpAction
+)
+{
+    uint32_t regVal = 0U;
+
+    regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA);
+    HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CAU, cmpAUpAction);
+    HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal);
+};
+
+/* Configure Output ChannelA AQ CMPA Down */
+static inline void cfgOutChAAqCAD(
+    uint32_t baseAddr,
+    uint32_t cmpADownAction
+)
+{
+    uint32_t regVal = 0U;
+
+    regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA);
+    HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CAD, cmpADownAction);
+    HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal);
+}
+
+/* Configure Output ChannelB AQ Zero  */
+static inline void cfgOutChBAqZero(
+    uint32_t baseAddr,
+    uint32_t zeroAction
+)
+{
+    uint32_t regVal = 0U;
+
+    regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLB);
+    HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLB_ZRO, zeroAction);
+    HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLB), (uint16_t)regVal);
+}
+
+/* Configure Output ChannelA AQ CMPB Up  */
+static inline void cfgOutChAAqCBU(
+    uint32_t baseAddr,
+    uint32_t cmpBUpAction
+)
+{
+    uint32_t regVal = 0U;
+
+    regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA);
+    HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CBU, cmpBUpAction);
+    HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal);
+}
+
+/* Write TB Period */
+static inline void writeTbPrd(
+    uint32_t baseAddr,
+    uint32_t tbPeriodCount
+)
+{
+    HW_WR_REG16((baseAddr + PWMSS_EPWM_TBPRD), (uint16_t)tbPeriodCount);
+}
+
+/* Write TB Phase */
+static inline void writeTbPhase(
+    uint32_t baseAddr,
+    uint32_t tbPhsValue
+)
+{
+    HW_WR_REG16((baseAddr + PWMSS_EPWM_TBPHS), (uint16_t)tbPhsValue);
+}
+
+/* Write TBCTL HSPDIV & CLKDIV */
+static inline void writeTbClkDiv(
+    uint32_t baseAddr,
+    uint32_t hspClkDiv,
+    uint32_t clkDiv
+)
+{
+    uint32_t regVal = 0U;
+
+    regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_TBCTL);
+    HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_CLKDIV, clkDiv);
+    HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_HSPCLKDIV, hspClkDiv);
+    HW_WR_REG16((baseAddr + PWMSS_EPWM_TBCTL), (uint16_t)regVal);
+}
+
+/* Write TBCTL CTRMODE */
+static inline void writeTbCtrMode(
+    uint32_t baseAddr,
+    uint32_t ctrMode
+)
+{
+    uint32_t regVal = 0U;
+
+    regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_TBCTL);
+    HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_CTRMODE, ctrMode);
+    HW_WR_REG16((baseAddr + PWMSS_EPWM_TBCTL), (uint16_t)regVal);
+}
+
+/* Configure PWM Time base counter Frequency/Period */
+void tbPwmFreqCfg(
+    uint32_t baseAddr,
+    uint32_t tbClk,
+    uint32_t pwmFreq,
+    uint32_t counterDir,
+    uint32_t enableShadowWrite,
+    uint32_t *pPeriodCount
+);
+
+#endif /* _EPWM_DRV_AUX_H_ */
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_mod.c
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_mod.c
@ -0,0 +1,75 @@
+/*
+ *  Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "epwm_mod.h"
+
+#include <stdint.h>
+#include <math.h>
+
+
+/* Min / max output amplitude.
+   Waveform amplitude values beyond these thresholds are saturated. */
+#define VREF_MAX                        (  1.0f )
+#define VREF_MIN                        ( -1.0f )
+
+/* Compute Duty Cycle & CMPx given Vref & EPWM period */
+void computeCmpx(
+    float       Vref,
+    uint32_t    epwmPrdVal,
+    float       *pEpwmDutyCycle,
+    uint16_t    *pEpwmCmpVal
+)
+{
+    float dc_f;
+    float cmp_f;
+    uint16_t cmp;
+
+    if (Vref >= VREF_MAX) {
+        /* 100% duty cycle */
+        dc_f = 1.0;
+    }
+    else if (Vref <= VREF_MIN) {
+        /* 0% duty cycle */
+        dc_f = 0.0;
+    }
+    else {
+        /* compute Duty Cycle */
+        dc_f = 0.5*(Vref + 1.0);
+    }
+
+    /* compute CMPx */
+    cmp_f = (1.0 - dc_f)*epwmPrdVal; /* up-down count */
+    cmp = (uint16_t)roundf(cmp_f);
+
+    *pEpwmDutyCycle = dc_f;
+    *pEpwmCmpVal = cmp;
+}
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_mod.h
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/epwm_mod.h
@ -0,0 +1,46 @@
+/*
+ *  Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _EPWM_MOD_H_
+#define _EPWM_MOD_H_
+
+#include <stdint.h>
+
+/* Compute Duty Cycle & CMPx given Vref */
+void computeCmpx(
+    float       Vref,
+    uint32_t    epwmPrdVal,
+    float       *pEpwmDutyCycle,
+    uint16_t    *pEpwmCmpVal
+);
+
+#endif /* _EPWM_MOD_H_ */
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/mclk_iep0_sync.c
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/mclk_iep0_sync.c
@ -0,0 +1,95 @@
+/*
+ *  Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include "stdint.h"
+#include "math.h"
+#include "stdio.h"
+
+#include <drivers/pruicss.h>
+#include <drivers/hw_include/hw_types.h>
+#include <drivers/hw_include/cslr_soc.h>
+
+void init_IEP0_SYNC()
+{
+/* ************************************* iep config ********************************** */
+
+    /*reset iep0 timer*/
+    HW_WR_REG8(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_GLOBAL_CFG_REG, 0x20);
+    HW_WR_REG32(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_COUNT_REG0, 0xffffffff);
+    HW_WR_REG32(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_COUNT_REG1, 0xffffffff);
+
+    /* set CMP1 period - SYNC01 trigger */
+    HW_WR_REG32(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_CMP1_REG0, 99);
+
+    /* set CMP2 period - SYNC1 trigger - with 6 ns delay - only used in independent mode*/
+    HW_WR_REG32(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_CMP2_REG0, 99);
+
+    /*Set sync ctrl register: SYNC1 dependent, cyclic generation , SYNC0 and SYNC1 enable, SYNC enable*/
+    HW_WR_REG32(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_SYNC_CTRL_REG, 0x00A7);
+
+    /*Set SYNC0/1 high pulse time in iep clok cycles  ( 7 clocks for 20 MHz at 300 MHz iep clk) */
+    HW_WR_REG32(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_SYNC_PWIDTH_REG, 0x0006);
+
+    /*Set SYNC0/1 period  ( 15 clocks for 20 MHz at 300 MHz iep clk)*/
+    HW_WR_REG32(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_SYNC0_PERIOD_REG, 14);
+
+    /*Set delay between SYNC0 and SYNC1 in clock cycles 2 = 3 clock cycles*/
+    HW_WR_REG32(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_SYNC1_DELAY_REG, 0);
+
+    /*Set offset from cpm1 hit*/
+    HW_WR_REG32(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_SYNC_START_REG, 0);
+
+    /*set enable cmp1 and cmp2 for sync start trigger generation*/
+    HW_WR_REG32(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_CMP_CFG_REG, 0x000000c);
+       
+    /*set default and compensation increment to 1*/
+    HW_WR_REG8(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_GLOBAL_CFG_REG, 0x0110);
+
+    return;
+}
+
+void start_IEP0(void)
+{
+    uint8_t regVal;
+
+    /*start iep0_timer*/
+    regVal = HW_RD_REG8(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_GLOBAL_CFG_REG);
+    regVal |= 0x1;
+    HW_WR_REG8(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_GLOBAL_CFG_REG, regVal);
+}
+
+void config_SYNC_DELAY(uint32_t delay)
+{
+   /* Set delay between SYNC0 and SYNC1 in clock cycles 2 = 3 clock cycles */
+    HW_WR_REG32(CSL_PRU_ICSSG1_IEP0_BASE+CSL_ICSS_G_PR1_IEP0_SLV_SYNC1_DELAY_REG, delay);
+}
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/mclk_iep0_sync.h
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/mclk_iep0_sync.h
@ -0,0 +1,39 @@
+/*
+ *  Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MCLK_IEP_SYNC_H_
+#define _MCLK_IEP_SYNC_H_
+
+void init_IEP0_SYNC(void);
+void start_IEP0(void);
+void config_SYNC_DELAY(uint32_t delay);
+#endif /* _MCLK_IEP_SYNC_H_ */
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/sdfm.c
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/sdfm.c
@ -0,0 +1,383 @@
+/*
+ *  Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <kernel/dpl/DebugP.h>
+#include "ti_drivers_config.h"
+#include "ti_drivers_open_close.h"
+#include "ti_board_open_close.h"
+
+#include <stdint.h>
+#include <drivers/hw_include/csl_types.h>
+#include <drivers/pruicss.h>
+#include <drivers/sciclient.h>
+
+#include "tisdfm_pruss_intc_mapping.h"  /* INTC configuration */
+#include "current_sense/sdfm/firmware/sdfm_bin.h"            /* SDFM image data */
+#include "sdfm.h"
+#include "current_sense/sdfm/include/sdfm_api.h"
+#include "mclk_iep0_sync.h"
+
+/* PRU SDFM FW image info */
+typedef struct PRUSDFM_PruFwImageInfo_s {
+    const uint32_t *pPruImemImg;
+    const uint32_t pruImemImgSz;
+} PRUSDFM_PruFwImageInfo;
+
+/* Number of PRU images */
+#define PRU_SDFM_NUM_PRU_IMAGE  ( 3 )
+
+/* PRU SDFM image info */
+static PRUSDFM_PruFwImageInfo gPruFwImageInfo[PRU_SDFM_NUM_PRU_IMAGE] =
+{
+    {pru_SDFM_PRU0_image_0, sizeof(pru_SDFM_PRU0_image_0)}, /* PRU FW */
+    {NULL, 0}
+};
+
+/* ICSS INTC configuration */
+static const PRUICSS_IntcInitData gPruicssIntcInitdata = PRUICSS_INTC_INITDATA;
+
+/*
+ *  ======== initIcss ========
+ */
+/* Initialize ICSSG */
+int32_t initIcss(
+    uint8_t icssInstId,
+    uint8_t sliceId,
+    uint8_t saMuxMode,
+    PRUICSS_Handle *pPruIcssHandle
+)
+{
+    PRUICSS_Handle pruIcssHandle;
+    int32_t size;
+    int32_t status;
+
+    /* Open ICSS PRU instance */
+    pruIcssHandle = PRUICSS_open(icssInstId);
+    if (pruIcssHandle == NULL) {
+        return SDFM_ERR_INIT_ICSSG;
+    }
+
+    /* Disable slice PRU cores */
+    if (sliceId == ICSSG_SLICE_ID_0)
+    {
+        status = PRUICSS_disableCore(pruIcssHandle, PRUICSS_PRU0);
+        if (status != SystemP_SUCCESS) {
+            return SDFM_ERR_INIT_ICSSG;
+        }
+    }
+    else if (sliceId == ICSSG_SLICE_ID_1)
+    {
+        status = PRUICSS_disableCore(pruIcssHandle, PRUICSS_PRU1);
+        if (status != SystemP_SUCCESS) {
+            return SDFM_ERR_INIT_ICSSG;
+        }
+    }
+    else
+    {
+        return SDFM_ERR_INIT_ICSSG;
+    }
+
+    /* Reset slice memories */
+    size = PRUICSS_initMemory(pruIcssHandle, PRUICSS_IRAM_PRU(sliceId));
+    if (size == 0)
+    {
+        return SDFM_ERR_INIT_ICSSG;
+    }
+    size = PRUICSS_initMemory(pruIcssHandle, PRUICSS_DATARAM(sliceId));
+    if (size == 0)
+    {
+        return SDFM_ERR_INIT_ICSSG;
+    }
+
+    /* Set ICSS pin mux */
+    PRUICSS_setSaMuxMode(pruIcssHandle, saMuxMode);
+
+    /* Initialize ICSS INTC */
+    status = PRUICSS_intcInit(pruIcssHandle, &gPruicssIntcInitdata);
+    if (status != SystemP_SUCCESS) {
+        return SDFM_ERR_INIT_ICSSG;
+    }
+
+    *pPruIcssHandle = pruIcssHandle;
+
+    return SDFM_ERR_NERR;
+}
+void sdfm_configure_gpio_pin(sdfm_handle h_sdfm)
+{
+    /*ch0 GPIO configuration*/
+    uint32_t gpioBaseAddrCh0Hi = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_HIGH_TH_CH0_BASE_ADDR);
+    uint32_t pinNumCh0Hi       = GPIO_HIGH_TH_CH0_PIN;
+    GPIO_setDirMode(gpioBaseAddrCh0Hi, pinNumCh0Hi, GPIO_HIGH_TH_CH0_DIR);
+    SDFM_configComparatorGpioPins(h_sdfm, 0, gpioBaseAddrCh0Hi, pinNumCh0Hi, 0);
+
+    uint32_t gpioBaseAddrCh0Lo = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_LOW_TH_CH0_BASE_ADDR);
+    uint32_t pinNumCh0Lo       = GPIO_LOW_TH_CH0_PIN;
+    GPIO_setDirMode(gpioBaseAddrCh0Lo, pinNumCh0Lo, GPIO_LOW_TH_CH0_DIR);
+    SDFM_configComparatorGpioPins(h_sdfm, 0, gpioBaseAddrCh0Lo, pinNumCh0Lo, 1);
+
+
+    /*ch1 GPIO configuration*/
+    uint32_t gpioBaseAddrCh1Hi = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_HIGH_TH_CH1_BASE_ADDR);
+    uint32_t pinNumCh1Hi       = GPIO_HIGH_TH_CH1_PIN;
+    GPIO_setDirMode(gpioBaseAddrCh1Hi, pinNumCh1Hi, GPIO_HIGH_TH_CH1_DIR);
+    SDFM_configComparatorGpioPins(h_sdfm, 1, gpioBaseAddrCh1Hi, pinNumCh1Hi, 0);
+
+    uint32_t gpioBaseAddrCh1Lo = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_LOW_TH_CH1_BASE_ADDR);
+    uint32_t pinNumCh1Lo       = GPIO_LOW_TH_CH1_PIN;
+    GPIO_setDirMode(gpioBaseAddrCh1Lo, pinNumCh1Lo, GPIO_LOW_TH_CH1_DIR);
+    SDFM_configComparatorGpioPins(h_sdfm, 1, gpioBaseAddrCh1Lo, pinNumCh1Lo, 1);
+
+
+    /*ch2 GPIO configuration*/
+    uint32_t gpioBaseAddrCh2Hi = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_HIGH_TH_CH2_BASE_ADDR);
+    uint32_t pinNumCh2Hi       = GPIO_HIGH_TH_CH2_PIN;
+    GPIO_setDirMode(gpioBaseAddrCh2Hi, pinNumCh2Hi, GPIO_HIGH_TH_CH2_DIR);
+    SDFM_configComparatorGpioPins(h_sdfm, 2, gpioBaseAddrCh2Hi, pinNumCh2Hi, 0);
+
+    uint32_t gpioBaseAddrCh2Lo = (uint32_t) AddrTranslateP_getLocalAddr(GPIO_LOW_TH_CH2_BASE_ADDR);
+    uint32_t pinNumCh2Lo       = GPIO_LOW_TH_CH2_PIN;
+    GPIO_setDirMode(gpioBaseAddrCh2Lo, pinNumCh2Lo, GPIO_LOW_TH_CH2_DIR);
+    SDFM_configComparatorGpioPins(h_sdfm, 2, gpioBaseAddrCh2Lo, pinNumCh2Lo, 1);
+
+
+}
+void SDFM_measurePhaseCompensation(sdfm_handle h_sdfm, uint32_t iep_clk)
+{
+   
+    /*waiting till measurment done */
+    float delay;
+    delay = SDFM_measureClockPhaseDelay(h_sdfm, 0);
+    /*Convert nenosec into IEP cycle count*/
+    uint32_t iepCount = (delay*iep_clk)/1000000000;
+
+    /*config IEP SYNC1 delay based on phase compensation  */
+    config_SYNC_DELAY(iepCount);
+    
+}
+/* Initialize SDFM PRU FW */
+int32_t init_sdfm_pru_fw(uint8_t pruId, SdfmPrms *pSdfmPrms, sdfm_handle *pHSdfm, void *pruss_cfg)
+{
+    sdfm_handle hSdfm;
+
+    /* Initialize SDFM instance */
+    hSdfm = SDFM_init(pruId);
+    
+    uint32_t i;
+    i = SDFM_getFirmwareVersion(hSdfm);
+    DebugP_log("\n\n\n");
+    DebugP_log("SDFM firmware version \t: %x.%x.%x (%s)\n\n", (i >> 24) & 0x7F,
+                (i >> 16) & 0xFF, i & 0xFFFF, i & (1 << 31) ? "internal" : "release");
+    if (hSdfm == NULL)
+    {
+        return SDFM_ERR_INIT_SDFM;
+    }
+
+    uint8_t SDFM_CH;
+    hSdfm->pru_core_clk = pSdfmPrms->pru_clock;
+    hSdfm->iep_clock = pSdfmPrms->G0iep_clock; 
+    hSdfm->sdfm_clock = pSdfmPrms->sd_clock; 
+    hSdfm->sampleOutputInterface = (SDFM_SampleOutInterface *)(pSdfmPrms->samplesBaseAddress);
+    uint32_t sampleOutputInterfaceGlobalAddr = CPU0_BTCM_SOCVIEW(pSdfmPrms->samplesBaseAddress);
+    hSdfm->p_sdfm_interface->sampleBufferBaseAdd = sampleOutputInterfaceGlobalAddr;
+    hSdfm->iep_inc = 1; /* Default IEP increment 1 */
+    hSdfm->pruss_cfg = pruss_cfg;
+
+
+    uint8_t acc_filter = 0; //SINC3 filter
+    uint8_t ecap_divider = 0x0F; //IEP at 300MHz: SD clock = 300/15=20Mhz
+    
+    if(pSdfmPrms->phase_delay)
+    {
+        SDFM_measurePhaseCompensation(hSdfm, pSdfmPrms->G1iep_clock);
+    }
+    
+
+    /*configure IEP count for one epwm period*/
+    SDFM_configIepCount(hSdfm, pSdfmPrms->epwm_out_freq);
+
+    /*configure ecap as PWM code for generate 20 MHz sdfm clock*/
+    SDFM_configEcap(hSdfm, ecap_divider);
+
+    /*set Noraml current OSR */
+    SDFM_setFilterOverSamplingRatio(hSdfm, pSdfmPrms->FilterOsr);
+     
+
+    /*below configuration for all three channel*/
+    for(SDFM_CH = 0; SDFM_CH < NUM_CH_SUPPORTED; SDFM_CH++)
+    {
+        SDFM_setEnableChannel(hSdfm, SDFM_CH);
+
+        /*set comparator osr or Over current osr*/
+        SDFM_setCompFilterOverSamplingRatio(hSdfm, SDFM_CH, pSdfmPrms->ComFilterOsr);
+
+        /*set ACC source or filter type*/
+        SDFM_configDataFilter(hSdfm, SDFM_CH, acc_filter);
+
+        /*set clock inversion & clock source for all three channel*/
+        SDFM_selectClockSource(hSdfm, SDFM_CH, pSdfmPrms->clkPrms[SDFM_CH]);
+
+        /*set threshold values */
+        SDFM_setCompFilterThresholds(hSdfm, SDFM_CH, pSdfmPrms->threshold_parms[SDFM_CH]);
+        if(pSdfmPrms->en_fd)
+        {
+            /*Fast detect configuration */
+            SDFM_configFastDetect(hSdfm, SDFM_CH, pSdfmPrms->fastDetect[SDFM_CH]);
+        }
+        if(pSdfmPrms->en_com)
+        {
+            SDFM_enableComparator(hSdfm, SDFM_CH);       
+        }
+        else
+        {
+            SDFM_disableComparator(hSdfm, SDFM_CH);
+        }
+
+    }
+    
+    /*GPIO pin configuration for threshold measurment*/
+    sdfm_configure_gpio_pin(hSdfm);
+
+    SDFM_setSampleTriggerTime(hSdfm, pSdfmPrms->firstSampTrigTime);
+    if(pSdfmPrms->en_second_update)
+    {
+        SDFM_enableDoubleSampling(hSdfm, pSdfmPrms->secondSampTrigTime);
+    }
+    else
+    {
+        SDFM_disableDoubleSampling(hSdfm);
+    }
+
+    /* Enable (global) SDFM */
+    SDFM_enable(hSdfm);
+
+    *pHSdfm = hSdfm;
+
+ return SDFM_ERR_NERR;
+}
+/*
+ *  ======== initPruSdfm ========
+ */
+/* Initialize PRU core for SDFM */
+int32_t initPruSdfm(
+    PRUICSS_Handle pruIcssHandle,
+    uint8_t pruInstId,
+    SdfmPrms *pSdfmPrms,
+    sdfm_handle *pHSdfm
+)
+{
+    uint8_t sliceId;
+    uint32_t pruIMem;
+    PRUSDFM_PruFwImageInfo *pPruFwImageInfo;
+    int32_t size;
+    const uint32_t *sourceMem;          /* Source memory[ Array of uint32_t ] */
+    uint32_t imemOffset;    /* Offset at which write will happen */
+    uint32_t byteLen;                   /* Total number of bytes to be written */
+    uint8_t pruId;
+    int32_t status;
+    void *pruss_cfg;
+
+    pruss_cfg = (void *)(((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->cfgRegBase);
+    /* Reset PRU */
+    status = PRUICSS_resetCore(pruIcssHandle, pruInstId);
+    if (status != SystemP_SUCCESS) {
+        return SDFM_ERR_INIT_PRU_SDFM;
+    }
+
+
+    /* Calculate slice ID */
+    sliceId = pruInstId - (uint8_t)pruInstId/ICSSG_NUM_SLICE * ICSSG_NUM_SLICE;
+    /* Determine PRU DMEM address */
+    /* Determine PRU FW image and PRU IMEM address */
+    switch (pruInstId)
+    {
+        case PRUICSS_PRU0:
+        case PRUICSS_PRU1:
+            pPruFwImageInfo = &gPruFwImageInfo[0];
+            pruIMem = PRUICSS_IRAM_PRU(sliceId);
+            break;
+        case PRUICSS_RTU_PRU0:
+        case PRUICSS_RTU_PRU1:
+            pPruFwImageInfo = &gPruFwImageInfo[1];
+            pruIMem = PRUICSS_IRAM_RTU_PRU(sliceId);
+            break;
+        case PRUICSS_TX_PRU0:
+        case PRUICSS_TX_PRU1:
+            pPruFwImageInfo = NULL;
+            break;
+        default:
+            pPruFwImageInfo = NULL;
+            break;
+    }
+
+    if ((pPruFwImageInfo == NULL) ||
+        (pPruFwImageInfo->pPruImemImg == NULL))
+    {
+        return SDFM_ERR_INIT_PRU_SDFM;
+    }
+
+    /* Write IMEM */
+    imemOffset = 0;
+    sourceMem = (uint32_t *)pPruFwImageInfo->pPruImemImg;
+    byteLen = pPruFwImageInfo->pruImemImgSz;
+    size = PRUICSS_writeMemory(pruIcssHandle, pruIMem, imemOffset, sourceMem, byteLen);
+    if (size == 0)
+    {
+        return SDFM_ERR_INIT_PRU_SDFM;
+    }
+
+    /* Enable PRU */
+    status = PRUICSS_enableCore(pruIcssHandle, pruInstId);
+    if (status != SystemP_SUCCESS) {
+        return SDFM_ERR_INIT_PRU_SDFM;
+    }
+/* Translate PRU ID to SDFM API */
+    if (pruInstId == PRUICSS_PRU0) {
+        pruId = PRU_ID_0;
+    }
+    else if (pruInstId == PRUICSS_PRU1) {
+        pruId = PRU_ID_1;
+    }
+    else {
+        return SDFM_ERR_INIT_PRU_SDFM;
+    }
+
+    /* Initialize SDFM PRU FW */
+    status = init_sdfm_pru_fw(pruId, pSdfmPrms, pHSdfm, pruss_cfg);
+    if (status != SDFM_ERR_NERR) {
+        return SDFM_ERR_INIT_PRU_SDFM;
+    }
+    return SDFM_ERR_NERR;
+
+}
+
+
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/sdfm.h
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/sdfm.h
@ -0,0 +1,180 @@
+/*
+ *  Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SDFM_H_
+#define _SDFM_H_
+
+#include <stdint.h>
+#include <drivers/pruicss.h>
+#include "current_sense/sdfm/include/sdfm_api.h"
+
+/* Status codes */
+#define SDFM_ERR_NERR               (  0 )  /* no error */
+#define SDFM_ERR_CFG_PIN_MUX        ( -1 )  /* pin mux configuration error */
+#define SDFM_ERR_CFG_ICSSG_CLKCFG   ( -2 )  /* ICSSG clock configuration error */
+#define SDFM_ERR_INIT_ICSSG         ( -3 )  /* initialize ICSSG error */
+#define SDFM_ERR_CFG_MCU_INTR       ( -4 )  /* interrupt configuration error */
+#define SDFM_ERR_INIT_PRU_SDFM      ( -5 )  /* initialize PRU for SDFM error */
+#define SDFM_ERR_INIT_SDFM          ( -6 )  /* initialize SDFM error */
+
+/* Bit for SDFM configuration mask */
+#define SDFM_CFG_CLK                    ( 1<<0 )
+#define SDFM_CFG_OSR                    ( 1<<1 )
+#define SDFM_CFG_TRIG_SAMP_TIME         ( 1<<2 )
+#define SDFM_CFG_TRIG_SAMP_CNT          ( 1<<3 )
+#define SDFM_CFG_CH_EN                  ( 1<<4 )
+#define SDFM_CFG_FD                     ( 1<<5 )
+#define SDFM_CFG_TRIG_OUT_SAMP_BUF      ( 1<<6 )
+
+/* SDFM mode */
+#define SDFM_MODE_TRIG                  ( 0 )
+#define SDFM_MODE_CONT                  ( 1 )
+
+/* ICSSG Core clock source selection options */
+#define CORE_CLK_SEL_ICSSGn_CORE_CLK    ( 0 )   /* Mux Output */
+#define CORE_CLK_SEL_ICSSGn_ICLK        ( 1 )   /* ICSSGn_ICLK = MAIN_SYSCLK0/2 = 250 MHz */
+/* ICSSG Core clock selections in case Mux Output selected */
+#define ICSSGn_CORE_CLK_SEL_MAIN_PLL2_HSDIV0_CLKOUT ( 0 )   /* 225 or 300 MHz, default 225 MHz */
+#define ICSSGn_CORE_CLK_SEL_MAIN_PLL0_HSDIV9_CLKOUT ( 1 )   /* 200, 250, or 333 MHz, default 200 MHz */
+#define ICSSGn_CORE_CLK_SEL_NUMSEL                  ( 2 )
+/* ICSSG Core clock frequency in case Mux Output selected.
+  Set to 0 in case clock frequency configuration not desired. */
+#define ICSSGn_CORE_CLK_FREQ_225MHZ     ( 225000000UL ) /* MAIN PLL2 HSDIV0, 225 MHz */
+#define ICSSGn_CORE_CLK_FREQ_300MHZ     ( 300000000UL ) /* MAIN PLL2 HSDIV0, 300 MHz */
+#define ICSSGn_CORE_CLK_FREQ_200MHZ     ( 200000000UL ) /* MAIN PLL0 HSDIV9, 200 MHz */
+#define ICSSGn_CORE_CLK_FREQ_250MHZ     ( 250000000UL ) /* MAIN PLL0 HSDIV9, 250 MHz */
+#define ICSSGn_CORE_CLK_FREQ_333MHZ     ( 333333333UL ) /* MAIN PLL0 HSDIV9, 333 MHz */
+#define ICSSGn_CORE_CLK_FREQ_NOCFG      ( 0UL )         /* No clock frequency reconfig */
+//#define ICSSGn_CORE_CLK_FREQ            ( ICSSGn_CORE_CLK_FREQ_NOCFG )
+#define ICSSGn_CORE_CLK_FREQ            ( ICSSGn_CORE_CLK_FREQ_300MHZ )
+//#define ICSSGn_CORE_CLK_FREQ            ( ICSSGn_CORE_CLK_FREQ_333MHZ )
+
+/* ICSSG IEP clock source selection options */
+#define IEP_CLK_SEL_ICSSGn_IEP_CLK      ( 0 )   /* Mux Output */
+#define IEP_CLK_SEL_CORE_CLK            ( 1 )   /* CORE_CLK */
+/* ICSSG IEP clock selections in case Mux output selected */
+#define ICSSGn_IEP_CLK_SEL_MAIN_PLL2_HSDIV5_CLKOUT  ( 0 )   /* Default 225 MHz */
+#define ICSSGn_IEP_CLK_SEL_MAIN_PLL0_HSDIV6_CLKOUT  ( 1 )   /* 200 or 250 MHz, default 200 MHz */
+#define ICSSGn_IEP_CLK_SEL_CPSW0_CPTS_RFT_CLK       ( 2 )
+#define ICSSGn_IEP_CLK_SEL_CPTS_RFT_CLK             ( 3 )
+#define ICSSGn_IEP_CLK_SEL_MCU_EXT_REFCLK0          ( 4 )
+#define ICSSGn_IEP_CLK_SEL_EXT_REFCLK1              ( 5 )
+#define ICSSGn_IEP_CLK_SEL_SERDES0_IP1_LN0_TXMCLK   ( 6 )
+#define ICSSGn_IEP_CLK_SEL_SYSCLK0                  ( 7 )
+#define ICSSGn_IEP_CLK_SEL_NUMSEL                   ( 8 )
+/* ICSSG IEP clock frequency in case Mux Output selected.
+   Set to 0 in case clock frequency configuration not desired. */
+#define ICSSGn_IEP_CLK_FREQ_200MHZ      ( 200000000UL ) /* MAIN PLL0 HSDIV6, 200 MHz */
+#define ICSSGn_IEP_CLK_FREQ_250MHZ      ( 250000000UL ) /* MAIN PLL0 HSDIV6, 250 MHz */
+#define ICSSGn_IEP_CLK_FREQ_NOCFG       ( 0UL )          /* No clock frequency reconfig */
+#define ICSSGn_IEP_CLK_FREQ             ( ICSSGn_IEP_CLK_FREQ_NOCFG )
+
+/* Default ICSS pin mux setting */
+#define PRUICSS_G_MUX_EN_DEF            ( 0x0 ) /* ICSSG_SA_MX_REG:G_MUX_EN */
+
+/* Translate the TCM local view addr to SoC view addr */
+#define CPU0_ATCM_SOCVIEW(x) (CSL_R5FSS0_CORE0_ATCM_BASE+(x))
+#define CPU1_ATCM_SOCVIEW(x) (CSL_R5FSS1_CORE0_ATCM_BASE+(x))
+#define CPU0_BTCM_SOCVIEW(x) (CSL_R5FSS0_CORE0_BTCM_BASE+(x - CSL_R5FSS0_BTCM_BASE))
+#define CPU1_BTCM_SOCVIEW(x) (CSL_R5FSS1_CORE0_BTCM_BASE+(x - CSL_R5FSS1_BTCM_BASE))
+
+#define ICSSG_SLICE_ID_0   ( 0 )    /* ICSSG slide ID 0 */
+#define ICSSG_SLICE_ID_1   ( 1 )    /* ICSSG slide ID 1 */
+#define ICSSG_NUM_SLICE    ( 2 )    /* ICSSG number of slices */
+#define NUM_FD_FIELD   ( 3 )
+/*!
+ *  @brief    PRUICSS Instance IDs
+ */
+typedef enum PRUICSS_MaxInstances_s
+{
+   PRUICSS_INSTANCE_ONE=0,
+   PRUICSS_INSTANCE_TWO=1,
+   PRUICSS_INSTANCE_MAX=2
+} PRUICSS_MaxInstances;
+
+/* SDFM configuration parameters */
+typedef struct SdfmPrms_s {
+    /**< PRU_CORE_CLOCK*/
+    uint32_t pru_clock;
+    /**< IEP clock value */
+    uint32_t G0iep_clock;
+    /**< IEP clock value */
+    uint32_t G1iep_clock;
+    /**< Sigma delta input clock value  */
+    uint32_t sd_clock;
+    /**< double update enable field  */
+    uint8_t en_second_update;
+    /**< First normal current sample trigger time  */
+    float firstSampTrigTime;
+    /**< First normal current sample trigger time  */
+    float secondSampTrigTime;
+    /**< output freq. of EPWM0  */
+    uint32_t epwm_out_freq;
+    /**< Over current threshold parameters  */
+    SDFM_ThresholdParms   threshold_parms[NUM_CH_SUPPORTED];
+    /**< SD clock source and clock inversion  */
+    SDFM_ClkSourceParms   clkPrms[3];
+    /**< Over current OSR  */
+    uint16_t ComFilterOsr;
+    /**< Normal current OSR  */
+    uint16_t FilterOsr;
+    /**< over current enable field */
+    uint8_t en_com;
+    /**< output samples base address*/
+    uint32_t samplesBaseAddress;
+    /**<enable fast detect*/
+    uint8_t en_fd;
+    /**<Fast detect configuration field*/
+    uint8_t fastDetect[NUM_SD_CH][NUM_FD_FIELD];
+    /**<Phase delay enbale */
+    uint8_t phase_delay;
+} SdfmPrms;
+
+
+/* Initialize ICSSG */
+int32_t initIcss(
+    uint8_t icssInstId,
+    uint8_t sliceId,
+    uint8_t saMuxMode,
+    PRUICSS_Handle *pPruIcssHandle
+);
+
+/* Initialize PRU core for SDFM */
+int32_t initPruSdfm(
+    PRUICSS_Handle pruIcssHandle,
+    uint8_t pruInstId,
+    SdfmPrms *pSdfmPrms,
+    sdfm_handle *pHSdfm
+);
+
+
+#endif /* _SDFM_H_ */
--- a/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/tisdfm_pruss_intc_mapping.h
+++ b/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/tisdfm_pruss_intc_mapping.h
@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2023, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/**
+* @file ti_uart_pruss_intc_mapping.h
+*
+* @brief Pruss interrupt mapping related macros
+*
+*/
+
+#ifndef TI_UART_PRUSS_INTC_MAPPING_H
+#define TI_UART_PRUSS_INTC_MAPPING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IEP_TIM_CAP_CMP_EVENT	7
+#define SYNC1_OUT_EVENT         13
+#define SYNC0_OUT_EVENT         14
+
+/* SYS_EVT_16-31 can be used for generating interrupts for IPC with hosts/prus etc */
+#define PRU_ARM_EVENT00         16
+#define PRU_ARM_EVENT01         17
+#define PRU_ARM_EVENT02         18
+#define PRU_ARM_EVENT03         19
+#define PRU_ARM_EVENT04         20
+#define PRU_ARM_EVENT05         21
+#define PRU_ARM_EVENT06         22
+#define PRU_ARM_EVENT07         23
+#define PRU_ARM_EVENT08         24
+#define PRU_ARM_EVENT09         25
+#define PRU_ARM_EVENT10         26
+#define PRU_ARM_EVENT11         27
+#define PRU_ARM_EVENT12         28
+#define PRU_ARM_EVENT13         29
+#define PRU_ARM_EVENT14         30
+#define PRU_ARM_EVENT15         31
+
+#define PRU0_RX_ERR32_EVENT     33
+#define PORT1_TX_UNDERFLOW	    39
+#define PORT1_TX_OVERFLOW	    40
+#define MII_LINK0_EVENT         41
+#define PORT1_RX_EOF_EVENT      42
+#define PRU1_RX_ERR32_EVENT     45
+#define PORT2_TX_UNDERFLOW	    51
+#define PORT2_TX_OVERFLOW	    53
+#define PORT2_RX_EOF_EVENT	    54
+#define MII_LINK1_EVENT         53
+
+#define CHANNEL0                0
+#define CHANNEL1                1
+#define CHANNEL2                2
+#define CHANNEL3                3
+#define CHANNEL4                4
+#define CHANNEL5                5
+#define CHANNEL6                6
+#define CHANNEL7                7
+#define CHANNEL8                8
+#define CHANNEL9                9
+
+#define PRU0                    0
+#define PRU1                    1
+#define PRU_EVTOUT0             2
+#define PRU_EVTOUT1             3
+#define PRU_EVTOUT2             4
+#define PRU_EVTOUT3             5
+#define PRU_EVTOUT4             6
+#define PRU_EVTOUT5             7
+#define PRU_EVTOUT6             8
+#define PRU_EVTOUT7             9
+
+#define PRU0_HOSTEN_MASK            ((uint32_t)0x0001)
+#define PRU1_HOSTEN_MASK            ((uint32_t)0x0002)
+#define PRU_EVTOUT0_HOSTEN_MASK     ((uint32_t)0x0004)
+#define PRU_EVTOUT1_HOSTEN_MASK     ((uint32_t)0x0008)
+#define PRU_EVTOUT2_HOSTEN_MASK     ((uint32_t)0x0010)
+#define PRU_EVTOUT3_HOSTEN_MASK     ((uint32_t)0x0020)
+#define PRU_EVTOUT4_HOSTEN_MASK     ((uint32_t)0x0040)
+#define PRU_EVTOUT5_HOSTEN_MASK     ((uint32_t)0x0080)
+#define PRU_EVTOUT6_HOSTEN_MASK     ((uint32_t)0x0100)
+#define PRU_EVTOUT7_HOSTEN_MASK     ((uint32_t)0x0200)
+
+#define SYS_EVT_POLARITY_LOW        0
+#define SYS_EVT_POLARITY_HIGH       1
+
+#define SYS_EVT_TYPE_PULSE          0
+#define SYS_EVT_TYPE_EDGE           1
+
+#define PRUICSS_INTC_INITDATA {   \
+{   IEP_TIM_CAP_CMP_EVENT, PRU_ARM_EVENT02, PRU_ARM_EVENT03, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, /* initializing member [0-15] for Misra C standards */ \
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,     /* initializing member [16-31] for Misra C standards */ \
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,     /* initializing member [32-47] for Misra C standards */ \
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},    /* initializing member [48-63] for Misra C standards */ \
+{ {IEP_TIM_CAP_CMP_EVENT,   CHANNEL1, SYS_EVT_POLARITY_HIGH, SYS_EVT_TYPE_PULSE},\
+  {PRU_ARM_EVENT02,         CHANNEL2, SYS_EVT_POLARITY_HIGH, SYS_EVT_TYPE_PULSE},\
+  {PRU_ARM_EVENT03,         CHANNEL3, SYS_EVT_POLARITY_HIGH, SYS_EVT_TYPE_PULSE},\
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [3] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [4] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [5] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [6] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [7] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [8] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [9] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [10] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [11] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [12] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [13] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [14] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [15] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [16] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [17] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [18] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [19] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [20] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [21] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [22] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [23] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [24] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [25] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [26] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [27] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [28] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [29] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [30] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [31] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [32] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [33] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [34] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [35] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [36] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [37] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [38] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [39] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [40] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [41] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [42] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [43] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [44] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [45] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [46] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [47] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [48] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [49] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [50] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [51] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [52] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [53] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [54] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [55] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [56] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [57] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [58] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [59] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [60] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [61] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}, /* initializing member [62] for Misra C standards */ \
+  {0xFF,0xFF,0xFF,0xFF}}, /* initializing member [63] for Misra C standards */ \
+  { {CHANNEL1, PRU1}, {CHANNEL2, PRU_EVTOUT0}, {CHANNEL3, PRU_EVTOUT1},\
+    {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, /* Initializing members [3,4,5] of array for Misra C standards */ \
+    {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF} }, /* Initializing members [6,7,8,9] of array for Misra C standards */ \
+  (PRU1_HOSTEN_MASK | PRU_EVTOUT0_HOSTEN_MASK | PRU_EVTOUT1_HOSTEN_MASK) \
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* TI_UART_PRUSS_INTC_MAPPING_H */
--- a/makefile.am243x
+++ b/makefile.am243x
@ -73,6 +73,8 @@ help:
 	@echo  $(MAKE) -s -C examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
+	@echo  $(MAKE) -s -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
+	@echo  $(MAKE) -s -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C examples/pruicss_pwm/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C examples/pruicss_pwm/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
@ -241,6 +243,8 @@ BUILD_COMBO_EXAMPLE_ALL += bissc_diagnostic_multi_channel_load_share_am243x-lp_r
 BUILD_COMBO_EXAMPLE_ALL += bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang
 BUILD_COMBO_EXAMPLE_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang
 BUILD_COMBO_EXAMPLE_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang
+BUILD_COMBO_EXAMPLE_ALL += icss_sdfm_three_channel_with_phase_compensation_am243x-evm_r5fss0-0_freertos_ti-arm-clang
+BUILD_COMBO_EXAMPLE_ALL += icss_sdfm_three_channel_with_phase_compensation_am243x-lp_r5fss0-0_freertos_ti-arm-clang
 BUILD_COMBO_EXAMPLE_ALL += pruicss_pwm_duty_cycle_am243x-evm_r5fss0-0_freertos_ti-arm-clang
 BUILD_COMBO_EXAMPLE_ALL += pruicss_pwm_duty_cycle_am243x-lp_r5fss0-0_freertos_ti-arm-clang
 # Various System Example Targets
@ -342,6 +346,12 @@ examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL)
 icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang:
 	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile all

+ icss_sdfm_three_channel_with_phase_compensation_am243x-evm_r5fss0-0_freertos_ti-arm-clang:
+	$(MAKE) -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all
+
+ icss_sdfm_three_channel_with_phase_compensation_am243x-lp_r5fss0-0_freertos_ti-arm-clang:
+	$(MAKE) -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile all
+
 pruicss_pwm_duty_cycle_am243x-evm_r5fss0-0_freertos_ti-arm-clang:
 	$(MAKE) -C examples/pruicss_pwm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all

@ -434,6 +444,8 @@ BUILD_COMBO_EXAMPLE_CLEAN_ALL += bissc_diagnostic_multi_channel_load_share_am243
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
+BUILD_COMBO_EXAMPLE_CLEAN_ALL += icss_sdfm_three_channel_with_phase_compensation_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
+BUILD_COMBO_EXAMPLE_CLEAN_ALL += icss_sdfm_three_channel_with_phase_compensation_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += pruicss_pwm_duty_cycle_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += pruicss_pwm_duty_cycle_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 # Various System Example Clean Targets
@ -535,6 +547,12 @@ examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL)
 icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
 	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile clean

+ icss_sdfm_three_channel_with_phase_compensation_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
+	$(MAKE) -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean
+
+ icss_sdfm_three_channel_with_phase_compensation_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
+	$(MAKE) -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile clean
+
 pruicss_pwm_duty_cycle_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
 	$(MAKE) -C examples/pruicss_pwm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean

@ -627,6 +645,8 @@ BUILD_COMBO_EXAMPLE_SCRUB_ALL += bissc_diagnostic_multi_channel_load_share_am243
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
+BUILD_COMBO_EXAMPLE_SCRUB_ALL += icss_sdfm_three_channel_with_phase_compensation_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
+BUILD_COMBO_EXAMPLE_SCRUB_ALL += icss_sdfm_three_channel_with_phase_compensation_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += pruicss_pwm_duty_cycle_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += pruicss_pwm_duty_cycle_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
 # Various System Example Scrub Targets
@ -728,6 +748,12 @@ examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL)
 icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub:
 	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile scrub

+ icss_sdfm_three_channel_with_phase_compensation_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub:
+	$(MAKE) -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
+
+ icss_sdfm_three_channel_with_phase_compensation_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub:
+	$(MAKE) -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
+
 pruicss_pwm_duty_cycle_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub:
 	$(MAKE) -C examples/pruicss_pwm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub

--- a/makefile.am64x
+++ b/makefile.am64x
@ -55,7 +55,6 @@ help:
 	@echo  $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
-	@echo  $(MAKE) -s -C examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C examples/pruicss_pwm/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
@ -189,7 +188,6 @@ BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_free
 BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang
 BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang
 BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang
-BUILD_COMBO_EXAMPLE_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang
 BUILD_COMBO_EXAMPLE_ALL += pruicss_pwm_duty_cycle_am64x-evm_r5fss0-0_freertos_ti-arm-clang
 # Various System Example Targets

@ -236,9 +234,6 @@ examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL)
 tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang:
 	$(MAKE) -C examples/position_sense/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all

- icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang:
-	$(MAKE) -C examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all
-
 pruicss_pwm_duty_cycle_am64x-evm_r5fss0-0_freertos_ti-arm-clang:
 	$(MAKE) -C examples/pruicss_pwm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all

@ -294,7 +289,6 @@ BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
-BUILD_COMBO_EXAMPLE_CLEAN_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += pruicss_pwm_duty_cycle_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 # Various System Example Clean Targets

@ -341,9 +335,6 @@ examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL)
 tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
 	$(MAKE) -C examples/position_sense/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean

- icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
-	$(MAKE) -C examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean
-
 pruicss_pwm_duty_cycle_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
 	$(MAKE) -C examples/pruicss_pwm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean

@ -399,7 +390,6 @@ BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
-BUILD_COMBO_EXAMPLE_SCRUB_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += pruicss_pwm_duty_cycle_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
 # Various System Example Scrub Targets

@ -446,9 +436,6 @@ examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL)
 tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub:
 	$(MAKE) -C examples/position_sense/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub

- icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub:
-	$(MAKE) -C examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
-
 pruicss_pwm_duty_cycle_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub:
 	$(MAKE) -C examples/pruicss_pwm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub

--- a/makefile_projectspec.am243x
+++ b/makefile_projectspec.am243x
@ -30,6 +30,8 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += bissc_diagnostic_multi_channel_load
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += icss_sdfm_three_channel_with_phase_compensation_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += icss_sdfm_three_channel_with_phase_compensation_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += pruicss_pwm_duty_cycle_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += pruicss_pwm_duty_cycle_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
 # Various System Example Projectspec Build Targets
@ -131,6 +133,12 @@ all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL)
 icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build:
 	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all

+ icss_sdfm_three_channel_with_phase_compensation_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build:
+	$(MAKE) -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
+
+ icss_sdfm_three_channel_with_phase_compensation_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build:
+	$(MAKE) -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
+
 pruicss_pwm_duty_cycle_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build:
 	$(MAKE) -C examples/pruicss_pwm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all

@ -224,6 +232,8 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += bissc_diagnostic_multi_channel_load
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += icss_sdfm_three_channel_with_phase_compensation_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += icss_sdfm_three_channel_with_phase_compensation_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += pruicss_pwm_duty_cycle_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += pruicss_pwm_duty_cycle_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 # Various System Example Projectspec Clean Targets
@ -325,6 +335,12 @@ clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL)
 icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
 	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean

+ icss_sdfm_three_channel_with_phase_compensation_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
+	$(MAKE) -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
+
+ icss_sdfm_three_channel_with_phase_compensation_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
+	$(MAKE) -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
+
 pruicss_pwm_duty_cycle_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
 	$(MAKE) -C examples/pruicss_pwm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean

@ -418,6 +434,8 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += bissc_diagnostic_multi_channel_loa
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += icss_sdfm_three_channel_with_phase_compensation_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += icss_sdfm_three_channel_with_phase_compensation_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += pruicss_pwm_duty_cycle_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += pruicss_pwm_duty_cycle_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
 # Various System Example Projectspec Export Targets
@ -519,6 +537,12 @@ export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL)
 icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export:
 	$(MAKE) -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export

+ icss_sdfm_three_channel_with_phase_compensation_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export:
+	$(MAKE) -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
+
+ icss_sdfm_three_channel_with_phase_compensation_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export:
+	$(MAKE) -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
+
 pruicss_pwm_duty_cycle_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export:
 	$(MAKE) -C examples/pruicss_pwm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export

@ -637,6 +661,8 @@ help:
 	@echo  $(MAKE) -s -C examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
+	@echo  $(MAKE) -s -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
+	@echo  $(MAKE) -s -C examples/current_sense/icss_sdfm_three_channel_with_phase_compensation/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C examples/pruicss_pwm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C examples/pruicss_pwm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
--- a/makefile_projectspec.am64x
+++ b/makefile_projectspec.am64x
@ -14,7 +14,6 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_multi_channel_am64x
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build
-BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += pruicss_pwm_duty_cycle_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build
 # Various System Example Projectspec Build Targets

@ -61,9 +60,6 @@ all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL)
 tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build:
 	$(MAKE) -C examples/position_sense/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all

- icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build:
-	$(MAKE) -C examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
-
 pruicss_pwm_duty_cycle_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build:
 	$(MAKE) -C examples/pruicss_pwm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all

@ -120,7 +116,6 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_multi_channel_am64x
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
-BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += pruicss_pwm_duty_cycle_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 # Various System Example Projectspec Clean Targets

@ -167,9 +162,6 @@ clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL)
 tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
 	$(MAKE) -C examples/position_sense/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean

- icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
-	$(MAKE) -C examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
-
 pruicss_pwm_duty_cycle_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
 	$(MAKE) -C examples/pruicss_pwm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean

@ -226,7 +218,6 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_multi_channel_am64
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export
-BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += pruicss_pwm_duty_cycle_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export
 # Various System Example Projectspec Export Targets

@ -273,9 +264,6 @@ export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL)
 tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export:
 	$(MAKE) -C examples/position_sense/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export

- icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export:
-	$(MAKE) -C examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
-
 pruicss_pwm_duty_cycle_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export:
 	$(MAKE) -C examples/pruicss_pwm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export

@ -357,7 +345,6 @@ help:
 	@echo  $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
-	@echo  $(MAKE) -s -C examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C examples/pruicss_pwm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/current_sense/sdfm/firmware/am64x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/endat/firmware/multi_channel_load_share/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
--- a/source/current_sense/sdfm/driver/sdfm_drv.c
+++ b/source/current_sense/sdfm/driver/sdfm_drv.c
@ -112,12 +112,11 @@
 #define SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT_MASK ( 3 )

 /* Internal structure for managing each PRU SD */
-//static sdfm g_sdfm[NUM_PRU] = {
 SDFM g_sdfm[NUM_PRU] = {
-    {PRU_ID_0,0,0,0, NULL},
-    {PRU_ID_1,0,0,0, NULL},
+    {PRU_ID_0,0,0,0,0, NULL},
+    {PRU_ID_1,0,0,0,0, NULL},
 };
-// static sdfm g_sdfm[NUM_PRU];
+

 /* Initialize SDFM instance */
 sdfm_handle SDFM_init(uint8_t pru_id)
@ -343,6 +342,41 @@ void SDFM_clearPwmTripStatus(sdfm_handle h_sdfm, uint8_t pwmIns)
    HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_PWM0 + pwmIns * 4, regval);

 }
+/*Measure Phase delay*/
+float SDFM_measureClockPhaseDelay(sdfm_handle h_sdfm, uint16_t clkEdg)
+{
+    /*enable phase delay measurement*/
+    h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.en_phase_delay = 1;
+    /*waiting till measurment done */
+    uint8_t ack = h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.en_phase_delay & SDFM_PHASE_DELAY_ACK_BIT_MASK;
+    while(ack)
+    {
+       ack = h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.en_phase_delay & SDFM_PHASE_DELAY_ACK_BIT_MASK ;
+    }
+
+
+   uint16_t nEdge = h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_edge;
+   float temp = h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_phase_delay;
+   /*avg*/
+    temp = temp/SDFM_PHASE_DELAY_CAL_LOOP_SIZE;
+   /*check data reading edge(clk polarity) & nearest edge */
+   if(nEdge == clkEdg)
+   {
+      /*PRU cycles for half SD clock period*/
+      uint32_t pruCycles = ceil(((float)h_sdfm->pru_core_clk)/(2*h_sdfm->sdfm_clock));
+      h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_phase_delay = pruCycles - temp;
+   }
+   else
+   {
+      /*PRU cycles for one SD clock period*/
+      uint32_t pruCycles = ceil((float)(h_sdfm->pru_core_clk/(h_sdfm->sdfm_clock)));
+      h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_phase_delay = pruCycles - temp;
+
+   }
+    /*conversion from PRU cycle to ns */
+    float phaseDelay =  ((float)h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_phase_delay * 1000000000)/h_sdfm->pru_core_clk;
+    return phaseDelay;
+}
 /* SDFM global enable */
 void SDFM_enable(sdfm_handle h_sdfm)
 {
--- a/source/current_sense/sdfm/firmware/icssg_sdfm.h
+++ b/source/current_sense/sdfm/firmware/icssg_sdfm.h
@ -111,12 +111,14 @@
 /* SDFM Configuration*/
 #define SDFM_CFG_SD_CH_ID_OFFSET             ( 0x10 )
 #define SDFM_CFG_SD_EN_COMP_OFFSET           ( 0x14 )
-#define SDFM_CFG_SD_ZC_ENABLE_OFFSET         ( 0x16 )
-#define SDFM_CFG_SD_EN_FD_OFFSET             ( 0x18 )
+#define SDFM_CFG_SD_EN_FD_OFFSET             ( 0x16 )
+#define SDFM_CFG_SD_EN_PHASE_DELAY           ( 0x17 )
+#define SDFM_CFG_SD_CLOCK_PHASE_DELAY        ( 0x18 )
+


 /*SDFM channel offsets*/
-/*ch0 offset*/
+/*Ch0 offset*/
 #define SDFM_CFG_CH0_CH_ID_OFFSET            ( 0x1C )
 #define SDFM_CFG_CH0_FILTER_TYPE_OFFSET      ( 0x1D )
 #define SDFM_CFG_CH0_OSR_OFFSET              ( 0x1E )
@ -141,7 +143,7 @@
 #define SDFM_CFG_LOW_THR_CH0_CLR_VAL_ADDR_OFFSET    ( 0x50 )


-/*ch1 offsets*/
+/*Ch1 offsets*/
 #define SDFM_CFG_CH1_CH_ID_OFFSET            ( 0x60 )
 #define SDFM_CFG_CH1_FILTER_TYPE_OFFSET      ( 0x61 )
 #define SDFM_CFG_CH1_OSR_OFFSET              ( 0x62 )
@ -167,7 +169,7 @@



-/*ch2 offsets*/
+/*Ch2 offsets*/
 #define SDFM_CFG_CH2_CH_ID_OFFSET            ( 0xA4 )
 #define SDFM_CFG_CH2_FILTER_TYPE_OFFSET      ( 0xA5 )
 #define SDFM_CFG_CH2_OSR_OFFSET              ( 0xA6 )
@ -193,22 +195,27 @@
 #define SDFM_CFG_LOW_THR_CH2_CLR_VAL_ADDR_OFFSET    ( 0xD8 )


-/*sample timing offset*/
+/*Sample timing offset*/
 #define SDFM_CFG_EN_DOUBLE_UPDATE                   ( 0xE8 )
 #define FW_REG_SDFM_CFG_FIRST_TRIG_SAMPLE_TIME      ( 0xEC )
 #define FW_REG_SDFM_CFG_SECOND_TRIG_SAMPLE_TIME     ( 0xF0 )
 #define SDFM_CFG_NC_PRD_IEP_CNT_OFFSET              ( 0xF4)

-/* output sample buffer base address offset*/
+/* Output sample buffer base address offset*/
 #define SDFM_CFG_OUT_SAMP_BUF_BASE_ADD_OFFSET         ( 0xF8 )

 /*Firmware version offset*/
 #define SDFM_FIRMWARE_VERSION_OFFSET                  (0xFC)

-/*Debug */
-#define SDFM_DUBUG_OFFSET         ( 0x104 )
+/*Local store offset for Phase delay: 2 byte */
+#define SDFM_CFG_DELAY_STORE_OFFSET                   ( 0x110 )

-/*output sample offset*/
+
+/*Phase delay offset */
+/*Debug */
+#define SDFM_DUBUG_OFFSET         ( 0x10F )
+
+/*Output sample offset*/
 #define SDFM_CFG_OUT_SAMP_BUF_OFFSET                   (0x00)
 /*
    Firmware register bit fields
--- a/source/current_sense/sdfm/firmware/sdfm.asm
+++ b/source/current_sense/sdfm/firmware/sdfm.asm
@ -101,12 +101,26 @@ SDFM_ENTRY:
        ; Write C24 block index for access to FW registers
        WRITE_C24_BLK_INDEX C24_BLK_INDEX_FW_REGS_VAL

+PHASE_DELAY_CAL:
+        ;check phase delay measurment active
+        LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_SD_EN_PHASE_DELAY, 1
+        QBBC    SKIP_PHASE_DELAY_CAL, TEMP_REG0.b0, 0
+        JAL     RET_ADDR_REG, SDFM_CLOCK_PHASE_COMPENSATION
+        ;acknowledge 
+        CLR     TEMP_REG0, TEMP_REG0, 0
+        SBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_SD_EN_PHASE_DELAY, 1       
+SKIP_PHASE_DELAY_CAL:
+
+

 ;
 ; Check SDFM global enable & set SDFM global enable acknowledge to inform R5 core.
 ; If SDFM global enable not set, wait for SDFM global enable from R5.
 ;
 check_sdfm_en:
+        ;Check for phase delay measurment
+        LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_SD_EN_PHASE_DELAY, 1
+        QBBS    PHASE_DELAY_CAL, TEMP_REG0.b0, 0
        ; Check SDFM global enable
        LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_LOC_DMEM, SDFM_EN_OFFSET, SDFM_EN_SZ
        QBBC    check_sdfm_en, TEMP_REG0.b0, 0                      ; If SDFM_EN not set, wait to set sdfm enable
@ -206,7 +220,6 @@ init_sdfm_cont:



-
        .if $isdefed("SDFM_PRU_CORE") ; no IEP on RTU
        ; Start IEP
        LBCO    &TEMP_REG0.b0, CT_PRU_ICSSG_IEP0, ICSSG_IEP_GLOBAL_CFG_REG, 1
@ -987,6 +1000,49 @@ SDFM_MASK_SKIP1_CH2:

       JMP     RET_ADDR_REG
      
+
+;Phase delay measurement
+; Measure Phase Difference between MCLK and MDATA
+; PRU mode is GPI mode (default)
+;     1)Waits for rising edge of DATA using wbs instruction
+;        ->GPO1 for SD_D
+;     2)check status of sd clock pin when data line is high. 
+;        ->GPO16 for SD_clock
+;     3)if clock line is high then call falling edge macro otherwise raising edge macro
+;   -> macro calcultes time between rising edge of data and upcoming nearest clock edge (rising or falling)
+;   -> store 8 times calculted time into DMEM
+SDFM_CLOCK_PHASE_COMPENSATION:
+        ;decide mask 
+        LDI32 TEMP_REG1, SDFM_11_MASK
+        ; waiting zero
+        wbc  R31.b0, 1
+        ;waiting for rising edge of sd data
+        wbs  R31.b0, 1
+        ; check nereset clock edge from starting point of bit
+        AND  TEMP_REG0, R31, TEMP_REG1
+        ;Max value
+        LDI   TEMP_REG2, 0
+        QBEQ   DELAY_CAL_FOR_FALLING_EDGE, TEMP_REG0, TEMP_REG1
+        LDI TEMP_REG1, 0
+
+        LOOP    SDFM_CLOCK_PHASE_COMPENSATION_LOOP, 8
+        M_SDFM_PHASE_DELAY_FOR_RAISING_EDGE
+SDFM_CLOCK_PHASE_COMPENSATION_LOOP:
+        JMP  END_PHASE_DELAY
+DELAY_CAL_FOR_FALLING_EDGE:
+        LDI TEMP_REG1, 0
+        LOOP    SDFM_CLOCK_PHASE_COMPENSATION_LOOP1, 8
+        M_SDFM_PHASE_DELAY_FOR_FALLING_EDGE
+SDFM_CLOCK_PHASE_COMPENSATION_LOOP1:
+END_PHASE_DELAY:
+        ;storing phase delay (8 times) and edge status in DMEM 
+        ;final result in TEMP_REG1 register
+        LSR    TEMP_REG0, TEMP_REG1.w0, 3
+        SUB  TEMP_REG0, TEMP_REG2,TEMP_REG0
+        QBLT   SDFM_CLOCK_PHASE_COMPENSATION, TEMP_REG0, 1
+        SBCO  &TEMP_REG1, CT_PRU_ICSSG_LOC_DMEM, SDFM_CFG_SD_CLOCK_PHASE_DELAY, 4
+        JMP     RET_ADDR_REG
+
 ;
 ; Initialize SD (eCAP PWM) clock
 ;
@ -1022,3 +1078,4 @@ init_sd_clock:
        SBCO    &TEMP_REG0, CT_PRU_ICSSG_ECAP, ICSSG_eCAP_ECCTL1, 4

        JMP     RET_ADDR_REG
+
--- a/source/current_sense/sdfm/firmware/sdfm.h
+++ b/source/current_sense/sdfm/firmware/sdfm.h
@ -271,6 +271,9 @@ TASKS_MGR_TS1_PC_S0             .set 0x08
 TASKS_MGR_TS1_PC_S1             .set 0x0C
 TASKS_MGR_TS1_GEN_CFG1          .set 0x38

+;MASK for phase delay
+SDFM_11_MASK                    .set  0x00010002
+SDFM_01_MASK                    .set  0x00000002
 TM_YIELD_XID                    .set 252

 ;IEP_CFG
--- a/source/current_sense/sdfm/firmware/sdfm_bin.h
+++ b/source/current_sense/sdfm/firmware/sdfm_bin.h
@ -14,16 +14,23 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x24000001,
 0x81200b01,
 0x10000000,
+0x91171801,
+0xc9000104,
+0x2301b899,
+0x1d00e1e1,
+0x81171801,
+0x91171801,
+0xd70001fa,
 0x91001801,
-0xcf0001ff,
+0xcf0001fd,
 0x1f00e1e1,
 0x81011801,
 0x91340401,
 0x1f01e1e1,
 0x81340401,
-0x23010499,
-0x32800000,
 0x23010b99,
+0x32800000,
+0x23011299,
 0x240c00c2,
 0x24000082,
 0x91021801,
@ -47,13 +54,13 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x0b04e1e1,
 0x110fe1e2,
 0x10020256,
-0x23012599,
-0x2301b199,
-0x23012999,
-0x23015999,
-0x23019e99,
+0x23012c99,
+0x23024d99,
+0x23013099,
+0x23016099,
+0x2301a599,
 0x1f19fefe,
-0x2301a799,
+0x2301ae99,
 0x240fffd5,
 0x24ffff95,
 0x240000d4,
@ -66,7 +73,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x81001a01,
 0x9114189a,
 0xd1009a02,
-0x21004300,
+0x21004a00,
 0xc9019a26,
 0x10161602,
 0x09020202,
@ -261,7 +268,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x10000000,
 0x24000b01,
 0x81000a01,
-0x2400b781,
+0x2400be81,
 0x810c0a81,
 0x24140081,
 0x81380a81,
@ -296,7 +303,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x2effa381,
 0x2f052381,
 0x20990000,
-0x91181804,
+0x91161804,
 0x240000e1,
 0x91103882,
 0x3102002c,
@ -313,7 +320,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x09015341,
 0x13414141,
 0x13804141,
-0x21015400,
+0x21015b00,
 0x6836030d,
 0x91621801,
 0xc9010417,
@ -326,7 +333,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x09015341,
 0x13414141,
 0x13804141,
-0x21015400,
+0x21015b00,
 0x6856030c,
 0x91a61801,
 0xc902040a,
@ -344,7 +351,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0xe0e33801,
 0x0b04e2e2,
 0x20990000,
-0x91181804,
+0x91161804,
 0x240000e1,
 0x91103882,
 0x31020041,
@ -368,7 +375,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x09033b21,
 0x09011b41,
 0x13414141,
-0x21019900,
+0x2101a000,
 0x68360314,
 0x24000081,
 0x917c1841,
@ -388,7 +395,7 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x09033b21,
 0x09011b41,
 0x13414141,
-0x21019900,
+0x2101a000,
 0x68560313,
 0x24000081,
 0x91c01841,
@ -432,6 +439,155 @@ const uint32_t pru_SDFM_PRU0_image_0[] = {
 0x13042121,
 0x80e22481,
 0x20990000,
+0x240001c2,
+0x24000282,
+0xd1011f00,
+0xc9011f00,
+0x10e2ffe1,
+0x240000e3,
+0x50e2e146,
+0x240000e2,
+0x31070043,
+0xd1011f00,
+0xc9011f00,
+0xd1005f10,
+0xd1005f12,
+0xd1005f14,
+0xd1005f16,
+0xd1005f18,
+0xd1005f1a,
+0xd1005f1c,
+0xd1005f1e,
+0xd1005f20,
+0xd1005f22,
+0xd1005f24,
+0xd1005f26,
+0xd1005f28,
+0xd1005f2a,
+0xd1005f2c,
+0xd1005f2e,
+0x01018282,
+0x1b01e3e3,
+0x21020200,
+0x01028282,
+0x1b02e3e3,
+0x21020200,
+0x01038282,
+0x1b03e3e3,
+0x21020200,
+0x01048282,
+0x1b04e3e3,
+0x21020200,
+0x01058282,
+0x1b05e3e3,
+0x21020200,
+0x01068282,
+0x1b06e3e3,
+0x21020200,
+0x01078282,
+0x1b07e3e3,
+0x21020200,
+0x01088282,
+0x1b08e3e3,
+0x21020200,
+0x01098282,
+0x1b09e3e3,
+0x21020200,
+0x010a8282,
+0x1b0ae3e3,
+0x21020200,
+0x010b8282,
+0x1b0be3e3,
+0x21020200,
+0x010c8282,
+0x1b0ce3e3,
+0x21020200,
+0x010d8282,
+0x1b0de3e3,
+0x21020200,
+0x010e8282,
+0x1b0ee3e3,
+0x21020200,
+0x010f8282,
+0x1b0fe3e3,
+0x21020200,
+0x01108282,
+0x1b10e3e3,
+0x24000042,
+0x21024800,
+0x240000e2,
+0x31070043,
+0xd1011f00,
+0xc9011f00,
+0xc9005f10,
+0xc9005f12,
+0xc9005f14,
+0xc9005f16,
+0xc9005f18,
+0xc9005f1a,
+0xc9005f1c,
+0xc9005f1e,
+0xc9005f20,
+0xc9005f22,
+0xc9005f24,
+0xc9005f26,
+0xc9005f28,
+0xc9005f2a,
+0xc9005f2c,
+0xc9005f2e,
+0x01018282,
+0x1b01e3e3,
+0x21024700,
+0x01028282,
+0x1b02e3e3,
+0x21024700,
+0x01038282,
+0x1b03e3e3,
+0x21024700,
+0x01048282,
+0x1b04e3e3,
+0x21024700,
+0x01058282,
+0x1b05e3e3,
+0x21024700,
+0x01068282,
+0x1b06e3e3,
+0x21024700,
+0x01078282,
+0x1b07e3e3,
+0x21024700,
+0x01088282,
+0x1b08e3e3,
+0x21024700,
+0x01098282,
+0x1b09e3e3,
+0x21024700,
+0x010a8282,
+0x1b0ae3e3,
+0x21024700,
+0x010b8282,
+0x1b0be3e3,
+0x21024700,
+0x010c8282,
+0x1b0ce3e3,
+0x21024700,
+0x010d8282,
+0x1b0de3e3,
+0x21024700,
+0x010e8282,
+0x1b0ee3e3,
+0x21024700,
+0x010f8282,
+0x1b0fe3e3,
+0x21024700,
+0x01108282,
+0x1b10e3e3,
+0x24000142,
+0x0b0382e1,
+0x04e1e3e1,
+0x4f01e16e,
+0x81183882,
+0x20990000,
 0x240280c1,
 0x24000081,
 0x81282381,
--- a/source/current_sense/sdfm/firmware/sdfm_macros.h
+++ b/source/current_sense/sdfm/firmware/sdfm_macros.h
@ -115,4 +115,217 @@ M_PRU_TM_ENABLE .macro
 ;Disable task manager
 M_PRU_TM_DISABLE .macro
    tsen 0
-    .endm
+    .endm
+
+
+;************************************************************************************
+;
+;   Macro: M_SDFM_PHASE_DELAY_FOR_RAISING_EDGE
+;
+;   Calculate number of PRU cycles between data raising edge  and upcoming nearest clock raising edge 
+;
+;   Invokes:
+;       None
+;
+;   Parameters:
+;      None
+;
+;   Results: TEMP_REG1.w0 -> PRU cycles
+;            TEMP_REG1.w2 -> Raising Edge status 
+;            TEMP_REG2    -> MAX PRU cyles between clk & data edge 
+;
+;
+;************************************************************************************
+M_SDFM_PHASE_DELAY_FOR_RAISING_EDGE .macro
+; waiting for one on SD data line 
+        wbc  R31.b0, 1
+        ;waiting for rising edge of sd data
+        wbs  R31.b0, 1
+        QBBS   DELAY_1_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_2_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_3_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_4_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_5_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_6_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_7_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_8_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_9_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_10_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_11_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_12_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_13_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_14_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_15_PRU_CYCLE,  R31.b2, 0
+        QBBS   DELAY_16_PRU_CYCLE,  R31.b2, 0
+DELAY_1_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 1 
+        MAX  TEMP_REG2, TEMP_REG2,   1
+        JMP  DELAY_DONE   
+DELAY_2_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 2 
+        MAX  TEMP_REG2, TEMP_REG2,   2
+        JMP  DELAY_DONE   
+DELAY_3_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 3 
+        MAX  TEMP_REG2, TEMP_REG2,   3
+        JMP  DELAY_DONE   
+DELAY_4_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 4 
+        MAX  TEMP_REG2, TEMP_REG2,   4
+        JMP  DELAY_DONE   
+DELAY_5_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 5 
+        MAX  TEMP_REG2, TEMP_REG2,   5
+        JMP  DELAY_DONE   
+DELAY_6_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 6 
+        MAX  TEMP_REG2, TEMP_REG2,   6
+        JMP  DELAY_DONE   
+DELAY_7_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 7 
+        MAX  TEMP_REG2, TEMP_REG2,   7
+        JMP  DELAY_DONE   
+DELAY_8_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 8 
+        MAX  TEMP_REG2, TEMP_REG2,   8
+        JMP  DELAY_DONE   
+DELAY_9_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 9 
+        MAX  TEMP_REG2, TEMP_REG2,   9
+        JMP  DELAY_DONE   
+DELAY_10_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 10
+        MAX  TEMP_REG2, TEMP_REG2,   10 
+        JMP  DELAY_DONE   
+DELAY_11_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 11 
+        MAX  TEMP_REG2, TEMP_REG2,   11
+        JMP  DELAY_DONE   
+DELAY_12_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 12 
+        MAX  TEMP_REG2, TEMP_REG2,   12
+        JMP  DELAY_DONE   
+DELAY_13_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 13
+        MAX  TEMP_REG2, TEMP_REG2,   13 
+        JMP  DELAY_DONE   
+DELAY_14_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 14
+        MAX  TEMP_REG2, TEMP_REG2,   14 
+        JMP  DELAY_DONE   
+DELAY_15_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 15
+        MAX  TEMP_REG2, TEMP_REG2,   15 
+        JMP  DELAY_DONE   
+DELAY_16_PRU_CYCLE:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 16
+        MAX  TEMP_REG2, TEMP_REG2,   16  
+DELAY_DONE:
+        LDI  TEMP_REG1.b2, 0  ; status of edge is 0 means rising edge
+       .endm
+  
+;************************************************************************************
+;
+;   Macro: M_SDFM_PHASE_DELAY_FOR_FALLING_EDGE
+;
+;  Calculate number of PRU cycles between data raising edge  and upcoming nearest clock falling edge 
+;
+;   Invokes:
+;       None
+;
+;   Parameters:
+;      None
+;
+;   Results: TEMP_REG1.w0 -> PRU cycles
+;            TEMP_REG1.w2 -> falling edage status 
+;            TEMP_REG2    -> MAX PRU cyles between clk & data edge 
+;
+;
+;************************************************************************************ 
+M_SDFM_PHASE_DELAY_FOR_FALLING_EDGE .macro
+; waiting for one on SD data line 
+        wbc  R31.b0, 1
+        ;waiting for rising edge of sd data
+        wbs  R31.b0, 1
+        QBBC   DELAY_1_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_2_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_3_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_4_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_5_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_6_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_7_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_8_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_9_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_10_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_11_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_12_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_13_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_14_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_15_PRU_CYCLE1,  R31.b2, 0
+        QBBC   DELAY_16_PRU_CYCLE1,  R31.b2, 0
+DELAY_1_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 1 
+        MAX  TEMP_REG2, TEMP_REG2,   1
+        JMP  DELAY_DONE1   
+DELAY_2_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 2
+        MAX  TEMP_REG2, TEMP_REG2,   2 
+        JMP  DELAY_DONE1   
+DELAY_3_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 3
+        MAX  TEMP_REG2, TEMP_REG2,   3 
+        JMP  DELAY_DONE1   
+DELAY_4_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 4
+        MAX  TEMP_REG2, TEMP_REG2,   4 
+        JMP  DELAY_DONE1   
+DELAY_5_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 5
+        MAX  TEMP_REG2, TEMP_REG2,   5 
+        JMP  DELAY_DONE1   
+DELAY_6_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 6
+        MAX  TEMP_REG2, TEMP_REG2,   6 
+        JMP  DELAY_DONE1   
+DELAY_7_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 7
+        MAX  TEMP_REG2, TEMP_REG2,   7 
+        JMP  DELAY_DONE1   
+DELAY_8_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 8
+        MAX  TEMP_REG2, TEMP_REG2,   8 
+        JMP  DELAY_DONE1   
+DELAY_9_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 9
+        MAX  TEMP_REG2, TEMP_REG2,   9 
+        JMP  DELAY_DONE1   
+DELAY_10_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 10 
+        MAX  TEMP_REG2, TEMP_REG2,   10
+        JMP  DELAY_DONE1   
+DELAY_11_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 11
+        MAX  TEMP_REG2, TEMP_REG2,   11 
+        JMP  DELAY_DONE1   
+DELAY_12_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 12
+        MAX  TEMP_REG2, TEMP_REG2,   12 
+        JMP  DELAY_DONE1   
+DELAY_13_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 13
+        MAX  TEMP_REG2, TEMP_REG2,   13 
+        JMP  DELAY_DONE1   
+DELAY_14_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 14
+        MAX  TEMP_REG2, TEMP_REG2,   14 
+        JMP  DELAY_DONE1   
+DELAY_15_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 15
+        MAX  TEMP_REG2, TEMP_REG2,   15 
+        JMP  DELAY_DONE1   
+DELAY_16_PRU_CYCLE1:
+        ADD  TEMP_REG1.w0,  TEMP_REG1.w0, 16
+        MAX  TEMP_REG2, TEMP_REG2,   16  
+DELAY_DONE1:
+        LDI  TEMP_REG1.b2, 1   ; status of edge is 1 means falling edge
+       .endm
--- a/source/current_sense/sdfm/include/sdfm_api.h
+++ b/source/current_sense/sdfm/include/sdfm_api.h
@ -328,6 +328,16 @@ uint32_t SDFM_getPwmTripStatus(sdfm_handle h_sdfm, uint8_t pwmIns);
 void SDFM_clearPwmTripStatus(sdfm_handle h_sdfm, uint8_t pwmIns); 


+/**
+ *
+ *  \brief  Measure Clock phase compensation 
+ *
+ *  \param[in]  h_sdfm          SDFM handle
+ *  \param[in]  clEdg           Clock polarity: 1 -> falling edge, 0 -> raising edge
+ *
+ *  \retval     Phase delay   in nano sec
+ */
+float SDFM_measureClockPhaseDelay(sdfm_handle h_sdfm, uint16_t clEdg);
 /** @} */

 #ifdef __cplusplus
--- a/source/current_sense/sdfm/include/sdfm_drv.h
+++ b/source/current_sense/sdfm/include/sdfm_drv.h
@ -40,6 +40,7 @@ extern "C" {

 #include <drivers/soc.h>
 #include <drivers/pruicss.h>
+#include  <math.h>



@ -121,6 +122,9 @@ extern "C" {
 #define ICSSG_SD_SAMP_CH_BUF_SZ  ( 128 )
 #define NUM_CH_SUPPORTED        ( 3 )

+#define SDFM_PHASE_DELAY_ACK_BIT_MASK   (1)
+#define SDFM_PHASE_DELAY_CAL_LOOP_SIZE  (8)
+
 /* ========================================================================== */
 /*                         Structures                                         */
 /* ========================================================================== */
@ -200,14 +204,14 @@ typedef struct SDFM_ChCtrl_s
    volatile uint32_t    sdfm_ch_id;
    /**< bit-field to enable comparators for individual SDFM channels, BitN:ChN, non-zero to enable */
    volatile uint16_t    enable_comparator;
-    /**< bit-field to set the output data format for individual SDFM channels, BitN:ChN */
-    volatile uint16_t    output_data_format;
    /**< bit-field to enable fast detect  for individual SDFM channels, BitN:ChN, non-zero to enable */
    volatile uint8_t    enFastDetect;
-     /**< reserved */
-     volatile uint8_t   reserved1;
-    /**< reserved */
-    volatile uint16_t    reserved2;
+     /**< enable phase delay calcualtion */
+    volatile uint8_t    en_phase_delay;
+    /**< Clock phase delay */
+     volatile uint16_t   clock_phase_delay;
+    /**<nearest clock edge status of data*/
+    volatile uint16_t    clock_edge;

 } SDFM_ChCtrl;

@ -324,6 +328,7 @@ typedef struct SDFM_s {
    uint8_t pru_id;
    uint32_t sdfm_clock;
    uint32_t iep_clock;
+    uint32_t pru_core_clk;
    uint8_t  iep_inc;
    SDFM_Interface * p_sdfm_interface;
    SDFM_SampleOutInterface *sampleOutputInterface;