| %SDFM
diff --git a/examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index 8b8309d..69640f4 100644
--- a/examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -103,9 +103,6 @@ SECTIONS
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
-
- /* TCM used by ICSS PRU to write sdfm sample output */
- .gSdfmSampleOutput : {} align(4) > R5F_TCMB0
}
/*
diff --git a/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index 8b8309d..69640f4 100644
--- a/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -103,9 +103,6 @@ SECTIONS
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
-
- /* TCM used by ICSS PRU to write sdfm sample output */
- .gSdfmSampleOutput : {} align(4) > R5F_TCMB0
}
/*
diff --git a/examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index 2fe832e..c4848c3 100644
--- a/examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -103,9 +103,6 @@ SECTIONS
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
-
- /* TCM used by ICSS PRU to write sdfm sample output */
- .gSdfmSampleOutput : {} align(4) > R5F_TCMB0
}
/*
diff --git a/examples/position_sense/bissc_diagnostic/bissc_diagnostic.c b/examples/position_sense/bissc_diagnostic/bissc_diagnostic.c
new file mode 100644
index 0000000..fde45e2
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/bissc_diagnostic.c
@@ -0,0 +1,592 @@
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include "ti_drivers_open_close.h"
+#include "ti_board_open_close.h"
+#include
+#define PRUICSS_SLICEx PRUICSS_PRUx
+#if PRUICSS_SLICEx
+#define PRUICSS_TXPRUx PRUICSS_TX_PRU1
+#define PRUICSS_RTUPRUx PRUICSS_RTU_PRU1
+#else
+#define PRUICSS_TXPRUx PRUICSS_TX_PRU0
+#define PRUICSS_RTUPRUx PRUICSS_RTU_PRU0
+#endif
+
+
+
+#if (CONFIG_BISSC0_MODE == BISSC_MODE_MULTI_CHANNEL_SINGLE_PRU)
+#include
+#endif
+
+#if (CONFIG_BISSC0_CHANNEL0) && (CONFIG_BISSC0_LOAD_SHARE_MODE)
+#include
+#endif
+
+#if (CONFIG_BISSC0_CHANNEL1) && (CONFIG_BISSC0_LOAD_SHARE_MODE)
+#include
+#endif
+
+#if (CONFIG_BISSC0_CHANNEL2) && (CONFIG_BISSC0_LOAD_SHARE_MODE)
+#include
+#endif
+
+#if (CONFIG_BISSC0_MODE == BISSC_MODE_SINGLE_CHANNEL_SINGLE_PRU)
+#include
+#endif
+
+#define WAIT_5_SECOND (5000)
+#define WAIT_2_SECOND (2000)
+
+struct bissc_priv *priv;
+/** \brief Global Structure pointer holding PRUICSS1 memory Map. */
+
+PRUICSS_Handle gPruIcssXHandle;
+
+int32_t multichannel = 0, totalchannels = 0, mask = 0, loadshare = 0;
+
+static void bissc_pruicss_init(void)
+{
+ int32_t status = SystemP_FAILURE;
+ int32_t size;
+ gPruIcssXHandle = PRUICSS_open(CONFIG_PRU_ICSS0);
+ /* Configure g_mux_en to 1 in ICSSG_SA_MX_REG Register. */
+ status = PRUICSS_setSaMuxMode(gPruIcssXHandle, PRUICSS_SA_MUX_MODE_SD_ENDAT);
+ DebugP_assert(SystemP_SUCCESS == status);
+ /* clear ICSS0 PRUx data RAM */
+ size = PRUICSS_initMemory(gPruIcssXHandle, PRUICSS_DATARAM(PRUICSS_PRUx));
+ DebugP_assert(size);
+ if(loadshare)
+ {
+ status = PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_RTUPRUx);
+ DebugP_assert(SystemP_SUCCESS == status);
+ status = PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_TXPRUx);
+ DebugP_assert(SystemP_SUCCESS == status);
+ }
+ status = PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_PRUx);
+ DebugP_assert(SystemP_SUCCESS == status);
+}
+
+int32_t bissc_pruicss_load_run_fw(struct bissc_priv *priv, uint8_t mask)
+{
+ int32_t status = SystemP_FAILURE, size;
+#if (CONFIG_BISSC0_LOAD_SHARE_MODE) /*enable loadshare mode*/
+#if(CONFIG_BISSC0_CHANNEL0)
+ status = PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_RTUPRUx);
+ DebugP_assert(SystemP_SUCCESS == status);
+ size = PRUICSS_writeMemory(gPruIcssXHandle, PRUICSS_IRAM_RTU_PRU(PRUICSS_SLICEx),
+ 0, (uint32_t *) BiSSFirmwareMultiMakeRTU_0,
+ sizeof(BiSSFirmwareMultiMakeRTU_0));
+ DebugP_assert(size);
+ status = PRUICSS_resetCore(gPruIcssXHandle, PRUICSS_RTUPRUx);
+ DebugP_assert(SystemP_SUCCESS == status);
+ status = PRUICSS_enableCore(gPruIcssXHandle, PRUICSS_RTUPRUx);
+ DebugP_assert(SystemP_SUCCESS == status);
+#endif
+#if(CONFIG_BISSC0_CHANNEL1)
+ status=PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_PRUx );
+ DebugP_assert(SystemP_SUCCESS == status);
+ size = PRUICSS_writeMemory(gPruIcssXHandle, PRUICSS_IRAM_PRU(PRUICSS_SLICEx),
+ 0, (uint32_t *) BiSSFirmwareMultiMakePRU_0,
+ sizeof(BiSSFirmwareMultiMakePRU_0));
+ DebugP_assert(size);
+ status = PRUICSS_resetCore(gPruIcssXHandle, PRUICSS_PRUx);
+ DebugP_assert(SystemP_SUCCESS == status);
+ status = PRUICSS_enableCore(gPruIcssXHandle, PRUICSS_PRUx);
+ DebugP_assert(SystemP_SUCCESS == status);
+#endif
+#if(CONFIG_BISSC0_CHANNEL2)
+ status = PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_TXPRUx);
+ DebugP_assert(SystemP_SUCCESS == status);
+ size = PRUICSS_writeMemory(gPruIcssXHandle, PRUICSS_IRAM_TX_PRU(PRUICSS_SLICEx),
+ 0, (uint32_t *) BiSSFirmwareMultiMakeTXPRU_0,
+ sizeof(BiSSFirmwareMultiMakeTXPRU_0));
+ DebugP_assert(size);
+ status = PRUICSS_resetCore(gPruIcssXHandle, PRUICSS_TXPRUx);
+ DebugP_assert(SystemP_SUCCESS == status);
+ status = PRUICSS_enableCore(gPruIcssXHandle, PRUICSS_TXPRUx);
+ DebugP_assert(SystemP_SUCCESS == status);
+#endif
+#else
+ status = PRUICSS_disableCore(gPruIcssXHandle, PRUICSS_PRUx);
+ DebugP_assert(SystemP_SUCCESS == status);
+#if(CONFIG_BISSC0_MODE == BISSC_MODE_MULTI_CHANNEL_SINGLE_PRU)
+ size = PRUICSS_writeMemory(gPruIcssXHandle, PRUICSS_IRAM_PRU(PRUICSS_PRUx),
+ 0, (uint32_t *) BiSSFirmwareMulti_0,
+ sizeof(BiSSFirmwareMulti_0));
+#else
+ size = PRUICSS_writeMemory(gPruIcssXHandle, PRUICSS_IRAM_PRU(PRUICSS_PRUx),
+ 0, (uint32_t *) BiSSFirmware_0,
+ sizeof(BiSSFirmware_0));
+#endif
+ DebugP_assert(size);
+ status = PRUICSS_resetCore(gPruIcssXHandle, PRUICSS_PRUx);
+ DebugP_assert(SystemP_SUCCESS == status);
+ /*Run firmware */
+ status = PRUICSS_enableCore(gPruIcssXHandle, PRUICSS_PRUx);
+ DebugP_assert(SystemP_SUCCESS == status);
+#endif
+ /* check initialization ack from firmware, with a timeout of 5 second */
+ status = bissc_wait_for_fw_initialization(priv, WAIT_5_SECOND, mask);
+ return status;
+}
+
+uint64_t bissc_get_fw_version(void)
+{
+#if (CONFIG_BISSC0_MODE == BISSC_MODE_MULTI_CHANNEL_SINGLE_PRU)
+ return *((unsigned long *)BiSSFirmwareMulti_0 + 2);
+#endif
+#if (CONFIG_BISSC0_CHANNEL0) && (CONFIG_BISSC0_LOAD_SHARE_MODE)
+ return *((unsigned long *)BiSSFirmwareMultiMakeRTU_0 + 2);
+#endif
+#if (CONFIG_BISSC0_CHANNEL1) && (CONFIG_BISSC0_LOAD_SHARE_MODE)
+ return *((unsigned long *)BiSSFirmwareMultiMakePRU_0 + 2);
+#endif
+#if (CONFIG_BISSC0_CHANNEL2) && (CONFIG_BISSC0_LOAD_SHARE_MODE)
+ return *((unsigned long *)BiSSFirmwareMultiMakeTXPRU_0 + 2);
+#endif
+#if (CONFIG_BISSC0_MODE == BISSC_MODE_SINGLE_CHANNEL_SINGLE_PRU)
+ return *((unsigned long *)BiSSFirmware_0 + 2);
+#endif
+}
+
+static int32_t bissc_clock_config(uint32_t frequency, struct bissc_priv *priv)
+{
+ struct bissc_clk_cfg clk_cfg;
+ int32_t status = SystemP_FAILURE;
+ if(bissc_calc_clock(frequency, &clk_cfg) < 0)
+ {
+ return SystemP_FAILURE;
+ }
+ DebugP_logInfo("\r| clock config values - tx_div: %u\trx_div: %u\trx_div_attr: %x\n",
+ clk_cfg.tx_div, clk_cfg.rx_div, clk_cfg.rx_div_attr);
+ bissc_update_max_proc_delay(priv, frequency);
+ bissc_config_endat_mode(priv);
+ bissc_config_clock(priv, &clk_cfg);
+ bissc_config_clr_cfg0(priv);
+ status = bissc_wait_measure_proc_delay(priv, WAIT_5_SECOND);
+ return status;
+}
+
+static void bissc_display_menu(void)
+{
+ DebugP_log("\r\n|------------------------------------------------------------------------------|");
+ DebugP_log("\r\n| Select input parametes |");
+ DebugP_log("\r\n|------------------------------------------------------------------------------|");
+ DebugP_log("\r\n| 1 : Number of position data bits |");
+ DebugP_log("\r\n| 2 : Select clock frequency in MHz(1/2/5/8/10) |");
+ DebugP_log("\r\n| 3 : Encoder send position values |");
+ DebugP_log("\r\n| 4 : Hex equivalent of control command(in hex) |");
+ DebugP_log("\r\n| 5 : Loop over BiSS-C cycles |");
+ DebugP_log("\r\n| 0 : Exit the application |");
+ DebugP_log("\r\n|------------------------------------------------------------------------------|");
+ DebugP_log("\r\n| enter value:\r\n");
+}
+void bissc_get_enc_data_len(struct bissc_priv *priv){
+ int32_t pru_num, totalprus;
+ uint32_t single_turn_len[3] = {0}, multi_turn_len[3] = {0};
+ priv->num_slaves[0] = 0;
+ priv->num_slaves[1] = 0;
+ priv->num_slaves[2] = 0;
+
+ if(priv->load_share)
+ totalprus = priv->totalchannels;
+ else
+ totalprus = 1;
+
+ for(pru_num = 0; pru_num < totalprus; pru_num++){
+ DebugP_log("\r\nPlease enter encoder lengths connected to Ch %d:\n", priv->channel[pru_num]);
+ DebugP_log("\r\nPlease enter 1st encoder single turn length\n");
+ DebugP_scanf("%u\n", &single_turn_len[0]);
+ if(single_turn_len[0]){
+ DebugP_log("\r\nPlease enter 1st encoder multiturn length, 0 if not multiturn\n");
+ DebugP_scanf("%u\n", &multi_turn_len[0]);
+ }
+ DebugP_log("\r\nPlease enter 0 as data length if daisy chain is not used\n");
+ DebugP_log("\r\nPlease enter 2nd encoder single turn length\n");
+ DebugP_scanf("%u\n", &single_turn_len[1]);
+ if(single_turn_len[1]){
+ DebugP_log("\r\nPlease enter 2nd encoder multiturn length, 0 if not multiturn\n");
+ DebugP_scanf("%u\n", &multi_turn_len[1]);
+ }
+ if(single_turn_len[1]){
+ DebugP_log("\r\nPlease enter 3rd encoder single turn length\n");
+ DebugP_scanf("%u\n", &single_turn_len[2]);
+ if(single_turn_len[2]){
+ DebugP_log("\r\nPlease enter 3rd encoder multiturn length, 0 if not multiturn\n");
+ DebugP_scanf("%u\n", &multi_turn_len[2]);
+ }
+ }
+ bissc_update_data_len(priv, single_turn_len, multi_turn_len, pru_num);
+ }
+}
+static int bissc_get_command()
+{
+ uint32_t cmd;
+ DebugP_scanf("%d\n", &cmd);
+ /* Check to make sure that the command issued is correct */
+ if( cmd < 0 || cmd > 5)
+ {
+ DebugP_log("\r\n| WARNING: invalid option try again\n");
+ return SystemP_FAILURE;
+ }
+ return cmd;
+}
+
+void bissc_main(void *args)
+{
+ int32_t i, totalprus, ch_num, ls_ch = 0, pru_num;
+ uint64_t icssgclk;
+ int32_t ch = 0;
+ if(CONFIG_BISSC0_LOAD_SHARE_MODE){
+ loadshare = 1;
+ }
+ /* Open drivers to open the UART driver for console */
+ Drivers_open();
+ Board_driversOpen();
+ /*C16 pin High for Enabling ch0 in booster pack */
+#if (CONFIG_BISSC0_BOOSTER_PACK)
+#if (CONFIG_BISSC0_CHANNEL0)
+ GPIO_setDirMode(ENC0_EN_BASE_ADDR, ENC0_EN_PIN, ENC0_EN_DIR);
+ GPIO_pinWriteHigh(ENC0_EN_BASE_ADDR, ENC0_EN_PIN);
+#endif
+#if (CONFIG_BISSC0_CHANNEL1)
+ GPIO_setDirMode(ENC1_EN_BASE_ADDR, ENC1_EN_PIN, ENC1_EN_DIR);
+ GPIO_pinWriteHigh(ENC1_EN_BASE_ADDR, ENC1_EN_PIN);
+#endif
+#if (CONFIG_BISSC0_CHANNEL2)
+ GPIO_setDirMode(ENC2_EN_BASE_ADDR, ENC2_EN_PIN, ENC2_EN_DIR);
+ GPIO_pinWriteHigh(ENC2_EN_BASE_ADDR, ENC2_EN_PIN);
+#endif
+#endif
+
+ i = bissc_get_fw_version();
+
+ DebugP_log("\n\n");
+ DebugP_log("BiSS-C firmware \t: %x.%x.%x (%s)\n", (i >> 24) & 0x7F,
+ (i >> 16) & 0xFF, i & 0xFFFF, i & (1 << 31) ? "internal" : "release");
+
+ bissc_pruicss_init();
+
+ i = CONFIG_BISSC0_CHANNEL0 & 0;
+
+ i += CONFIG_BISSC0_CHANNEL1;
+
+ i += CONFIG_BISSC0_CHANNEL2<<1;
+
+ if(i < 0 || i > 2)
+ {
+ DebugP_log("\r\nWARNING: invalid channel selected, defaulting to Channel 0\n");
+ i = 0;
+ }
+
+ mask = CONFIG_BISSC0_CHANNEL0<<0 | CONFIG_BISSC0_CHANNEL1<<1 | CONFIG_BISSC0_CHANNEL2<<2;
+
+ totalchannels = (CONFIG_BISSC0_CHANNEL0 + CONFIG_BISSC0_CHANNEL1 + CONFIG_BISSC0_CHANNEL2);
+
+ if(CONFIG_BISSC0_MODE == BISSC_MODE_MULTI_CHANNEL_SINGLE_PRU){
+
+ multichannel = 1;
+ }
+ DebugP_log("\r\n\n");
+
+ priv = bissc_init(gPruIcssXHandle, PRUICSS_PRUx, CONFIG_BISSC0_BAUDRATE);
+ bissc_config_channel(priv, mask, totalchannels);
+ if(loadshare){
+ bissc_config_load_share(priv, mask, loadshare);
+ }
+
+ /* Read the ICSSG configured clock frequency. */
+ if(gPruIcssXHandle->hwAttrs->instance)
+ {
+ SOC_moduleGetClockFrequency(TISCI_DEV_PRU_ICSSG1, TISCI_DEV_PRU_ICSSG1_CORE_CLK, &icssgclk);
+ }
+ else
+ {
+ SOC_moduleGetClockFrequency(TISCI_DEV_PRU_ICSSG0, TISCI_DEV_PRU_ICSSG0_CORE_CLK, &icssgclk);
+ }
+ bissc_set_default_initialization(priv,CONFIG_BISSC0_BAUDRATE, icssgclk);
+ if(CONFIG_BISSC0_MODE == BISSC_MODE_MULTI_CHANNEL_MULTI_PRU){
+ DebugP_log("\r\nBiSS-C Load Share Demo application is running......\n");
+ for(pru_num = 0; pru_num < totalchannels; pru_num++)
+ DebugP_log("\r\nChannel %d is enabled\n", priv->channel[pru_num]);
+ }
+ else if(CONFIG_BISSC0_MODE == BISSC_MODE_MULTI_CHANNEL_SINGLE_PRU){
+ DebugP_log("\r\nBiSS-C Multi channel, Single PRU Demo application is running......\n");
+ for(ch_num = 0; ch_num < totalchannels; ch_num++)
+ DebugP_log("\r\nChannel %d is enabled\n", priv->channel[ch_num]);
+ }
+ else{
+ DebugP_log("\r\nBiSS-C Single channel, Single PRU Demo application is running......\n");
+ DebugP_log("\r\nChannel %d is enabled\n", priv->channel[0]);
+ }
+ bissc_get_enc_data_len(priv);
+ i = bissc_pruicss_load_run_fw(priv, mask);
+ if(i < 0)
+ {
+ DebugP_log("\r\nERROR: BiSS-C initialization failed \n");
+ DebugP_log("\r\ncheck whether encoder is connected and ensure proper connections\n");
+ DebugP_log("\r\nexit %s due to failed firmware initialization\n", __func__);
+ goto deinit;
+ }
+
+ if(!loadshare && multichannel){
+ if(priv->pruicss_xchg->proc_delay[priv->channel[0]] == priv->pruicss_xchg->proc_delay[priv->channel[1]]){
+ if(priv->totalchannels > 2){
+ if(priv->pruicss_xchg->proc_delay[priv->channel[1]] != priv->pruicss_xchg->proc_delay[priv->channel[2]])
+ {
+ DebugP_log("\r\n Encoders connected accross channels have different processing delays, multi channel configuration is not supported\n");
+ goto deinit;
+ }
+ }
+ }
+ else{
+ DebugP_log("\r\n Encoders connected accross channels have different processing delays, multi channel configuration is not supported\n");
+ goto deinit;
+ }
+ }
+
+ DebugP_log("\r\nBiSS-C encoder/encoders detected and running at frequency %dMHz\n", CONFIG_BISSC0_BAUDRATE);
+ for( ch_num = 0; ch_num < totalchannels; ch_num++){
+ DebugP_log("\r\nProcessing Delay for Ch %d : %u\n",priv->channel[ch_num], priv->pruicss_xchg->proc_delay[priv->channel[ch_num]]);
+ }
+
+ while(1)
+ {
+ int32_t cmd, ret;
+ uint32_t freq, ctrl_cmd[3]={0};
+ uint32_t loop_cnt;
+ bissc_display_menu();
+ cmd = bissc_get_command();
+ if(cmd < 0)
+ {
+ continue;
+ }
+ else if(cmd == 0)
+ {
+ DebugP_log("\r\tGood bye!\n");
+ break;
+ }
+ else if(cmd == 1)
+ {
+ bissc_get_enc_data_len(priv);
+ }
+ else if(cmd == 2)
+ {
+ DebugP_log("\r\nPlease enter frequency in MHz:\n");
+ DebugP_scanf("%u\n", &freq);
+ if(!((freq == 1) || (freq == 2) || (freq == 5) || (freq == 8) || (freq == 10)))
+ {
+ DebugP_log("\r\n CLK divisors will not be possible. Please provide valid freq: 1/2/5/8/10 \n");
+ continue;
+ }
+ ret = bissc_clock_config(freq, priv);
+ if(ret < 0)
+ {
+ DebugP_log("\r\n ERROR: Processing time measurement failed \n");
+ DebugP_log("\r\n check whether encoder is connected and ensure proper connections \n");
+ DebugP_log("\r\n Good bye!\n");
+ break;
+ }
+ ClockP_sleep(2);
+ }
+ else if(cmd == 3)
+ {
+ ret = bissc_get_pos_res(priv);
+ if(ret < 0)
+ {
+ DebugP_log("\r\n ERROR: Position data measurement failed \n");
+ }
+ for(ch_num = 0; ch_num < priv->totalchannels; ch_num++)
+ {
+ ch = priv->channel[ch_num];
+ if(loadshare)
+ ls_ch = ch;
+ else
+ ls_ch = 0;
+ DebugP_log("\r\n Channel %d:\n", ch);
+ if(priv->multi_turn_len[ls_ch][0]){
+ DebugP_log("\r\n Encoder-1 Multiturn rev: %u, Angle: %.12f, crc: %x, otf crc: %x, e_w: %x\n", priv->enc_pos_data[ch].num_of_turns[0],
+ priv->enc_pos_data[ch].angle[0], priv->enc_pos_data[ch].rcv_crc[0], priv->enc_pos_data[ch].otf_crc[0], priv->enc_pos_data[ch].ew[0]);
+ }
+ else{
+ DebugP_log("\r\n Encoder-1 Singleturn Angle: %.12f, crc: %x, otf crc: %x, e_w: %x\n", priv->enc_pos_data[ch].angle[0], priv->enc_pos_data[ch].rcv_crc[0],
+ priv->enc_pos_data[ch].otf_crc[0], priv->enc_pos_data[ch].ew[0]);
+ }
+ DebugP_log("\r\n CRC Status: %s, crc error count: %u\n", (priv->enc_pos_data[ch].rcv_crc[0] == priv->enc_pos_data[ch].otf_crc[0]) ? "success" : "failure" ,
+ priv->pd_crc_err_cnt[ch][0]);
+
+ if(priv->data_len[ls_ch][1]){
+ if(priv->multi_turn_len[1]){
+ DebugP_log("\r\n Encoder-2 Multiturn rev: %u, Angle: %.12f, crc: %x, otf crc: %x, e_w: %x\n", priv->enc_pos_data[ch].num_of_turns[1],
+ priv->enc_pos_data[ch].angle[1], priv->enc_pos_data[ch].rcv_crc[1], priv->enc_pos_data[ch].otf_crc[1], priv->enc_pos_data[ch].ew[1]);
+ }
+ else{
+ DebugP_log("\r\n Encoder-2 Singleturn Angle: %.12f, crc: %x, otf crc: %x, e_w: %x\n", priv->enc_pos_data[ch].angle[1], priv->enc_pos_data[ch].rcv_crc[1],
+ priv->enc_pos_data[ch].otf_crc[1], priv->enc_pos_data[ch].ew[1]);
+ }
+ DebugP_log("\r\n CRC Status: %s, crc error count: %u\n", (priv->enc_pos_data[ch].rcv_crc[1] == priv->enc_pos_data[ch].otf_crc[1]) ? "success" : "failure" ,
+ priv->pd_crc_err_cnt[ch][1]);
+
+ if(priv->data_len[ls_ch][2]){
+ if(priv->multi_turn_len[2]){
+ DebugP_log("\r\n Encoder-3 Multiturn rev: %u, Angle: %.12f, crc: %x, otf crc: %x, e_w: %x\n", priv->enc_pos_data[ch].num_of_turns[2],
+ priv->enc_pos_data[ch].angle[2], priv->enc_pos_data[ch].rcv_crc[2], priv->enc_pos_data[ch].otf_crc[2], priv->enc_pos_data[ch].ew[2]);
+ }
+ else{
+ DebugP_log("\r\n Encoder-3 Singleturn Angle: %.12f, crc: %x, otf crc: %x, e_w: %x\n", priv->enc_pos_data[ch].angle[2], priv->enc_pos_data[ch].rcv_crc[2],
+ priv->enc_pos_data[ch].otf_crc[2], priv->enc_pos_data[ch].ew[2]);
+ }
+ DebugP_log("\r\n CRC Status: %s, crc error count: %u\n", (priv->enc_pos_data[ch].rcv_crc[2] == priv->enc_pos_data[ch].otf_crc[2]) ? "success" : "failure" ,
+ priv->pd_crc_err_cnt[ch][2]);
+ }
+ }
+ }
+ }
+ else if(cmd == 4)
+ {
+ DebugP_log("\r\nPlease enter control command in Hex:\n");
+ if(loadshare){
+ totalprus = priv->totalchannels;
+ for(pru_num = 0; pru_num < totalprus; pru_num++){
+ ls_ch = priv->channel[pru_num];
+ DebugP_log("\r\nCh %d: ",ls_ch);
+ DebugP_scanf("%x\n", &ctrl_cmd[ls_ch]);
+ }
+ }
+ else{
+ DebugP_scanf("%x\n", &ctrl_cmd[0]);
+ }
+ ret = bissc_set_ctrl_cmd_and_process(priv, ctrl_cmd);
+ if(ret < 0)
+ {
+ DebugP_log("\r\n ERROR: Control communication failed \n");
+ }
+ for(ch_num = 0; ch_num < priv->totalchannels; ch_num++)
+ {
+ ch = priv->channel[ch_num];
+ DebugP_log("\r\n Channel %d:\n", ch);
+ DebugP_log("\r\n Control communication result: %x, crc: %x, otf crc: %x, status: %s\n",priv->enc_ctrl_data[ch].cmd_result,
+ priv->enc_ctrl_data[ch].cmd_rcv_crc, priv->enc_ctrl_data[ch].cmd_otf_crc,
+ (priv->enc_ctrl_data[ch].cmd_rcv_crc == priv->enc_ctrl_data[ch].cmd_otf_crc) ? "success" : "failure");
+
+ DebugP_log("\r\n CTRL CRC error count: %u\n", priv->ctrl_crc_err_cnt[ch]);
+ }
+ }
+ else if(cmd == 5)
+ {
+ DebugP_log("\r\nEnter number of BiSS-C cycles:\n");
+ DebugP_scanf("%u\n", &loop_cnt);
+ if(loop_cnt)
+ {
+ do
+ {
+ ret = bissc_get_pos_res(priv);
+ if(ret < 0)
+ {
+ DebugP_log("\r\n ERROR: Position data measurement for first encoder failed \n");
+ }
+ for( ch_num = 0; ch_num < totalchannels; ch_num++ ){
+ ch = priv->channel[ch_num];
+ if(loadshare)
+ ls_ch = ch;
+ else
+ ls_ch = 0;
+ if(multichannel || loadshare)
+ DebugP_log("%s", (ch_num != (totalchannels-1))?"\r":" & ");
+ else
+ DebugP_log("\r");
+ if(priv->data_len[ls_ch][1])
+ {
+ if(priv->data_len[ls_ch][2])
+ {
+ if(priv->multi_turn_len[ls_ch][2]){
+ DebugP_log("Ch:%d - Enc3: MT rev:%u, Angle:%.12f, Enc2: MT rev:%u, Angle:%.12f, Enc1: MT rev:%u, Angle:%.12f, crc error count enc3:%u, crc error count enc2:%u, crc error count enc_1:%u ",ch, priv->enc_pos_data[ch].num_of_turns[2], priv->enc_pos_data[ch].angle[2],priv->enc_pos_data[ch].num_of_turns[1], priv->enc_pos_data[ch].angle[1],
+ priv->enc_pos_data[ch].num_of_turns[0], priv->enc_pos_data[ch].angle[0], priv->pd_crc_err_cnt[ch][2], priv->pd_crc_err_cnt[ch][1], priv->pd_crc_err_cnt[ch][0]);
+ }
+ else{
+ DebugP_log("Ch:%d - Enc3: Angle:%.12f, Enc2: Angle:%.12f, Enc1: Angle:%.12f, crc error count enc3:%u, crc error count enc2:%u, crc error count enc1:%u ",ch, priv->enc_pos_data[ch].angle[2], priv->enc_pos_data[ch].angle[1],
+ priv->enc_pos_data[ch].angle[0], priv->pd_crc_err_cnt[ch][2], priv->pd_crc_err_cnt[ch][1], priv->pd_crc_err_cnt[ch][0]);
+ }
+ }
+ else{
+ if(priv->multi_turn_len[ls_ch][1]){
+ DebugP_log("Ch:%d - Enc2: MT rev:%u, Angle:%.12f, Enc1: MT rev:%u, Angle:%.12f, crc error count enc2:%u, crc error count enc1:%u ",ch,priv->enc_pos_data[ch].num_of_turns[1], priv->enc_pos_data[ch].angle[1],
+ priv->enc_pos_data[ch].num_of_turns[0], priv->enc_pos_data[ch].angle[0],priv->pd_crc_err_cnt[ch][1], priv->pd_crc_err_cnt[ch][0]);
+ }
+ else{
+ DebugP_log("Ch:%d - Enc2: Angle:%.12f, Enc1: Angle:%.12f, crc error count enc2:%u, crc error count enc1:%u ",ch, priv->enc_pos_data[ch].angle[1], priv->enc_pos_data[ch].angle[0], priv->pd_crc_err_cnt[ch][1],
+ priv->pd_crc_err_cnt[ch][0]);
+ }
+ }
+ }
+ else{
+ if(priv->multi_turn_len[ls_ch][0]){
+ DebugP_log("Ch:%d - Enc1: MT rev:%u, Angle:%.12f, crc error count enc1:%u ",ch, priv->enc_pos_data[ch].num_of_turns[0], priv->enc_pos_data[ch].angle[0],
+ priv->pd_crc_err_cnt[ch][0]);
+ }
+ else{
+ DebugP_log("Ch:%d - Enc1: Angle:%.12f, crc error count enc1:%u ",ch, priv->enc_pos_data[ch].angle[0],
+ priv->pd_crc_err_cnt[ch][0]);
+ }
+ }
+ }
+ loop_cnt--;
+ }while(loop_cnt);
+ }
+ else{
+ DebugP_log("Please enter non-zero value\n");
+ }
+ }
+ }
+deinit:
+
+ Board_driversClose();
+ Drivers_close();
+ return;
+}
+
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/.project/project.js b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/.project/project.js
new file mode 100644
index 0000000..f6c2d16
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/.project/project.js
@@ -0,0 +1,14 @@
+function getComponentProperty(device)
+{
+ return require(`./project_${device}`).getComponentProperty();
+};
+
+function getComponentBuildProperty(buildOption)
+{
+ return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption);
+};
+
+module.exports = {
+ getComponentProperty,
+ getComponentBuildProperty,
+};
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/.project/project_am243x.js b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/.project/project_am243x.js
new file mode 100644
index 0000000..652da19
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/.project/project_am243x.js
@@ -0,0 +1,123 @@
+let path = require('path');
+
+let device = "am243x";
+
+const files = {
+ common: [
+ "bissc_diagnostic.c",
+ "main.c",
+ ],
+};
+
+/* Relative to where the makefile will be generated
+ * Typically at ///
+ */
+const filedirs = {
+ common: [
+ "..", /* core_os_combo base */
+ "../../../..", /* Example base */
+ ],
+};
+
+const libdirs_freertos = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib",
+ ],
+};
+
+const includes_freertos_r5f = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f",
+ ],
+};
+
+const libs_freertos_r5f = {
+ common: [
+ "freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "board.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "motorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+ ],
+};
+
+const defines_r5f = {
+ common: [
+ "SOC_AM243X",
+ ],
+};
+
+const lnkfiles = {
+ common: [
+ "linker.cmd",
+ ]
+};
+
+const syscfgfile = "../example.syscfg";
+
+const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_BISSC";
+
+const templates_freertos_r5f =
+[
+ {
+ input: ".project/templates/am243x/common/linker_r5f.cmd.xdt",
+ output: "linker.cmd",
+ },
+ {
+ input: ".project/templates/am243x/freertos/main_freertos.c.xdt",
+ output: "../main.c",
+ options: {
+ entryFunction: "bissc_main",
+ taskPri: 5,
+ },
+ }
+];
+
+const buildOptionCombos = [
+ { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-lp", os: "freertos"},
+];
+
+function getComponentProperty() {
+ let property = {};
+
+ property.dirPath = path.resolve(__dirname, "..");
+ property.type = "executable";
+ property.name = "bissc_diagnostic_multi_channel_load_share";
+ property.isInternal = false;
+ property.buildOptionCombos = buildOptionCombos;
+ property.isSkipTopLevelBuild = false;
+
+ return property;
+}
+
+function getComponentBuildProperty(buildOption) {
+ let build_property = {};
+
+ build_property.files = files;
+ build_property.filedirs = filedirs;
+ build_property.lnkfiles = lnkfiles;
+ build_property.syscfgfile = syscfgfile;
+ build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
+
+ if(buildOption.cpu.match(/r5f*/)) {
+ if(buildOption.os.match(/freertos*/) )
+ {
+ build_property.includes = includes_freertos_r5f;
+ build_property.libdirs = libdirs_freertos;
+ build_property.libs = libs_freertos_r5f;
+ build_property.templates = templates_freertos_r5f;
+ build_property.defines = defines_r5f;
+ }
+ }
+
+ return build_property;
+}
+
+module.exports = {
+ getComponentProperty,
+ getComponentBuildProperty,
+};
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/.project/project_am64x.js b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/.project/project_am64x.js
new file mode 100644
index 0000000..5ced694
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/.project/project_am64x.js
@@ -0,0 +1,123 @@
+let path = require('path');
+
+let device = "am64x";
+
+const files = {
+ common: [
+ "bissc_diagnostic.c",
+ "main.c",
+ ],
+};
+
+/* Relative to where the makefile will be generated
+ * Typically at ///
+ */
+const filedirs = {
+ common: [
+ "..", /* core_os_combo base */
+ "../../../..", /* Example base */
+ ],
+};
+
+const libdirs_freertos = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib",
+ ],
+};
+
+const includes_freertos_r5f = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am64x/r5f",
+ ],
+};
+
+const libs_freertos_r5f = {
+ common: [
+ "freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "board.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "motorcontrol_bissc.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
+ ],
+};
+
+const defines_r5f = {
+ common: [
+ "SOC_AM64X",
+ ],
+};
+
+const lnkfiles = {
+ common: [
+ "linker.cmd",
+ ]
+};
+
+const syscfgfile = "../example.syscfg";
+
+const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_BISSC";
+
+const templates_freertos_r5f =
+[
+ {
+ input: ".project/templates/am64x/common/linker_r5f.cmd.xdt",
+ output: "linker.cmd",
+ },
+ {
+ input: ".project/templates/am64x/freertos/main_freertos.c.xdt",
+ output: "../main.c",
+ options: {
+ entryFunction: "bissc_main",
+ taskPri: 5,
+ },
+ }
+];
+
+const buildOptionCombos = [
+ { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"},
+];
+
+function getComponentProperty() {
+ let property = {};
+
+ property.dirPath = path.resolve(__dirname, "..");
+ property.type = "executable";
+ property.name = "bissc_diagnostic_multi_channel_load_share";
+ property.isInternal = false;
+ property.buildOptionCombos = buildOptionCombos;
+ property.isSkipTopLevelBuild = false;
+
+ return property;
+}
+
+function getComponentBuildProperty(buildOption) {
+ let build_property = {};
+
+ build_property.files = files;
+ build_property.filedirs = filedirs;
+ build_property.lnkfiles = lnkfiles;
+ build_property.syscfgfile = syscfgfile;
+ build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
+
+ if(buildOption.cpu.match(/r5f*/)) {
+ if(buildOption.os.match(/freertos*/) )
+ {
+ build_property.includes = includes_freertos_r5f;
+ build_property.libdirs = libdirs_freertos;
+ build_property.libs = libs_freertos_r5f;
+ build_property.templates = templates_freertos_r5f;
+ build_property.defines = defines_r5f;
+ }
+ }
+
+ return build_property;
+}
+
+module.exports = {
+ getComponentProperty,
+ getComponentBuildProperty,
+};
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/example.syscfg b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/example.syscfg
new file mode 100644
index 0000000..a979eca
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/example.syscfg
@@ -0,0 +1,102 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK_AM243X@09.01.00"
+ * @versions {"tool":"1.18.0+3266"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false);
+const i2c1 = i2c.addInstance();
+const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
+const pruicss1 = pruicss.addInstance();
+const debug_log = scripting.addModule("/kernel/dpl/debug_log");
+const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
+const mpu_armv71 = mpu_armv7.addInstance();
+const mpu_armv72 = mpu_armv7.addInstance();
+const mpu_armv73 = mpu_armv7.addInstance();
+const mpu_armv74 = mpu_armv7.addInstance();
+const mpu_armv75 = mpu_armv7.addInstance();
+const mpu_armv76 = mpu_armv7.addInstance();
+const timer = scripting.addModule("/kernel/dpl/timer", {}, false);
+const timer1 = timer.addInstance();
+const endat = scripting.addModule("/position_sense/endat", {}, false);
+const endat1 = endat.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+i2c1.$name = "CONFIG_I2C0";
+i2c1.I2C.$assign = "I2C1";
+
+debug_log.enableCssLog = false;
+debug_log.enableUartLog = true;
+debug_log.uartLog.$name = "CONFIG_UART0";
+
+mpu_armv71.$name = "CONFIG_MPU_REGION0";
+mpu_armv71.size = 31;
+mpu_armv71.attributes = "Device";
+mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv72.$name = "CONFIG_MPU_REGION1";
+mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv72.size = 15;
+
+mpu_armv73.$name = "CONFIG_MPU_REGION2";
+mpu_armv73.size = 15;
+mpu_armv73.baseAddr = 0x41010000;
+mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv74.$name = "CONFIG_MPU_REGION3";
+mpu_armv74.size = 21;
+mpu_armv74.baseAddr = 0x70000000;
+mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv75.$name = "CONFIG_MPU_REGION4";
+mpu_armv75.size = 28;
+mpu_armv75.baseAddr = 0x60000000;
+mpu_armv75.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv76.$name = "CONFIG_MPU_REGION5";
+mpu_armv76.size = 31;
+mpu_armv76.baseAddr = 0x80000000;
+
+timer1.$name = "CONFIG_TIMER0";
+timer1.timerCallback = "endat_position_loop";
+timer1.intrPriority = 0;
+timer1.TIMER.$assign = "DMTIMER0";
+
+endat1.$name = "CONFIG_ENDAT0";
+endat1.Channel_1 = true;
+endat1.Channel_2 = true;
+endat1.Multi_Channel_Load_Share = true;
+endat1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1";
+
+pruicss1.$name = "CONFIG_PRU_ICSS0";
+endat1.pru = pruicss1;
+pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
+
+/**
+ * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
+ * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to
+ * re-solve from scratch.
+ */
+i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL";
+i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA";
+debug_log.uartLog.UART.$suggestSolution = "USART0";
+debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD";
+debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD";
+endat1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2";
+endat1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1";
+endat1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0";
+endat1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13";
+endat1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5";
+endat1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4";
+endat1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3";
+endat1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14";
+endat1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8";
+endat1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12";
+endat1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6";
+endat1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11";
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/main.c b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/main.c
new file mode 100644
index 0000000..de5e3bb
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/main.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include "ti_drivers_config.h"
+#include "ti_board_config.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define MAIN_TASK_PRI (5)
+
+#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE))
+StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
+
+StaticTask_t gMainTaskObj;
+TaskHandle_t gMainTask;
+
+void bissc_main(void *args);
+
+void freertos_main(void *args)
+{
+ bissc_main(NULL);
+
+ vTaskDelete(NULL);
+}
+
+
+int main(void)
+{
+ /* init SOC specific modules */
+ System_init();
+ Board_init();
+
+ /* This task is created at highest priority, it should create more tasks and then delete itself */
+ gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */
+ "freertos_main", /* Text name for the task. This is to facilitate debugging only. */
+ MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
+ NULL, /* We are not using the task parameter. */
+ MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
+ gMainTaskStack, /* pointer to stack base */
+ &gMainTaskObj ); /* pointer to statically allocated task object memory */
+ configASSERT(gMainTask != NULL);
+
+ /* Start the scheduler to start the tasks executing. */
+ vTaskStartScheduler();
+
+ /* The following line should never be reached because vTaskStartScheduler()
+ will only return if there was not enough FreeRTOS heap memory available to
+ create the Idle and (if configured) Timer tasks. Heap management, and
+ techniques for trapping heap exhaustion, are described in the book text. */
+ DebugP_assertNoLog(0);
+
+ return 0;
+}
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec
new file mode 100644
index 0000000..16d1992
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@@ -0,0 +1,114 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
new file mode 100644
index 0000000..69640f4
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -0,0 +1,148 @@
+
+/* This is the stack that is used by code running within main()
+ * In case of NORTOS,
+ * - This means all the code outside of ISR uses this stack
+ * In case of FreeRTOS
+ * - This means all the code until vTaskStartScheduler() is called in main()
+ * uses this stack.
+ * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
+ */
+--stack_size=16384
+/* This is the heap size for malloc() API in NORTOS and FreeRTOS
+ * This is also the heap used by pvPortMalloc in FreeRTOS
+ */
+--heap_size=32768
+-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
+
+/* This is the size of stack when R5 is in IRQ mode
+ * In NORTOS,
+ * - Here interrupt nesting is enabled
+ * - This is the stack used by ISRs registered as type IRQ
+ * In FreeRTOS,
+ * - Here interrupt nesting is disabled
+ * - This is stack that is used initally when a IRQ is received
+ * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
+ * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
+ */
+__IRQ_STACK_SIZE = 256;
+/* This is the size of stack when R5 is in IRQ mode
+ * - In both NORTOS and FreeRTOS nesting is disabled for FIQ
+ */
+__FIQ_STACK_SIZE = 256;
+__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
+__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */
+__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */
+
+SECTIONS
+{
+ /* This has the R5F entry point and vector table, this MUST be at 0x0 */
+ .vectors:{} palign(8) > R5F_VECS
+
+ /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
+ * i.e this cannot be placed in DDR
+ */
+ GROUP {
+ .text.hwi: palign(8)
+ .text.cache: palign(8)
+ .text.mpu: palign(8)
+ .text.boot: palign(8)
+ .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
+ } > MSRAM
+
+ /* This is rest of code. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .text: {} palign(8) /* This is where code resides */
+ .rodata: {} palign(8) /* This is where const's go */
+ } > MSRAM
+
+ /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .data: {} palign(8) /* This is where initialized globals and static go */
+ } > MSRAM
+
+ /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .bss: {} palign(8) /* This is where uninitialized globals go */
+ RUN_START(__BSS_START)
+ RUN_END(__BSS_END)
+ .sysmem: {} palign(8) /* This is where the malloc heap goes */
+ .stack: {} palign(8) /* This is where the main() stack goes */
+ } > MSRAM
+
+ /* This is where the stacks for different R5F modes go */
+ GROUP {
+ .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+ .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
+ RUN_START(__UNDEFINED_STACK_START)
+ RUN_END(__UNDEFINED_STACK_END)
+ } > MSRAM
+
+ /* Sections needed for C++ projects */
+ GROUP {
+ .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
+ .init_array: {} palign(8) /* Contains function pointers called before main */
+ .fini_array: {} palign(8) /* Contains function pointers called after main */
+ } > MSRAM
+
+ /* General purpose user shared memory, used in some examples */
+ .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
+ /* this is used when Debug log's to shared memory are enabled, else this is not used */
+ .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
+ /* this is used only when IPC RPMessage is enabled, else this is not used */
+ .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
+ /* General purpose non cacheable memory, used in some examples */
+ .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
+}
+
+/*
+NOTE: Below memory is reserved for DMSC usage
+ - During Boot till security handoff is complete
+ 0x701E0000 - 0x701FFFFF (128KB)
+ - After "Security Handoff" is complete (i.e at run time)
+ 0x701F4000 - 0x701FFFFF (48KB)
+
+ Security handoff is complete when this message is sent to the DMSC,
+ TISCI_MSG_SEC_HANDOVER
+
+ This should be sent once all cores are loaded and all application
+ specific firewall calls are setup.
+*/
+
+MEMORY
+{
+ R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
+ R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
+ R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+
+ /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
+ NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
+
+ /* when using multi-core application's i.e more than one R5F/M4F active, make sure
+ * this memory does not overlap with other R5F's
+ */
+ MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000
+
+ /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
+ * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
+ */
+ FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000
+
+ /* shared memory segments */
+ /* On R5F,
+ * - make sure there is a MPU entry which maps below regions as non-cache
+ */
+ USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180
+ LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180
+ RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
+}
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile
new file mode 100644
index 0000000..0d2e157
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile
@@ -0,0 +1,308 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak
+
+CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
+
+CC=$(CG_TOOL_ROOT)/bin/tiarmclang
+LNK=$(CG_TOOL_ROOT)/bin/tiarmclang
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+ PYTHON=python
+else
+ PYTHON=python3
+endif
+
+PROFILE?=release
+ConfigName:=$(PROFILE)
+
+OUTNAME:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).out
+
+BOOTIMAGE_PATH=$(abspath .)
+BOOTIMAGE_NAME:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).appimage
+BOOTIMAGE_NAME_XIP:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).appimage.signed
+BOOTIMAGE_RPRC_NAME:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).rprc_tmp
+BOOTIMAGE_NAME_HS:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).appimage.hs
+BOOTIMAGE_NAME_HS_FS:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).appimage.hs_fs
+TARGETS := $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+ TARGETS += $(BOOTIMAGE_NAME_HS)
+endif
+
+FILES_common := \
+ bissc_diagnostic.c \
+ main.c \
+ ti_drivers_config.c \
+ ti_drivers_open_close.c \
+ ti_board_config.c \
+ ti_board_open_close.c \
+ ti_dpl_config.c \
+ ti_pinmux_config.c \
+ ti_power_clock_config.c \
+
+FILES_PATH_common = \
+ .. \
+ ../../../.. \
+ generated \
+
+INCLUDES_common := \
+ -I${CG_TOOL_ROOT}/include/c \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source \
+ -I${MOTOR_CONTROL_SDK_PATH}/source \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \
+ -Igenerated \
+
+DEFINES_common := \
+ -DSOC_AM243X \
+ -DSOC_AM243X \
+
+CFLAGS_common := \
+ -mcpu=cortex-r5 \
+ -mfloat-abi=hard \
+ -mfpu=vfpv3-d16 \
+ -mthumb \
+ -Wall \
+ -Werror \
+ -g \
+ -Wno-gnu-variable-sized-type-not-at-end \
+ -Wno-unused-function \
+
+CFLAGS_cpp_common := \
+ -Wno-c99-designator \
+ -Wno-extern-c-compat \
+ -Wno-c++11-narrowing \
+ -Wno-reorder-init-list \
+ -Wno-deprecated-register \
+ -Wno-writable-strings \
+ -Wno-enum-compare \
+ -Wno-reserved-user-defined-literal \
+ -Wno-unused-const-variable \
+ -x c++ \
+
+CFLAGS_debug := \
+ -D_DEBUG_=1 \
+
+CFLAGS_release := \
+ -Os \
+
+LNK_FILES_common = \
+ linker.cmd \
+
+LIBS_PATH_common = \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib \
+ -Wl,-i${CG_TOOL_ROOT}/lib \
+
+LIBS_common = \
+ -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -lmotorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -llibc.a \
+ -llibsysbm.a \
+
+LFLAGS_common = \
+ -Wl,--diag_suppress=10063 \
+ -Wl,--ram_model \
+ -Wl,--reread_libs \
+
+
+LIBS_NAME = \
+ freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ motorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ libc.a \
+ libsysbm.a \
+
+LIBS_PATH_NAME = \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib \
+ ${CG_TOOL_ROOT}/lib \
+
+FILES := $(FILES_common) $(FILES_$(PROFILE))
+ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
+FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
+CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
+INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
+LIBS := $(LIBS_common) $(LIBS_$(PROFILE))
+LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE))
+LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE))
+LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE))
+LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE))
+
+OBJDIR := obj/$(PROFILE)/
+OBJS := $(FILES:%.c=%.obj)
+OBJS += $(ASMFILES:%.S=%.obj)
+DEPS := $(FILES:%.c=%.d)
+
+vpath %.obj $(OBJDIR)
+vpath %.c $(FILES_PATH)
+vpath %.S $(FILES_PATH)
+vpath %.lib $(LIBS_PATH_NAME)
+vpath %.a $(LIBS_PATH_NAME)
+
+$(OBJDIR)/%.obj %.obj: %.c
+ @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $<
+ $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.S
+ @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $<
+ $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
+
+all: $(TARGETS)
+
+SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h
+SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h
+SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h
+SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c
+SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h
+SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h
+
+$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME)
+ @echo .
+ @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ...
+ $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES)
+ @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
+ @echo .
+
+clean:
+ @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
+ $(RMDIR) $(OBJDIR)
+ $(RM) $(OUTNAME)
+ $(RM) $(BOOTIMAGE_NAME)
+ $(RM) $(BOOTIMAGE_NAME_XIP)
+ $(RM) $(BOOTIMAGE_NAME_SIGNED)
+ $(RM) $(BOOTIMAGE_NAME_HS)
+ $(RM) $(BOOTIMAGE_NAME_HS_FS)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+ $(RMDIR) generated/
+
+scrub:
+ @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang bissc_diagnostic_multi_channel_load_share ...
+ $(RMDIR) obj
+ifeq ($(OS),Windows_NT)
+ $(RM) \*.out
+ $(RM) \*.map
+ $(RM) \*.appimage*
+ $(RM) \*.rprc*
+ $(RM) \*.tiimage*
+ $(RM) \*.bin
+else
+ $(RM) *.out
+ $(RM) *.map
+ $(RM) *.appimage*
+ $(RM) *.rprc*
+ $(RM) *.tiimage*
+ $(RM) *.bin
+endif
+ $(RMDIR) generated
+
+$(OBJS): | $(OBJDIR)
+
+$(OBJDIR):
+ $(MKDIR) $@
+
+
+.NOTPARALLEL:
+
+.INTERMEDIATE: syscfg
+$(SYSCFG_GEN_FILES): syscfg
+
+syscfg: ../example.syscfg
+ @echo Generating SysConfig files ...
+ $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg
+
+syscfg-gui:
+ $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALV_beta --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+ BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+ BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+ $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+ $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+$(BOOTIMAGE_NAME): $(OUTNAME)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
+ifneq ($(OS),Windows_NT)
+ $(CHMOD) a+x $(XIPGEN_CMD)
+endif
+ $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
+ $(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!!
+ @echo .
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+ @echo .
+
+$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+ @echo Boot image signing: Encryption is disabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+else
+ @echo Boot image signing: Encryption is enabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
+ $(RM) $(BOOTIMAGE_NAME)-enc
+endif
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
+ @echo .
+endif
+-include $(addprefix $(OBJDIR)/, $(DEPS))
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
new file mode 100644
index 0000000..8666cfd
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@@ -0,0 +1,106 @@
+#
+# Auto generated makefile
+#
+
+# Below variables need to be defined outside this file or via command line
+# - MOTOR_CONTROL_SDK_PATH
+# - PROFILE
+# - CG_TOOL_ROOT
+# - OUTNAME
+# - CCS_INSTALL_DIR
+# - CCS_IDE_MODE
+
+CCS_PATH=$(CCS_INSTALL_DIR)
+include ${MOTOR_CONTROL_SDK_PATH}/imports.mak
+include ${MOTOR_CONTROL_SDK_PATH}/devconfig/devconfig.mak
+
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+ PYTHON=python
+else
+ PYTHON=python3
+endif
+
+OUTFILE=$(PROFILE)/$(OUTNAME).out
+BOOTIMAGE_PATH=$(abspath ${PROFILE})
+BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
+BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
+BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+ BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+ BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+ $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+ $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+all:
+ifeq ($(CCS_IDE_MODE),cloud)
+# No post build steps
+else
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ...
+ $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
+ $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
+ifeq ($(DEVICE_TYPE),HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+ @echo Boot image signing: Encryption is disabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
+else
+ @echo Boot image signing: Encryption is enabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
+ $(RM) $(BOOTIMAGE_NAME)-enc
+endif
+endif
+ $(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
+ @echo .
+ifeq ($(DEVICE_TYPE),HS)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
+ @echo .
+else
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+ @echo .
+endif
+endif
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
new file mode 100644
index 0000000..f640159
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
@@ -0,0 +1,20 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=bissc_diagnostic_multi_channel_load_share_am243x-evm_r5fss0-0_freertos_ti-arm-clang
+
+all:
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+ $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
new file mode 100644
index 0000000..472ab38
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
@@ -0,0 +1,8 @@
+/*
+ * ======== syscfg_c.rov.xs ========
+ * This file contains the information needed by the Runtime Object
+ * View (ROV) tool.
+ */
+var crovFiles = [
+ "kernel/freertos/rov/FreeRTOS.rov.js",
+];
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/example.syscfg b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/example.syscfg
new file mode 100644
index 0000000..879ae4d
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/example.syscfg
@@ -0,0 +1,126 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM243x_ALX_beta" --package "ALX" --part "ALX" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK@09.01.00"
+ * @versions {"tool":"1.18.0+3266"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false);
+const gpio1 = gpio.addInstance();
+const gpio2 = gpio.addInstance();
+const gpio3 = gpio.addInstance();
+const gpio4 = gpio.addInstance();
+const gpio5 = gpio.addInstance();
+const gpio6 = gpio.addInstance();
+const debug_log = scripting.addModule("/kernel/dpl/debug_log");
+const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
+const mpu_armv71 = mpu_armv7.addInstance();
+const mpu_armv72 = mpu_armv7.addInstance();
+const mpu_armv73 = mpu_armv7.addInstance();
+const mpu_armv74 = mpu_armv7.addInstance();
+const mpu_armv75 = mpu_armv7.addInstance();
+const bissc = scripting.addModule("/position_sense/bissc", {}, false);
+const bissc1 = bissc.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+debug_log.enableUartLog = true;
+debug_log.enableCssLog = false;
+debug_log.uartLog.$name = "CONFIG_UART_CONSOLE";
+debug_log.uartLog.UART.$assign = "USART0";
+
+mpu_armv71.$name = "CONFIG_MPU_REGION0";
+mpu_armv71.size = 31;
+mpu_armv71.attributes = "Device";
+mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv71.allowExecute = false;
+
+mpu_armv72.$name = "CONFIG_MPU_REGION1";
+mpu_armv72.size = 15;
+mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv73.$name = "CONFIG_MPU_REGION2";
+mpu_armv73.baseAddr = 0x41010000;
+mpu_armv73.size = 15;
+mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv74.$name = "CONFIG_MPU_REGION3";
+mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv74.baseAddr = 0x70000000;
+mpu_armv74.size = 21;
+
+mpu_armv75.$name = "CONFIG_MPU_REGION4";
+mpu_armv75.baseAddr = 0x60000000;
+mpu_armv75.size = 28;
+mpu_armv75.accessPermissions = "Supervisor RD, User RD";
+
+bissc1.$name = "CONFIG_BISSC0";
+bissc1.Booster_Pack = true;
+bissc1.channel_2 = true;
+bissc1.Multi_Channel_Load_Share = true;
+bissc1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1";
+bissc1.PRU_ICSSG0_PRU.GPO4.$used = false;
+bissc1.PRU_ICSSG0_PRU.GPO3.$used = false;
+bissc1.PRU_ICSSG0_PRU.GPI14.$used = false;
+
+bissc1.ENC1_EN = gpio1;
+gpio1.$name = "ENC1_EN";
+gpio1.GPIO.$assign = "GPIO1";
+gpio1.GPIO.gpioPin.pu_pd = "pu";
+gpio1.GPIO.gpioPin.rx = false;
+
+bissc1.BISSC_CH0_OUT_EN = gpio2;
+gpio2.$name = "BISSC_CH0_OUT_EN";
+gpio2.GPIO.gpioPin.rx = false;
+gpio2.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO2";
+
+bissc1.BISSC_CH2_OUT_EN = gpio3;
+gpio3.$name = "BISSC_CH2_OUT_EN";
+gpio3.GPIO.gpioPin.rx = false;
+gpio3.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO8";
+
+bissc1.ENC2_EN = gpio4;
+gpio4.$name = "ENC2_EN";
+gpio4.GPIO.gpioPin.pu_pd = "pu";
+gpio4.GPIO.gpioPin.rx = false;
+gpio4.GPIO.gpioPin.$assign = "MMC1_SDCD";
+
+bissc1.BISSC_CH1_OUT_EN = gpio5;
+gpio5.$name = "BISSC_CH1_OUT_EN";
+gpio5.GPIO.gpioPin.rx = false;
+gpio5.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO5";
+
+gpio6.$name = "ENC0_EN";
+gpio6.pinDir = "OUTPUT";
+bissc1.ENC0_EN = gpio6;
+gpio6.GPIO.gpioPin.$assign = "MMC1_SDWP";
+
+const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
+const pruicss1 = pruicss.addInstance({}, false);
+pruicss1.$name = "CONFIG_PRU_ICSS0";
+bissc1.pru = pruicss1;
+pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
+
+/**
+ * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
+ * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to
+ * re-solve from scratch.
+ */
+debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD";
+debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD";
+bissc1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1";
+bissc1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0";
+bissc1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13";
+bissc1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12";
+bissc1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6";
+bissc1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11";
+gpio1.GPIO.gpioPin.$suggestSolution = "PRG0_PRU0_GPO0";
+gpio2.GPIO.$suggestSolution = "GPIO1";
+gpio3.GPIO.$suggestSolution = "GPIO1";
+gpio4.GPIO.$suggestSolution = "GPIO1";
+gpio5.GPIO.$suggestSolution = "GPIO1";
+gpio6.GPIO.$suggestSolution = "GPIO1";
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/main.c b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/main.c
new file mode 100644
index 0000000..de5e3bb
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/main.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include "ti_drivers_config.h"
+#include "ti_board_config.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define MAIN_TASK_PRI (5)
+
+#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE))
+StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
+
+StaticTask_t gMainTaskObj;
+TaskHandle_t gMainTask;
+
+void bissc_main(void *args);
+
+void freertos_main(void *args)
+{
+ bissc_main(NULL);
+
+ vTaskDelete(NULL);
+}
+
+
+int main(void)
+{
+ /* init SOC specific modules */
+ System_init();
+ Board_init();
+
+ /* This task is created at highest priority, it should create more tasks and then delete itself */
+ gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */
+ "freertos_main", /* Text name for the task. This is to facilitate debugging only. */
+ MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
+ NULL, /* We are not using the task parameter. */
+ MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
+ gMainTaskStack, /* pointer to stack base */
+ &gMainTaskObj ); /* pointer to statically allocated task object memory */
+ configASSERT(gMainTask != NULL);
+
+ /* Start the scheduler to start the tasks executing. */
+ vTaskStartScheduler();
+
+ /* The following line should never be reached because vTaskStartScheduler()
+ will only return if there was not enough FreeRTOS heap memory available to
+ create the Idle and (if configured) Timer tasks. Heap management, and
+ techniques for trapping heap exhaustion, are described in the book text. */
+ DebugP_assertNoLog(0);
+
+ return 0;
+}
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
new file mode 100644
index 0000000..a7d4a41
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@@ -0,0 +1,114 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
new file mode 100644
index 0000000..69640f4
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -0,0 +1,148 @@
+
+/* This is the stack that is used by code running within main()
+ * In case of NORTOS,
+ * - This means all the code outside of ISR uses this stack
+ * In case of FreeRTOS
+ * - This means all the code until vTaskStartScheduler() is called in main()
+ * uses this stack.
+ * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
+ */
+--stack_size=16384
+/* This is the heap size for malloc() API in NORTOS and FreeRTOS
+ * This is also the heap used by pvPortMalloc in FreeRTOS
+ */
+--heap_size=32768
+-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
+
+/* This is the size of stack when R5 is in IRQ mode
+ * In NORTOS,
+ * - Here interrupt nesting is enabled
+ * - This is the stack used by ISRs registered as type IRQ
+ * In FreeRTOS,
+ * - Here interrupt nesting is disabled
+ * - This is stack that is used initally when a IRQ is received
+ * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
+ * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
+ */
+__IRQ_STACK_SIZE = 256;
+/* This is the size of stack when R5 is in IRQ mode
+ * - In both NORTOS and FreeRTOS nesting is disabled for FIQ
+ */
+__FIQ_STACK_SIZE = 256;
+__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
+__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */
+__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */
+
+SECTIONS
+{
+ /* This has the R5F entry point and vector table, this MUST be at 0x0 */
+ .vectors:{} palign(8) > R5F_VECS
+
+ /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
+ * i.e this cannot be placed in DDR
+ */
+ GROUP {
+ .text.hwi: palign(8)
+ .text.cache: palign(8)
+ .text.mpu: palign(8)
+ .text.boot: palign(8)
+ .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
+ } > MSRAM
+
+ /* This is rest of code. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .text: {} palign(8) /* This is where code resides */
+ .rodata: {} palign(8) /* This is where const's go */
+ } > MSRAM
+
+ /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .data: {} palign(8) /* This is where initialized globals and static go */
+ } > MSRAM
+
+ /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .bss: {} palign(8) /* This is where uninitialized globals go */
+ RUN_START(__BSS_START)
+ RUN_END(__BSS_END)
+ .sysmem: {} palign(8) /* This is where the malloc heap goes */
+ .stack: {} palign(8) /* This is where the main() stack goes */
+ } > MSRAM
+
+ /* This is where the stacks for different R5F modes go */
+ GROUP {
+ .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+ .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
+ RUN_START(__UNDEFINED_STACK_START)
+ RUN_END(__UNDEFINED_STACK_END)
+ } > MSRAM
+
+ /* Sections needed for C++ projects */
+ GROUP {
+ .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
+ .init_array: {} palign(8) /* Contains function pointers called before main */
+ .fini_array: {} palign(8) /* Contains function pointers called after main */
+ } > MSRAM
+
+ /* General purpose user shared memory, used in some examples */
+ .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
+ /* this is used when Debug log's to shared memory are enabled, else this is not used */
+ .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
+ /* this is used only when IPC RPMessage is enabled, else this is not used */
+ .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
+ /* General purpose non cacheable memory, used in some examples */
+ .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
+}
+
+/*
+NOTE: Below memory is reserved for DMSC usage
+ - During Boot till security handoff is complete
+ 0x701E0000 - 0x701FFFFF (128KB)
+ - After "Security Handoff" is complete (i.e at run time)
+ 0x701F4000 - 0x701FFFFF (48KB)
+
+ Security handoff is complete when this message is sent to the DMSC,
+ TISCI_MSG_SEC_HANDOVER
+
+ This should be sent once all cores are loaded and all application
+ specific firewall calls are setup.
+*/
+
+MEMORY
+{
+ R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
+ R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
+ R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+
+ /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
+ NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
+
+ /* when using multi-core application's i.e more than one R5F/M4F active, make sure
+ * this memory does not overlap with other R5F's
+ */
+ MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000
+
+ /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
+ * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
+ */
+ FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000
+
+ /* shared memory segments */
+ /* On R5F,
+ * - make sure there is a MPU entry which maps below regions as non-cache
+ */
+ USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180
+ LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180
+ RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
+}
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
new file mode 100644
index 0000000..fe4ea8e
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
@@ -0,0 +1,308 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak
+
+CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
+
+CC=$(CG_TOOL_ROOT)/bin/tiarmclang
+LNK=$(CG_TOOL_ROOT)/bin/tiarmclang
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+ PYTHON=python
+else
+ PYTHON=python3
+endif
+
+PROFILE?=release
+ConfigName:=$(PROFILE)
+
+OUTNAME:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).out
+
+BOOTIMAGE_PATH=$(abspath .)
+BOOTIMAGE_NAME:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).appimage
+BOOTIMAGE_NAME_XIP:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).appimage.signed
+BOOTIMAGE_RPRC_NAME:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).rprc_tmp
+BOOTIMAGE_NAME_HS:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).appimage.hs
+BOOTIMAGE_NAME_HS_FS:=bissc_diagnostic_multi_channel_load_share.$(PROFILE).appimage.hs_fs
+TARGETS := $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+ TARGETS += $(BOOTIMAGE_NAME_HS)
+endif
+
+FILES_common := \
+ bissc_diagnostic.c \
+ main.c \
+ ti_drivers_config.c \
+ ti_drivers_open_close.c \
+ ti_board_config.c \
+ ti_board_open_close.c \
+ ti_dpl_config.c \
+ ti_pinmux_config.c \
+ ti_power_clock_config.c \
+
+FILES_PATH_common = \
+ .. \
+ ../../../.. \
+ generated \
+
+INCLUDES_common := \
+ -I${CG_TOOL_ROOT}/include/c \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source \
+ -I${MOTOR_CONTROL_SDK_PATH}/source \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \
+ -Igenerated \
+
+DEFINES_common := \
+ -DSOC_AM243X \
+ -DSOC_AM243X \
+
+CFLAGS_common := \
+ -mcpu=cortex-r5 \
+ -mfloat-abi=hard \
+ -mfpu=vfpv3-d16 \
+ -mthumb \
+ -Wall \
+ -Werror \
+ -g \
+ -Wno-gnu-variable-sized-type-not-at-end \
+ -Wno-unused-function \
+
+CFLAGS_cpp_common := \
+ -Wno-c99-designator \
+ -Wno-extern-c-compat \
+ -Wno-c++11-narrowing \
+ -Wno-reorder-init-list \
+ -Wno-deprecated-register \
+ -Wno-writable-strings \
+ -Wno-enum-compare \
+ -Wno-reserved-user-defined-literal \
+ -Wno-unused-const-variable \
+ -x c++ \
+
+CFLAGS_debug := \
+ -D_DEBUG_=1 \
+
+CFLAGS_release := \
+ -Os \
+
+LNK_FILES_common = \
+ linker.cmd \
+
+LIBS_PATH_common = \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib \
+ -Wl,-i${CG_TOOL_ROOT}/lib \
+
+LIBS_common = \
+ -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -lmotorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -llibc.a \
+ -llibsysbm.a \
+
+LFLAGS_common = \
+ -Wl,--diag_suppress=10063 \
+ -Wl,--ram_model \
+ -Wl,--reread_libs \
+
+
+LIBS_NAME = \
+ freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ motorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ libc.a \
+ libsysbm.a \
+
+LIBS_PATH_NAME = \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib \
+ ${CG_TOOL_ROOT}/lib \
+
+FILES := $(FILES_common) $(FILES_$(PROFILE))
+ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
+FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
+CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
+INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
+LIBS := $(LIBS_common) $(LIBS_$(PROFILE))
+LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE))
+LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE))
+LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE))
+LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE))
+
+OBJDIR := obj/$(PROFILE)/
+OBJS := $(FILES:%.c=%.obj)
+OBJS += $(ASMFILES:%.S=%.obj)
+DEPS := $(FILES:%.c=%.d)
+
+vpath %.obj $(OBJDIR)
+vpath %.c $(FILES_PATH)
+vpath %.S $(FILES_PATH)
+vpath %.lib $(LIBS_PATH_NAME)
+vpath %.a $(LIBS_PATH_NAME)
+
+$(OBJDIR)/%.obj %.obj: %.c
+ @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $<
+ $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.S
+ @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $<
+ $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
+
+all: $(TARGETS)
+
+SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h
+SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h
+SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h
+SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c
+SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h
+SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h
+
+$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME)
+ @echo .
+ @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ...
+ $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES)
+ @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
+ @echo .
+
+clean:
+ @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
+ $(RMDIR) $(OBJDIR)
+ $(RM) $(OUTNAME)
+ $(RM) $(BOOTIMAGE_NAME)
+ $(RM) $(BOOTIMAGE_NAME_XIP)
+ $(RM) $(BOOTIMAGE_NAME_SIGNED)
+ $(RM) $(BOOTIMAGE_NAME_HS)
+ $(RM) $(BOOTIMAGE_NAME_HS_FS)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+ $(RMDIR) generated/
+
+scrub:
+ @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang bissc_diagnostic_multi_channel_load_share ...
+ $(RMDIR) obj
+ifeq ($(OS),Windows_NT)
+ $(RM) \*.out
+ $(RM) \*.map
+ $(RM) \*.appimage*
+ $(RM) \*.rprc*
+ $(RM) \*.tiimage*
+ $(RM) \*.bin
+else
+ $(RM) *.out
+ $(RM) *.map
+ $(RM) *.appimage*
+ $(RM) *.rprc*
+ $(RM) *.tiimage*
+ $(RM) *.bin
+endif
+ $(RMDIR) generated
+
+$(OBJS): | $(OBJDIR)
+
+$(OBJDIR):
+ $(MKDIR) $@
+
+
+.NOTPARALLEL:
+
+.INTERMEDIATE: syscfg
+$(SYSCFG_GEN_FILES): syscfg
+
+syscfg: ../example.syscfg
+ @echo Generating SysConfig files ...
+ $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg
+
+syscfg-gui:
+ $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALX_beta --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+ BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+ BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+ $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+ $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+$(BOOTIMAGE_NAME): $(OUTNAME)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
+ifneq ($(OS),Windows_NT)
+ $(CHMOD) a+x $(XIPGEN_CMD)
+endif
+ $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
+ $(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!!
+ @echo .
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+ @echo .
+
+$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+ @echo Boot image signing: Encryption is disabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+else
+ @echo Boot image signing: Encryption is enabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
+ $(RM) $(BOOTIMAGE_NAME)-enc
+endif
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
+ @echo .
+endif
+-include $(addprefix $(OBJDIR)/, $(DEPS))
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
new file mode 100644
index 0000000..8666cfd
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@@ -0,0 +1,106 @@
+#
+# Auto generated makefile
+#
+
+# Below variables need to be defined outside this file or via command line
+# - MOTOR_CONTROL_SDK_PATH
+# - PROFILE
+# - CG_TOOL_ROOT
+# - OUTNAME
+# - CCS_INSTALL_DIR
+# - CCS_IDE_MODE
+
+CCS_PATH=$(CCS_INSTALL_DIR)
+include ${MOTOR_CONTROL_SDK_PATH}/imports.mak
+include ${MOTOR_CONTROL_SDK_PATH}/devconfig/devconfig.mak
+
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+ PYTHON=python
+else
+ PYTHON=python3
+endif
+
+OUTFILE=$(PROFILE)/$(OUTNAME).out
+BOOTIMAGE_PATH=$(abspath ${PROFILE})
+BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
+BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
+BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+ BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+ BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+ $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+ $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+all:
+ifeq ($(CCS_IDE_MODE),cloud)
+# No post build steps
+else
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ...
+ $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
+ $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
+ifeq ($(DEVICE_TYPE),HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+ @echo Boot image signing: Encryption is disabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
+else
+ @echo Boot image signing: Encryption is enabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
+ $(RM) $(BOOTIMAGE_NAME)-enc
+endif
+endif
+ $(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
+ @echo .
+ifeq ($(DEVICE_TYPE),HS)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
+ @echo .
+else
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+ @echo .
+endif
+endif
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
new file mode 100644
index 0000000..cad69e2
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
@@ -0,0 +1,20 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=bissc_diagnostic_multi_channel_load_share_am243x-lp_r5fss0-0_freertos_ti-arm-clang
+
+all:
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+ $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
new file mode 100644
index 0000000..472ab38
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
@@ -0,0 +1,8 @@
+/*
+ * ======== syscfg_c.rov.xs ========
+ * This file contains the information needed by the Runtime Object
+ * View (ROV) tool.
+ */
+var crovFiles = [
+ "kernel/freertos/rov/FreeRTOS.rov.js",
+];
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/.project/project.js b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/.project/project.js
new file mode 100644
index 0000000..f6c2d16
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/.project/project.js
@@ -0,0 +1,14 @@
+function getComponentProperty(device)
+{
+ return require(`./project_${device}`).getComponentProperty();
+};
+
+function getComponentBuildProperty(buildOption)
+{
+ return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption);
+};
+
+module.exports = {
+ getComponentProperty,
+ getComponentBuildProperty,
+};
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/.project/project_am243x.js b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/.project/project_am243x.js
new file mode 100644
index 0000000..b74ca4a
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/.project/project_am243x.js
@@ -0,0 +1,123 @@
+let path = require('path');
+
+let device = "am243x";
+
+const files = {
+ common: [
+ "bissc_diagnostic.c",
+ "main.c",
+ ],
+};
+
+/* Relative to where the makefile will be generated
+ * Typically at ///
+ */
+const filedirs = {
+ common: [
+ "..", /* core_os_combo base */
+ "../../../..", /* Example base */
+ ],
+};
+
+const libdirs_freertos = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib",
+ ],
+};
+
+const includes_freertos_r5f = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f",
+ ],
+};
+
+const libs_freertos_r5f = {
+ common: [
+ "freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "board.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "motorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+ ],
+};
+
+const defines_r5f = {
+ common: [
+ "SOC_AM243X",
+ ],
+};
+
+const lnkfiles = {
+ common: [
+ "linker.cmd",
+ ]
+};
+
+const syscfgfile = "../example.syscfg";
+
+const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_BISSC";
+
+const templates_freertos_r5f =
+[
+ {
+ input: ".project/templates/am243x/common/linker_r5f.cmd.xdt",
+ output: "linker.cmd",
+ },
+ {
+ input: ".project/templates/am243x/freertos/main_freertos.c.xdt",
+ output: "../main.c",
+ options: {
+ entryFunction: "bissc_main",
+ taskPri: 5,
+ },
+ }
+];
+
+const buildOptionCombos = [
+ { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-lp", os: "freertos"},
+];
+
+function getComponentProperty() {
+ let property = {};
+
+ property.dirPath = path.resolve(__dirname, "..");
+ property.type = "executable";
+ property.name = "bissc_diagnostic_multi_channel_single_pru";
+ property.isInternal = false;
+ property.buildOptionCombos = buildOptionCombos;
+ property.isSkipTopLevelBuild = false;
+
+ return property;
+}
+
+function getComponentBuildProperty(buildOption) {
+ let build_property = {};
+
+ build_property.files = files;
+ build_property.filedirs = filedirs;
+ build_property.lnkfiles = lnkfiles;
+ build_property.syscfgfile = syscfgfile;
+ build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
+
+ if(buildOption.cpu.match(/r5f*/)) {
+ if(buildOption.os.match(/freertos*/) )
+ {
+ build_property.includes = includes_freertos_r5f;
+ build_property.libdirs = libdirs_freertos;
+ build_property.libs = libs_freertos_r5f;
+ build_property.templates = templates_freertos_r5f;
+ build_property.defines = defines_r5f;
+ }
+ }
+
+ return build_property;
+}
+
+module.exports = {
+ getComponentProperty,
+ getComponentBuildProperty,
+};
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/.project/project_am64x.js b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/.project/project_am64x.js
new file mode 100644
index 0000000..e1dc790
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/.project/project_am64x.js
@@ -0,0 +1,123 @@
+let path = require('path');
+
+let device = "am64x";
+
+const files = {
+ common: [
+ "bissc_diagnostic.c",
+ "main.c",
+ ],
+};
+
+/* Relative to where the makefile will be generated
+ * Typically at ///
+ */
+const filedirs = {
+ common: [
+ "..", /* core_os_combo base */
+ "../../../..", /* Example base */
+ ],
+};
+
+const libdirs_freertos = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib",
+ ],
+};
+
+const includes_freertos_r5f = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am64x/r5f",
+ ],
+};
+
+const libs_freertos_r5f = {
+ common: [
+ "freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "board.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "motorcontrol_bissc.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
+ ],
+};
+
+const defines_r5f = {
+ common: [
+ "SOC_AM64X",
+ ],
+};
+
+const lnkfiles = {
+ common: [
+ "linker.cmd",
+ ]
+};
+
+const syscfgfile = "../example.syscfg";
+
+const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_BISSC";
+
+const templates_freertos_r5f =
+[
+ {
+ input: ".project/templates/am64x/common/linker_r5f.cmd.xdt",
+ output: "linker.cmd",
+ },
+ {
+ input: ".project/templates/am64x/freertos/main_freertos.c.xdt",
+ output: "../main.c",
+ options: {
+ entryFunction: "bissc_main",
+ taskPri: 5,
+ },
+ }
+];
+
+const buildOptionCombos = [
+ { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"},
+];
+
+function getComponentProperty() {
+ let property = {};
+
+ property.dirPath = path.resolve(__dirname, "..");
+ property.type = "executable";
+ property.name = "bissc_diagnostic_multi_channel_single_pru";
+ property.isInternal = false;
+ property.buildOptionCombos = buildOptionCombos;
+ property.isSkipTopLevelBuild = false;
+
+ return property;
+}
+
+function getComponentBuildProperty(buildOption) {
+ let build_property = {};
+
+ build_property.files = files;
+ build_property.filedirs = filedirs;
+ build_property.lnkfiles = lnkfiles;
+ build_property.syscfgfile = syscfgfile;
+ build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
+
+ if(buildOption.cpu.match(/r5f*/)) {
+ if(buildOption.os.match(/freertos*/) )
+ {
+ build_property.includes = includes_freertos_r5f;
+ build_property.libdirs = libdirs_freertos;
+ build_property.libs = libs_freertos_r5f;
+ build_property.templates = templates_freertos_r5f;
+ build_property.defines = defines_r5f;
+ }
+ }
+
+ return build_property;
+}
+
+module.exports = {
+ getComponentProperty,
+ getComponentBuildProperty,
+};
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/example.syscfg b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/example.syscfg
new file mode 100644
index 0000000..86efa4a
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/example.syscfg
@@ -0,0 +1,101 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK_AM243X@09.01.00"
+ * @versions {"tool":"1.18.0+3266"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false);
+const i2c1 = i2c.addInstance();
+const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
+const pruicss1 = pruicss.addInstance();
+const debug_log = scripting.addModule("/kernel/dpl/debug_log");
+const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
+const mpu_armv71 = mpu_armv7.addInstance();
+const mpu_armv72 = mpu_armv7.addInstance();
+const mpu_armv73 = mpu_armv7.addInstance();
+const mpu_armv74 = mpu_armv7.addInstance();
+const mpu_armv75 = mpu_armv7.addInstance();
+const mpu_armv76 = mpu_armv7.addInstance();
+const timer = scripting.addModule("/kernel/dpl/timer", {}, false);
+const timer1 = timer.addInstance();
+const endat = scripting.addModule("/position_sense/endat", {}, false);
+const endat1 = endat.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+i2c1.$name = "CONFIG_I2C0";
+i2c1.I2C.$assign = "I2C1";
+
+debug_log.enableCssLog = false;
+debug_log.enableUartLog = true;
+debug_log.uartLog.$name = "CONFIG_UART0";
+
+mpu_armv71.$name = "CONFIG_MPU_REGION0";
+mpu_armv71.size = 31;
+mpu_armv71.attributes = "Device";
+mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv72.$name = "CONFIG_MPU_REGION1";
+mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv72.size = 15;
+
+mpu_armv73.$name = "CONFIG_MPU_REGION2";
+mpu_armv73.size = 15;
+mpu_armv73.baseAddr = 0x41010000;
+mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv74.$name = "CONFIG_MPU_REGION3";
+mpu_armv74.size = 21;
+mpu_armv74.baseAddr = 0x70000000;
+mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv75.$name = "CONFIG_MPU_REGION4";
+mpu_armv75.size = 28;
+mpu_armv75.baseAddr = 0x60000000;
+mpu_armv75.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv76.$name = "CONFIG_MPU_REGION5";
+mpu_armv76.size = 31;
+mpu_armv76.baseAddr = 0x80000000;
+
+timer1.$name = "CONFIG_TIMER0";
+timer1.timerCallback = "endat_position_loop";
+timer1.intrPriority = 0;
+timer1.TIMER.$assign = "DMTIMER0";
+
+endat1.$name = "CONFIG_ENDAT0";
+endat1.Channel_1 = true;
+endat1.Channel_2 = true;
+endat1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1";
+
+pruicss1.$name = "CONFIG_PRU_ICSS0";
+endat1.pru = pruicss1;
+pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
+
+/**
+ * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
+ * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to
+ * re-solve from scratch.
+ */
+i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL";
+i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA";
+debug_log.uartLog.UART.$suggestSolution = "USART0";
+debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD";
+debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD";
+endat1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2";
+endat1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1";
+endat1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0";
+endat1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13";
+endat1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5";
+endat1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4";
+endat1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3";
+endat1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14";
+endat1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8";
+endat1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12";
+endat1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6";
+endat1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11";
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/main.c b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/main.c
new file mode 100644
index 0000000..de5e3bb
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/main.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include "ti_drivers_config.h"
+#include "ti_board_config.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define MAIN_TASK_PRI (5)
+
+#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE))
+StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
+
+StaticTask_t gMainTaskObj;
+TaskHandle_t gMainTask;
+
+void bissc_main(void *args);
+
+void freertos_main(void *args)
+{
+ bissc_main(NULL);
+
+ vTaskDelete(NULL);
+}
+
+
+int main(void)
+{
+ /* init SOC specific modules */
+ System_init();
+ Board_init();
+
+ /* This task is created at highest priority, it should create more tasks and then delete itself */
+ gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */
+ "freertos_main", /* Text name for the task. This is to facilitate debugging only. */
+ MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
+ NULL, /* We are not using the task parameter. */
+ MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
+ gMainTaskStack, /* pointer to stack base */
+ &gMainTaskObj ); /* pointer to statically allocated task object memory */
+ configASSERT(gMainTask != NULL);
+
+ /* Start the scheduler to start the tasks executing. */
+ vTaskStartScheduler();
+
+ /* The following line should never be reached because vTaskStartScheduler()
+ will only return if there was not enough FreeRTOS heap memory available to
+ create the Idle and (if configured) Timer tasks. Heap management, and
+ techniques for trapping heap exhaustion, are described in the book text. */
+ DebugP_assertNoLog(0);
+
+ return 0;
+}
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec
new file mode 100644
index 0000000..33ef666
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@@ -0,0 +1,114 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
new file mode 100644
index 0000000..69640f4
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -0,0 +1,148 @@
+
+/* This is the stack that is used by code running within main()
+ * In case of NORTOS,
+ * - This means all the code outside of ISR uses this stack
+ * In case of FreeRTOS
+ * - This means all the code until vTaskStartScheduler() is called in main()
+ * uses this stack.
+ * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
+ */
+--stack_size=16384
+/* This is the heap size for malloc() API in NORTOS and FreeRTOS
+ * This is also the heap used by pvPortMalloc in FreeRTOS
+ */
+--heap_size=32768
+-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
+
+/* This is the size of stack when R5 is in IRQ mode
+ * In NORTOS,
+ * - Here interrupt nesting is enabled
+ * - This is the stack used by ISRs registered as type IRQ
+ * In FreeRTOS,
+ * - Here interrupt nesting is disabled
+ * - This is stack that is used initally when a IRQ is received
+ * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
+ * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
+ */
+__IRQ_STACK_SIZE = 256;
+/* This is the size of stack when R5 is in IRQ mode
+ * - In both NORTOS and FreeRTOS nesting is disabled for FIQ
+ */
+__FIQ_STACK_SIZE = 256;
+__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
+__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */
+__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */
+
+SECTIONS
+{
+ /* This has the R5F entry point and vector table, this MUST be at 0x0 */
+ .vectors:{} palign(8) > R5F_VECS
+
+ /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
+ * i.e this cannot be placed in DDR
+ */
+ GROUP {
+ .text.hwi: palign(8)
+ .text.cache: palign(8)
+ .text.mpu: palign(8)
+ .text.boot: palign(8)
+ .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
+ } > MSRAM
+
+ /* This is rest of code. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .text: {} palign(8) /* This is where code resides */
+ .rodata: {} palign(8) /* This is where const's go */
+ } > MSRAM
+
+ /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .data: {} palign(8) /* This is where initialized globals and static go */
+ } > MSRAM
+
+ /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .bss: {} palign(8) /* This is where uninitialized globals go */
+ RUN_START(__BSS_START)
+ RUN_END(__BSS_END)
+ .sysmem: {} palign(8) /* This is where the malloc heap goes */
+ .stack: {} palign(8) /* This is where the main() stack goes */
+ } > MSRAM
+
+ /* This is where the stacks for different R5F modes go */
+ GROUP {
+ .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+ .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
+ RUN_START(__UNDEFINED_STACK_START)
+ RUN_END(__UNDEFINED_STACK_END)
+ } > MSRAM
+
+ /* Sections needed for C++ projects */
+ GROUP {
+ .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
+ .init_array: {} palign(8) /* Contains function pointers called before main */
+ .fini_array: {} palign(8) /* Contains function pointers called after main */
+ } > MSRAM
+
+ /* General purpose user shared memory, used in some examples */
+ .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
+ /* this is used when Debug log's to shared memory are enabled, else this is not used */
+ .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
+ /* this is used only when IPC RPMessage is enabled, else this is not used */
+ .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
+ /* General purpose non cacheable memory, used in some examples */
+ .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
+}
+
+/*
+NOTE: Below memory is reserved for DMSC usage
+ - During Boot till security handoff is complete
+ 0x701E0000 - 0x701FFFFF (128KB)
+ - After "Security Handoff" is complete (i.e at run time)
+ 0x701F4000 - 0x701FFFFF (48KB)
+
+ Security handoff is complete when this message is sent to the DMSC,
+ TISCI_MSG_SEC_HANDOVER
+
+ This should be sent once all cores are loaded and all application
+ specific firewall calls are setup.
+*/
+
+MEMORY
+{
+ R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
+ R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
+ R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+
+ /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
+ NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
+
+ /* when using multi-core application's i.e more than one R5F/M4F active, make sure
+ * this memory does not overlap with other R5F's
+ */
+ MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000
+
+ /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
+ * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
+ */
+ FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000
+
+ /* shared memory segments */
+ /* On R5F,
+ * - make sure there is a MPU entry which maps below regions as non-cache
+ */
+ USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180
+ LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180
+ RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
+}
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile
new file mode 100644
index 0000000..72d8220
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile
@@ -0,0 +1,308 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak
+
+CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
+
+CC=$(CG_TOOL_ROOT)/bin/tiarmclang
+LNK=$(CG_TOOL_ROOT)/bin/tiarmclang
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+ PYTHON=python
+else
+ PYTHON=python3
+endif
+
+PROFILE?=release
+ConfigName:=$(PROFILE)
+
+OUTNAME:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).out
+
+BOOTIMAGE_PATH=$(abspath .)
+BOOTIMAGE_NAME:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).appimage
+BOOTIMAGE_NAME_XIP:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).appimage.signed
+BOOTIMAGE_RPRC_NAME:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).rprc_tmp
+BOOTIMAGE_NAME_HS:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).appimage.hs
+BOOTIMAGE_NAME_HS_FS:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).appimage.hs_fs
+TARGETS := $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+ TARGETS += $(BOOTIMAGE_NAME_HS)
+endif
+
+FILES_common := \
+ bissc_diagnostic.c \
+ main.c \
+ ti_drivers_config.c \
+ ti_drivers_open_close.c \
+ ti_board_config.c \
+ ti_board_open_close.c \
+ ti_dpl_config.c \
+ ti_pinmux_config.c \
+ ti_power_clock_config.c \
+
+FILES_PATH_common = \
+ .. \
+ ../../../.. \
+ generated \
+
+INCLUDES_common := \
+ -I${CG_TOOL_ROOT}/include/c \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source \
+ -I${MOTOR_CONTROL_SDK_PATH}/source \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \
+ -Igenerated \
+
+DEFINES_common := \
+ -DSOC_AM243X \
+ -DSOC_AM243X \
+
+CFLAGS_common := \
+ -mcpu=cortex-r5 \
+ -mfloat-abi=hard \
+ -mfpu=vfpv3-d16 \
+ -mthumb \
+ -Wall \
+ -Werror \
+ -g \
+ -Wno-gnu-variable-sized-type-not-at-end \
+ -Wno-unused-function \
+
+CFLAGS_cpp_common := \
+ -Wno-c99-designator \
+ -Wno-extern-c-compat \
+ -Wno-c++11-narrowing \
+ -Wno-reorder-init-list \
+ -Wno-deprecated-register \
+ -Wno-writable-strings \
+ -Wno-enum-compare \
+ -Wno-reserved-user-defined-literal \
+ -Wno-unused-const-variable \
+ -x c++ \
+
+CFLAGS_debug := \
+ -D_DEBUG_=1 \
+
+CFLAGS_release := \
+ -Os \
+
+LNK_FILES_common = \
+ linker.cmd \
+
+LIBS_PATH_common = \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib \
+ -Wl,-i${CG_TOOL_ROOT}/lib \
+
+LIBS_common = \
+ -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -lmotorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -llibc.a \
+ -llibsysbm.a \
+
+LFLAGS_common = \
+ -Wl,--diag_suppress=10063 \
+ -Wl,--ram_model \
+ -Wl,--reread_libs \
+
+
+LIBS_NAME = \
+ freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ motorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ libc.a \
+ libsysbm.a \
+
+LIBS_PATH_NAME = \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib \
+ ${CG_TOOL_ROOT}/lib \
+
+FILES := $(FILES_common) $(FILES_$(PROFILE))
+ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
+FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
+CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
+INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
+LIBS := $(LIBS_common) $(LIBS_$(PROFILE))
+LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE))
+LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE))
+LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE))
+LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE))
+
+OBJDIR := obj/$(PROFILE)/
+OBJS := $(FILES:%.c=%.obj)
+OBJS += $(ASMFILES:%.S=%.obj)
+DEPS := $(FILES:%.c=%.d)
+
+vpath %.obj $(OBJDIR)
+vpath %.c $(FILES_PATH)
+vpath %.S $(FILES_PATH)
+vpath %.lib $(LIBS_PATH_NAME)
+vpath %.a $(LIBS_PATH_NAME)
+
+$(OBJDIR)/%.obj %.obj: %.c
+ @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $<
+ $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.S
+ @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $<
+ $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
+
+all: $(TARGETS)
+
+SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h
+SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h
+SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h
+SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c
+SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h
+SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h
+
+$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME)
+ @echo .
+ @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ...
+ $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES)
+ @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
+ @echo .
+
+clean:
+ @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
+ $(RMDIR) $(OBJDIR)
+ $(RM) $(OUTNAME)
+ $(RM) $(BOOTIMAGE_NAME)
+ $(RM) $(BOOTIMAGE_NAME_XIP)
+ $(RM) $(BOOTIMAGE_NAME_SIGNED)
+ $(RM) $(BOOTIMAGE_NAME_HS)
+ $(RM) $(BOOTIMAGE_NAME_HS_FS)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+ $(RMDIR) generated/
+
+scrub:
+ @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang bissc_diagnostic_multi_channel_single_pru ...
+ $(RMDIR) obj
+ifeq ($(OS),Windows_NT)
+ $(RM) \*.out
+ $(RM) \*.map
+ $(RM) \*.appimage*
+ $(RM) \*.rprc*
+ $(RM) \*.tiimage*
+ $(RM) \*.bin
+else
+ $(RM) *.out
+ $(RM) *.map
+ $(RM) *.appimage*
+ $(RM) *.rprc*
+ $(RM) *.tiimage*
+ $(RM) *.bin
+endif
+ $(RMDIR) generated
+
+$(OBJS): | $(OBJDIR)
+
+$(OBJDIR):
+ $(MKDIR) $@
+
+
+.NOTPARALLEL:
+
+.INTERMEDIATE: syscfg
+$(SYSCFG_GEN_FILES): syscfg
+
+syscfg: ../example.syscfg
+ @echo Generating SysConfig files ...
+ $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg
+
+syscfg-gui:
+ $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALV_beta --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+ BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+ BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+ $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+ $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+$(BOOTIMAGE_NAME): $(OUTNAME)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
+ifneq ($(OS),Windows_NT)
+ $(CHMOD) a+x $(XIPGEN_CMD)
+endif
+ $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
+ $(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!!
+ @echo .
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+ @echo .
+
+$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+ @echo Boot image signing: Encryption is disabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+else
+ @echo Boot image signing: Encryption is enabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
+ $(RM) $(BOOTIMAGE_NAME)-enc
+endif
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
+ @echo .
+endif
+-include $(addprefix $(OBJDIR)/, $(DEPS))
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
new file mode 100644
index 0000000..8666cfd
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@@ -0,0 +1,106 @@
+#
+# Auto generated makefile
+#
+
+# Below variables need to be defined outside this file or via command line
+# - MOTOR_CONTROL_SDK_PATH
+# - PROFILE
+# - CG_TOOL_ROOT
+# - OUTNAME
+# - CCS_INSTALL_DIR
+# - CCS_IDE_MODE
+
+CCS_PATH=$(CCS_INSTALL_DIR)
+include ${MOTOR_CONTROL_SDK_PATH}/imports.mak
+include ${MOTOR_CONTROL_SDK_PATH}/devconfig/devconfig.mak
+
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+ PYTHON=python
+else
+ PYTHON=python3
+endif
+
+OUTFILE=$(PROFILE)/$(OUTNAME).out
+BOOTIMAGE_PATH=$(abspath ${PROFILE})
+BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
+BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
+BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+ BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+ BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+ $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+ $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+all:
+ifeq ($(CCS_IDE_MODE),cloud)
+# No post build steps
+else
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ...
+ $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
+ $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
+ifeq ($(DEVICE_TYPE),HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+ @echo Boot image signing: Encryption is disabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
+else
+ @echo Boot image signing: Encryption is enabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
+ $(RM) $(BOOTIMAGE_NAME)-enc
+endif
+endif
+ $(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
+ @echo .
+ifeq ($(DEVICE_TYPE),HS)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
+ @echo .
+else
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+ @echo .
+endif
+endif
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
new file mode 100644
index 0000000..bedcefa
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
@@ -0,0 +1,20 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=bissc_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang
+
+all:
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+ $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
new file mode 100644
index 0000000..472ab38
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
@@ -0,0 +1,8 @@
+/*
+ * ======== syscfg_c.rov.xs ========
+ * This file contains the information needed by the Runtime Object
+ * View (ROV) tool.
+ */
+var crovFiles = [
+ "kernel/freertos/rov/FreeRTOS.rov.js",
+];
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/example.syscfg b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/example.syscfg
new file mode 100644
index 0000000..607338e
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/example.syscfg
@@ -0,0 +1,125 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM243x_ALX_beta" --package "ALX" --part "ALX" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK@09.01.00"
+ * @versions {"tool":"1.18.0+3266"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false);
+const gpio1 = gpio.addInstance();
+const gpio2 = gpio.addInstance();
+const gpio3 = gpio.addInstance();
+const gpio4 = gpio.addInstance();
+const gpio5 = gpio.addInstance();
+const gpio6 = gpio.addInstance();
+const debug_log = scripting.addModule("/kernel/dpl/debug_log");
+const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
+const mpu_armv71 = mpu_armv7.addInstance();
+const mpu_armv72 = mpu_armv7.addInstance();
+const mpu_armv73 = mpu_armv7.addInstance();
+const mpu_armv74 = mpu_armv7.addInstance();
+const mpu_armv75 = mpu_armv7.addInstance();
+const bissc = scripting.addModule("/position_sense/bissc", {}, false);
+const bissc1 = bissc.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+debug_log.enableUartLog = true;
+debug_log.enableCssLog = false;
+debug_log.uartLog.$name = "CONFIG_UART_CONSOLE";
+debug_log.uartLog.UART.$assign = "USART0";
+
+mpu_armv71.$name = "CONFIG_MPU_REGION0";
+mpu_armv71.size = 31;
+mpu_armv71.attributes = "Device";
+mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv71.allowExecute = false;
+
+mpu_armv72.$name = "CONFIG_MPU_REGION1";
+mpu_armv72.size = 15;
+mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv73.$name = "CONFIG_MPU_REGION2";
+mpu_armv73.baseAddr = 0x41010000;
+mpu_armv73.size = 15;
+mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv74.$name = "CONFIG_MPU_REGION3";
+mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv74.baseAddr = 0x70000000;
+mpu_armv74.size = 21;
+
+mpu_armv75.$name = "CONFIG_MPU_REGION4";
+mpu_armv75.baseAddr = 0x60000000;
+mpu_armv75.size = 28;
+mpu_armv75.accessPermissions = "Supervisor RD, User RD";
+
+bissc1.$name = "CONFIG_BISSC0";
+bissc1.Booster_Pack = true;
+bissc1.channel_2 = true;
+bissc1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1";
+bissc1.PRU_ICSSG0_PRU.GPO4.$used = false;
+bissc1.PRU_ICSSG0_PRU.GPO3.$used = false;
+bissc1.PRU_ICSSG0_PRU.GPI14.$used = false;
+
+bissc1.ENC1_EN = gpio1;
+gpio1.$name = "ENC1_EN";
+gpio1.GPIO.$assign = "GPIO1";
+gpio1.GPIO.gpioPin.pu_pd = "pu";
+gpio1.GPIO.gpioPin.rx = false;
+
+bissc1.BISSC_CH0_OUT_EN = gpio2;
+gpio2.$name = "BISSC_CH0_OUT_EN";
+gpio2.GPIO.gpioPin.rx = false;
+gpio2.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO2";
+
+bissc1.BISSC_CH2_OUT_EN = gpio3;
+gpio3.$name = "BISSC_CH2_OUT_EN";
+gpio3.GPIO.gpioPin.rx = false;
+gpio3.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO8";
+
+bissc1.ENC2_EN = gpio4;
+gpio4.$name = "ENC2_EN";
+gpio4.GPIO.gpioPin.pu_pd = "pu";
+gpio4.GPIO.gpioPin.rx = false;
+gpio4.GPIO.gpioPin.$assign = "MMC1_SDCD";
+
+bissc1.BISSC_CH1_OUT_EN = gpio5;
+gpio5.$name = "BISSC_CH1_OUT_EN";
+gpio5.GPIO.gpioPin.rx = false;
+gpio5.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO5";
+
+gpio6.$name = "ENC0_EN";
+gpio6.pinDir = "OUTPUT";
+bissc1.ENC0_EN = gpio6;
+gpio6.GPIO.gpioPin.$assign = "MMC1_SDWP";
+
+const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
+const pruicss1 = pruicss.addInstance({}, false);
+pruicss1.$name = "CONFIG_PRU_ICSS0";
+bissc1.pru = pruicss1;
+pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
+
+/**
+ * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
+ * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to
+ * re-solve from scratch.
+ */
+debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD";
+debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD";
+bissc1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1";
+bissc1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0";
+bissc1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13";
+bissc1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12";
+bissc1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6";
+bissc1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11";
+gpio1.GPIO.gpioPin.$suggestSolution = "PRG0_PRU0_GPO0";
+gpio2.GPIO.$suggestSolution = "GPIO1";
+gpio3.GPIO.$suggestSolution = "GPIO1";
+gpio4.GPIO.$suggestSolution = "GPIO1";
+gpio5.GPIO.$suggestSolution = "GPIO1";
+gpio6.GPIO.$suggestSolution = "GPIO1";
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/main.c b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/main.c
new file mode 100644
index 0000000..de5e3bb
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/main.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include "ti_drivers_config.h"
+#include "ti_board_config.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define MAIN_TASK_PRI (5)
+
+#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE))
+StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
+
+StaticTask_t gMainTaskObj;
+TaskHandle_t gMainTask;
+
+void bissc_main(void *args);
+
+void freertos_main(void *args)
+{
+ bissc_main(NULL);
+
+ vTaskDelete(NULL);
+}
+
+
+int main(void)
+{
+ /* init SOC specific modules */
+ System_init();
+ Board_init();
+
+ /* This task is created at highest priority, it should create more tasks and then delete itself */
+ gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */
+ "freertos_main", /* Text name for the task. This is to facilitate debugging only. */
+ MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
+ NULL, /* We are not using the task parameter. */
+ MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
+ gMainTaskStack, /* pointer to stack base */
+ &gMainTaskObj ); /* pointer to statically allocated task object memory */
+ configASSERT(gMainTask != NULL);
+
+ /* Start the scheduler to start the tasks executing. */
+ vTaskStartScheduler();
+
+ /* The following line should never be reached because vTaskStartScheduler()
+ will only return if there was not enough FreeRTOS heap memory available to
+ create the Idle and (if configured) Timer tasks. Heap management, and
+ techniques for trapping heap exhaustion, are described in the book text. */
+ DebugP_assertNoLog(0);
+
+ return 0;
+}
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
new file mode 100644
index 0000000..757fc00
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@@ -0,0 +1,114 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
new file mode 100644
index 0000000..69640f4
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -0,0 +1,148 @@
+
+/* This is the stack that is used by code running within main()
+ * In case of NORTOS,
+ * - This means all the code outside of ISR uses this stack
+ * In case of FreeRTOS
+ * - This means all the code until vTaskStartScheduler() is called in main()
+ * uses this stack.
+ * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
+ */
+--stack_size=16384
+/* This is the heap size for malloc() API in NORTOS and FreeRTOS
+ * This is also the heap used by pvPortMalloc in FreeRTOS
+ */
+--heap_size=32768
+-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
+
+/* This is the size of stack when R5 is in IRQ mode
+ * In NORTOS,
+ * - Here interrupt nesting is enabled
+ * - This is the stack used by ISRs registered as type IRQ
+ * In FreeRTOS,
+ * - Here interrupt nesting is disabled
+ * - This is stack that is used initally when a IRQ is received
+ * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
+ * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
+ */
+__IRQ_STACK_SIZE = 256;
+/* This is the size of stack when R5 is in IRQ mode
+ * - In both NORTOS and FreeRTOS nesting is disabled for FIQ
+ */
+__FIQ_STACK_SIZE = 256;
+__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
+__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */
+__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */
+
+SECTIONS
+{
+ /* This has the R5F entry point and vector table, this MUST be at 0x0 */
+ .vectors:{} palign(8) > R5F_VECS
+
+ /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
+ * i.e this cannot be placed in DDR
+ */
+ GROUP {
+ .text.hwi: palign(8)
+ .text.cache: palign(8)
+ .text.mpu: palign(8)
+ .text.boot: palign(8)
+ .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
+ } > MSRAM
+
+ /* This is rest of code. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .text: {} palign(8) /* This is where code resides */
+ .rodata: {} palign(8) /* This is where const's go */
+ } > MSRAM
+
+ /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .data: {} palign(8) /* This is where initialized globals and static go */
+ } > MSRAM
+
+ /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .bss: {} palign(8) /* This is where uninitialized globals go */
+ RUN_START(__BSS_START)
+ RUN_END(__BSS_END)
+ .sysmem: {} palign(8) /* This is where the malloc heap goes */
+ .stack: {} palign(8) /* This is where the main() stack goes */
+ } > MSRAM
+
+ /* This is where the stacks for different R5F modes go */
+ GROUP {
+ .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+ .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
+ RUN_START(__UNDEFINED_STACK_START)
+ RUN_END(__UNDEFINED_STACK_END)
+ } > MSRAM
+
+ /* Sections needed for C++ projects */
+ GROUP {
+ .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
+ .init_array: {} palign(8) /* Contains function pointers called before main */
+ .fini_array: {} palign(8) /* Contains function pointers called after main */
+ } > MSRAM
+
+ /* General purpose user shared memory, used in some examples */
+ .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
+ /* this is used when Debug log's to shared memory are enabled, else this is not used */
+ .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
+ /* this is used only when IPC RPMessage is enabled, else this is not used */
+ .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
+ /* General purpose non cacheable memory, used in some examples */
+ .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
+}
+
+/*
+NOTE: Below memory is reserved for DMSC usage
+ - During Boot till security handoff is complete
+ 0x701E0000 - 0x701FFFFF (128KB)
+ - After "Security Handoff" is complete (i.e at run time)
+ 0x701F4000 - 0x701FFFFF (48KB)
+
+ Security handoff is complete when this message is sent to the DMSC,
+ TISCI_MSG_SEC_HANDOVER
+
+ This should be sent once all cores are loaded and all application
+ specific firewall calls are setup.
+*/
+
+MEMORY
+{
+ R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
+ R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
+ R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+
+ /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
+ NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
+
+ /* when using multi-core application's i.e more than one R5F/M4F active, make sure
+ * this memory does not overlap with other R5F's
+ */
+ MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000
+
+ /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
+ * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
+ */
+ FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000
+
+ /* shared memory segments */
+ /* On R5F,
+ * - make sure there is a MPU entry which maps below regions as non-cache
+ */
+ USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180
+ LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180
+ RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
+}
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
new file mode 100644
index 0000000..f4f912f
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
@@ -0,0 +1,308 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak
+
+CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
+
+CC=$(CG_TOOL_ROOT)/bin/tiarmclang
+LNK=$(CG_TOOL_ROOT)/bin/tiarmclang
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+ PYTHON=python
+else
+ PYTHON=python3
+endif
+
+PROFILE?=release
+ConfigName:=$(PROFILE)
+
+OUTNAME:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).out
+
+BOOTIMAGE_PATH=$(abspath .)
+BOOTIMAGE_NAME:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).appimage
+BOOTIMAGE_NAME_XIP:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).appimage.signed
+BOOTIMAGE_RPRC_NAME:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).rprc_tmp
+BOOTIMAGE_NAME_HS:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).appimage.hs
+BOOTIMAGE_NAME_HS_FS:=bissc_diagnostic_multi_channel_single_pru.$(PROFILE).appimage.hs_fs
+TARGETS := $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+ TARGETS += $(BOOTIMAGE_NAME_HS)
+endif
+
+FILES_common := \
+ bissc_diagnostic.c \
+ main.c \
+ ti_drivers_config.c \
+ ti_drivers_open_close.c \
+ ti_board_config.c \
+ ti_board_open_close.c \
+ ti_dpl_config.c \
+ ti_pinmux_config.c \
+ ti_power_clock_config.c \
+
+FILES_PATH_common = \
+ .. \
+ ../../../.. \
+ generated \
+
+INCLUDES_common := \
+ -I${CG_TOOL_ROOT}/include/c \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source \
+ -I${MOTOR_CONTROL_SDK_PATH}/source \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \
+ -Igenerated \
+
+DEFINES_common := \
+ -DSOC_AM243X \
+ -DSOC_AM243X \
+
+CFLAGS_common := \
+ -mcpu=cortex-r5 \
+ -mfloat-abi=hard \
+ -mfpu=vfpv3-d16 \
+ -mthumb \
+ -Wall \
+ -Werror \
+ -g \
+ -Wno-gnu-variable-sized-type-not-at-end \
+ -Wno-unused-function \
+
+CFLAGS_cpp_common := \
+ -Wno-c99-designator \
+ -Wno-extern-c-compat \
+ -Wno-c++11-narrowing \
+ -Wno-reorder-init-list \
+ -Wno-deprecated-register \
+ -Wno-writable-strings \
+ -Wno-enum-compare \
+ -Wno-reserved-user-defined-literal \
+ -Wno-unused-const-variable \
+ -x c++ \
+
+CFLAGS_debug := \
+ -D_DEBUG_=1 \
+
+CFLAGS_release := \
+ -Os \
+
+LNK_FILES_common = \
+ linker.cmd \
+
+LIBS_PATH_common = \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib \
+ -Wl,-i${CG_TOOL_ROOT}/lib \
+
+LIBS_common = \
+ -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -lmotorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -llibc.a \
+ -llibsysbm.a \
+
+LFLAGS_common = \
+ -Wl,--diag_suppress=10063 \
+ -Wl,--ram_model \
+ -Wl,--reread_libs \
+
+
+LIBS_NAME = \
+ freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ motorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ libc.a \
+ libsysbm.a \
+
+LIBS_PATH_NAME = \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib \
+ ${CG_TOOL_ROOT}/lib \
+
+FILES := $(FILES_common) $(FILES_$(PROFILE))
+ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
+FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
+CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
+INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
+LIBS := $(LIBS_common) $(LIBS_$(PROFILE))
+LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE))
+LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE))
+LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE))
+LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE))
+
+OBJDIR := obj/$(PROFILE)/
+OBJS := $(FILES:%.c=%.obj)
+OBJS += $(ASMFILES:%.S=%.obj)
+DEPS := $(FILES:%.c=%.d)
+
+vpath %.obj $(OBJDIR)
+vpath %.c $(FILES_PATH)
+vpath %.S $(FILES_PATH)
+vpath %.lib $(LIBS_PATH_NAME)
+vpath %.a $(LIBS_PATH_NAME)
+
+$(OBJDIR)/%.obj %.obj: %.c
+ @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $<
+ $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.S
+ @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $<
+ $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
+
+all: $(TARGETS)
+
+SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h
+SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h
+SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h
+SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c
+SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h
+SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h
+
+$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME)
+ @echo .
+ @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ...
+ $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES)
+ @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
+ @echo .
+
+clean:
+ @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
+ $(RMDIR) $(OBJDIR)
+ $(RM) $(OUTNAME)
+ $(RM) $(BOOTIMAGE_NAME)
+ $(RM) $(BOOTIMAGE_NAME_XIP)
+ $(RM) $(BOOTIMAGE_NAME_SIGNED)
+ $(RM) $(BOOTIMAGE_NAME_HS)
+ $(RM) $(BOOTIMAGE_NAME_HS_FS)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+ $(RMDIR) generated/
+
+scrub:
+ @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang bissc_diagnostic_multi_channel_single_pru ...
+ $(RMDIR) obj
+ifeq ($(OS),Windows_NT)
+ $(RM) \*.out
+ $(RM) \*.map
+ $(RM) \*.appimage*
+ $(RM) \*.rprc*
+ $(RM) \*.tiimage*
+ $(RM) \*.bin
+else
+ $(RM) *.out
+ $(RM) *.map
+ $(RM) *.appimage*
+ $(RM) *.rprc*
+ $(RM) *.tiimage*
+ $(RM) *.bin
+endif
+ $(RMDIR) generated
+
+$(OBJS): | $(OBJDIR)
+
+$(OBJDIR):
+ $(MKDIR) $@
+
+
+.NOTPARALLEL:
+
+.INTERMEDIATE: syscfg
+$(SYSCFG_GEN_FILES): syscfg
+
+syscfg: ../example.syscfg
+ @echo Generating SysConfig files ...
+ $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg
+
+syscfg-gui:
+ $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALX_beta --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+ BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+ BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+ $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+ $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+$(BOOTIMAGE_NAME): $(OUTNAME)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
+ifneq ($(OS),Windows_NT)
+ $(CHMOD) a+x $(XIPGEN_CMD)
+endif
+ $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
+ $(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!!
+ @echo .
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+ @echo .
+
+$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+ @echo Boot image signing: Encryption is disabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+else
+ @echo Boot image signing: Encryption is enabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
+ $(RM) $(BOOTIMAGE_NAME)-enc
+endif
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
+ @echo .
+endif
+-include $(addprefix $(OBJDIR)/, $(DEPS))
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
new file mode 100644
index 0000000..8666cfd
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@@ -0,0 +1,106 @@
+#
+# Auto generated makefile
+#
+
+# Below variables need to be defined outside this file or via command line
+# - MOTOR_CONTROL_SDK_PATH
+# - PROFILE
+# - CG_TOOL_ROOT
+# - OUTNAME
+# - CCS_INSTALL_DIR
+# - CCS_IDE_MODE
+
+CCS_PATH=$(CCS_INSTALL_DIR)
+include ${MOTOR_CONTROL_SDK_PATH}/imports.mak
+include ${MOTOR_CONTROL_SDK_PATH}/devconfig/devconfig.mak
+
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+ PYTHON=python
+else
+ PYTHON=python3
+endif
+
+OUTFILE=$(PROFILE)/$(OUTNAME).out
+BOOTIMAGE_PATH=$(abspath ${PROFILE})
+BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
+BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
+BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+ BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+ BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+ $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+ $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+all:
+ifeq ($(CCS_IDE_MODE),cloud)
+# No post build steps
+else
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ...
+ $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
+ $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
+ifeq ($(DEVICE_TYPE),HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+ @echo Boot image signing: Encryption is disabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
+else
+ @echo Boot image signing: Encryption is enabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
+ $(RM) $(BOOTIMAGE_NAME)-enc
+endif
+endif
+ $(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
+ @echo .
+ifeq ($(DEVICE_TYPE),HS)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
+ @echo .
+else
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+ @echo .
+endif
+endif
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
new file mode 100644
index 0000000..cd7d2ce
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
@@ -0,0 +1,20 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang
+
+all:
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+ $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full
diff --git a/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
new file mode 100644
index 0000000..472ab38
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
@@ -0,0 +1,8 @@
+/*
+ * ======== syscfg_c.rov.xs ========
+ * This file contains the information needed by the Runtime Object
+ * View (ROV) tool.
+ */
+var crovFiles = [
+ "kernel/freertos/rov/FreeRTOS.rov.js",
+];
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/.project/project.js b/examples/position_sense/bissc_diagnostic/single_channel/.project/project.js
new file mode 100644
index 0000000..f6c2d16
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/.project/project.js
@@ -0,0 +1,14 @@
+function getComponentProperty(device)
+{
+ return require(`./project_${device}`).getComponentProperty();
+};
+
+function getComponentBuildProperty(buildOption)
+{
+ return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption);
+};
+
+module.exports = {
+ getComponentProperty,
+ getComponentBuildProperty,
+};
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/.project/project_am243x.js b/examples/position_sense/bissc_diagnostic/single_channel/.project/project_am243x.js
new file mode 100644
index 0000000..ec6b96e
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/.project/project_am243x.js
@@ -0,0 +1,124 @@
+let path = require('path');
+
+let device = "am243x";
+
+const files = {
+ common: [
+ "bissc_diagnostic.c",
+ "main.c",
+ ],
+};
+
+/* Relative to where the makefile will be generated
+ * Typically at ///
+ */
+const filedirs = {
+ common: [
+ "..", /* core_os_combo base */
+ "../../../..", /* Example base */
+ ],
+};
+
+const libdirs_freertos = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib",
+ ],
+};
+
+const includes_freertos_r5f = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f",
+ ],
+};
+
+const libs_freertos_r5f = {
+ common: [
+ "freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "board.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "motorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
+ ],
+};
+
+const defines_r5f = {
+ common: [
+ "SOC_AM243X",
+ ],
+};
+
+const lnkfiles = {
+ common: [
+ "linker.cmd",
+ ]
+};
+
+const syscfgfile = "../example.syscfg";
+
+const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_BISSC";
+
+const templates_freertos_r5f =
+[
+ {
+ input: ".project/templates/am243x/common/linker_r5f.cmd.xdt",
+ output: "linker.cmd",
+ },
+ {
+ input: ".project/templates/am243x/freertos/main_freertos.c.xdt",
+ output: "../main.c",
+ options: {
+ entryFunction: "bissc_main",
+ taskPri: 5,
+ },
+ }
+];
+
+const buildOptionCombos = [
+ { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-lp", os: "freertos"},
+
+];
+
+function getComponentProperty() {
+ let property = {};
+
+ property.dirPath = path.resolve(__dirname, "..");
+ property.type = "executable";
+ property.name = "bissc_diagnostic_single_channel";
+ property.isInternal = false;
+ property.buildOptionCombos = buildOptionCombos;
+ property.isSkipTopLevelBuild = false;
+
+ return property;
+}
+
+function getComponentBuildProperty(buildOption) {
+ let build_property = {};
+
+ build_property.files = files;
+ build_property.filedirs = filedirs;
+ build_property.lnkfiles = lnkfiles;
+ build_property.syscfgfile = syscfgfile;
+ build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
+
+ if(buildOption.cpu.match(/r5f*/)) {
+ if(buildOption.os.match(/freertos*/) )
+ {
+ build_property.includes = includes_freertos_r5f;
+ build_property.libdirs = libdirs_freertos;
+ build_property.libs = libs_freertos_r5f;
+ build_property.templates = templates_freertos_r5f;
+ build_property.defines = defines_r5f;
+ }
+ }
+
+ return build_property;
+}
+
+module.exports = {
+ getComponentProperty,
+ getComponentBuildProperty,
+};
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/.project/project_am64x.js b/examples/position_sense/bissc_diagnostic/single_channel/.project/project_am64x.js
new file mode 100644
index 0000000..d615a99
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/.project/project_am64x.js
@@ -0,0 +1,123 @@
+let path = require('path');
+
+let device = "am64x";
+
+const files = {
+ common: [
+ "bissc_diagnostic.c",
+ "main.c",
+ ],
+};
+
+/* Relative to where the makefile will be generated
+ * Typically at ///
+ */
+const filedirs = {
+ common: [
+ "..", /* core_os_combo base */
+ "../../../..", /* Example base */
+ ],
+};
+
+const libdirs_freertos = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib",
+ "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib",
+ ],
+};
+
+const includes_freertos_r5f = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F",
+ "${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am64x/r5f",
+ ],
+};
+
+const libs_freertos_r5f = {
+ common: [
+ "freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "board.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
+ "motorcontrol_bissc.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
+ ],
+};
+
+const defines_r5f = {
+ common: [
+ "SOC_AM64X",
+ ],
+};
+
+const lnkfiles = {
+ common: [
+ "linker.cmd",
+ ]
+};
+
+const syscfgfile = "../example.syscfg";
+
+const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_BISSC";
+
+const templates_freertos_r5f =
+[
+ {
+ input: ".project/templates/am64x/common/linker_r5f.cmd.xdt",
+ output: "linker.cmd",
+ },
+ {
+ input: ".project/templates/am64x/freertos/main_freertos.c.xdt",
+ output: "../main.c",
+ options: {
+ entryFunction: "bissc_main",
+ taskPri: 5,
+ },
+ }
+];
+
+const buildOptionCombos = [
+ { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"},
+];
+
+function getComponentProperty() {
+ let property = {};
+
+ property.dirPath = path.resolve(__dirname, "..");
+ property.type = "executable";
+ property.name = "bissc_diagnostic_single_channel";
+ property.isInternal = false;
+ property.buildOptionCombos = buildOptionCombos;
+ property.isSkipTopLevelBuild = false;
+
+ return property;
+}
+
+function getComponentBuildProperty(buildOption) {
+ let build_property = {};
+
+ build_property.files = files;
+ build_property.filedirs = filedirs;
+ build_property.lnkfiles = lnkfiles;
+ build_property.syscfgfile = syscfgfile;
+ build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
+
+ if(buildOption.cpu.match(/r5f*/)) {
+ if(buildOption.os.match(/freertos*/) )
+ {
+ build_property.includes = includes_freertos_r5f;
+ build_property.libdirs = libdirs_freertos;
+ build_property.libs = libs_freertos_r5f;
+ build_property.templates = templates_freertos_r5f;
+ build_property.defines = defines_r5f;
+ }
+ }
+
+ return build_property;
+}
+
+module.exports = {
+ getComponentProperty,
+ getComponentBuildProperty,
+};
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/example.syscfg b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/example.syscfg
new file mode 100644
index 0000000..2d7389b
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/example.syscfg
@@ -0,0 +1,76 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK_AM243X@09.01.00"
+ * @versions {"tool":"1.18.0+3266"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
+const pruicss1 = pruicss.addInstance();
+const debug_log = scripting.addModule("/kernel/dpl/debug_log");
+const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
+const mpu_armv71 = mpu_armv7.addInstance();
+const mpu_armv72 = mpu_armv7.addInstance();
+const mpu_armv73 = mpu_armv7.addInstance();
+const mpu_armv74 = mpu_armv7.addInstance();
+const mpu_armv75 = mpu_armv7.addInstance();
+const mpu_armv76 = mpu_armv7.addInstance();
+const bissc = scripting.addModule("/position_sense/bissc", {}, false);
+const bissc1 = bissc.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+debug_log.enableCssLog = false;
+debug_log.enableUartLog = true;
+debug_log.uartLog.$name = "CONFIG_UART0";
+
+mpu_armv71.$name = "CONFIG_MPU_REGION0";
+mpu_armv71.size = 31;
+mpu_armv71.attributes = "Device";
+mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv72.$name = "CONFIG_MPU_REGION1";
+mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv72.size = 15;
+
+mpu_armv73.$name = "CONFIG_MPU_REGION2";
+mpu_armv73.size = 15;
+mpu_armv73.baseAddr = 0x41010000;
+mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv74.$name = "CONFIG_MPU_REGION3";
+mpu_armv74.size = 21;
+mpu_armv74.baseAddr = 0x70000000;
+mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv75.$name = "CONFIG_MPU_REGION4";
+mpu_armv75.size = 28;
+mpu_armv75.baseAddr = 0x60000000;
+mpu_armv75.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv76.$name = "CONFIG_MPU_REGION5";
+mpu_armv76.size = 31;
+mpu_armv76.baseAddr = 0x80000000;
+
+bissc1.$name = "CONFIG_BISSC0";
+
+pruicss1.$name = "CONFIG_PRU_ICSS0";
+bissc1.pru = pruicss1;
+pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
+
+/**
+ * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
+ * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to
+ * re-solve from scratch.
+ */
+debug_log.uartLog.UART.$suggestSolution = "USART0";
+debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD";
+debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD";
+bissc1.PRU_ICSSG0_PRU.$suggestSolution = "PRU_ICSSG0_PRU1";
+bissc1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1";
+bissc1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0";
+bissc1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13";
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/main.c b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/main.c
new file mode 100644
index 0000000..de5e3bb
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/main.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include "ti_drivers_config.h"
+#include "ti_board_config.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define MAIN_TASK_PRI (5)
+
+#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE))
+StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
+
+StaticTask_t gMainTaskObj;
+TaskHandle_t gMainTask;
+
+void bissc_main(void *args);
+
+void freertos_main(void *args)
+{
+ bissc_main(NULL);
+
+ vTaskDelete(NULL);
+}
+
+
+int main(void)
+{
+ /* init SOC specific modules */
+ System_init();
+ Board_init();
+
+ /* This task is created at highest priority, it should create more tasks and then delete itself */
+ gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */
+ "freertos_main", /* Text name for the task. This is to facilitate debugging only. */
+ MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
+ NULL, /* We are not using the task parameter. */
+ MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
+ gMainTaskStack, /* pointer to stack base */
+ &gMainTaskObj ); /* pointer to statically allocated task object memory */
+ configASSERT(gMainTask != NULL);
+
+ /* Start the scheduler to start the tasks executing. */
+ vTaskStartScheduler();
+
+ /* The following line should never be reached because vTaskStartScheduler()
+ will only return if there was not enough FreeRTOS heap memory available to
+ create the Idle and (if configured) Timer tasks. Heap management, and
+ techniques for trapping heap exhaustion, are described in the book text. */
+ DebugP_assertNoLog(0);
+
+ return 0;
+}
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec
new file mode 100644
index 0000000..beab966
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@@ -0,0 +1,114 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
new file mode 100644
index 0000000..69640f4
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -0,0 +1,148 @@
+
+/* This is the stack that is used by code running within main()
+ * In case of NORTOS,
+ * - This means all the code outside of ISR uses this stack
+ * In case of FreeRTOS
+ * - This means all the code until vTaskStartScheduler() is called in main()
+ * uses this stack.
+ * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
+ */
+--stack_size=16384
+/* This is the heap size for malloc() API in NORTOS and FreeRTOS
+ * This is also the heap used by pvPortMalloc in FreeRTOS
+ */
+--heap_size=32768
+-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
+
+/* This is the size of stack when R5 is in IRQ mode
+ * In NORTOS,
+ * - Here interrupt nesting is enabled
+ * - This is the stack used by ISRs registered as type IRQ
+ * In FreeRTOS,
+ * - Here interrupt nesting is disabled
+ * - This is stack that is used initally when a IRQ is received
+ * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
+ * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
+ */
+__IRQ_STACK_SIZE = 256;
+/* This is the size of stack when R5 is in IRQ mode
+ * - In both NORTOS and FreeRTOS nesting is disabled for FIQ
+ */
+__FIQ_STACK_SIZE = 256;
+__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
+__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */
+__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */
+
+SECTIONS
+{
+ /* This has the R5F entry point and vector table, this MUST be at 0x0 */
+ .vectors:{} palign(8) > R5F_VECS
+
+ /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
+ * i.e this cannot be placed in DDR
+ */
+ GROUP {
+ .text.hwi: palign(8)
+ .text.cache: palign(8)
+ .text.mpu: palign(8)
+ .text.boot: palign(8)
+ .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
+ } > MSRAM
+
+ /* This is rest of code. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .text: {} palign(8) /* This is where code resides */
+ .rodata: {} palign(8) /* This is where const's go */
+ } > MSRAM
+
+ /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .data: {} palign(8) /* This is where initialized globals and static go */
+ } > MSRAM
+
+ /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .bss: {} palign(8) /* This is where uninitialized globals go */
+ RUN_START(__BSS_START)
+ RUN_END(__BSS_END)
+ .sysmem: {} palign(8) /* This is where the malloc heap goes */
+ .stack: {} palign(8) /* This is where the main() stack goes */
+ } > MSRAM
+
+ /* This is where the stacks for different R5F modes go */
+ GROUP {
+ .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+ .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
+ RUN_START(__UNDEFINED_STACK_START)
+ RUN_END(__UNDEFINED_STACK_END)
+ } > MSRAM
+
+ /* Sections needed for C++ projects */
+ GROUP {
+ .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
+ .init_array: {} palign(8) /* Contains function pointers called before main */
+ .fini_array: {} palign(8) /* Contains function pointers called after main */
+ } > MSRAM
+
+ /* General purpose user shared memory, used in some examples */
+ .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
+ /* this is used when Debug log's to shared memory are enabled, else this is not used */
+ .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
+ /* this is used only when IPC RPMessage is enabled, else this is not used */
+ .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
+ /* General purpose non cacheable memory, used in some examples */
+ .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
+}
+
+/*
+NOTE: Below memory is reserved for DMSC usage
+ - During Boot till security handoff is complete
+ 0x701E0000 - 0x701FFFFF (128KB)
+ - After "Security Handoff" is complete (i.e at run time)
+ 0x701F4000 - 0x701FFFFF (48KB)
+
+ Security handoff is complete when this message is sent to the DMSC,
+ TISCI_MSG_SEC_HANDOVER
+
+ This should be sent once all cores are loaded and all application
+ specific firewall calls are setup.
+*/
+
+MEMORY
+{
+ R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
+ R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
+ R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+
+ /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
+ NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
+
+ /* when using multi-core application's i.e more than one R5F/M4F active, make sure
+ * this memory does not overlap with other R5F's
+ */
+ MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000
+
+ /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
+ * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
+ */
+ FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000
+
+ /* shared memory segments */
+ /* On R5F,
+ * - make sure there is a MPU entry which maps below regions as non-cache
+ */
+ USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180
+ LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180
+ RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
+}
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile
new file mode 100644
index 0000000..eac23e4
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile
@@ -0,0 +1,308 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak
+
+CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
+
+CC=$(CG_TOOL_ROOT)/bin/tiarmclang
+LNK=$(CG_TOOL_ROOT)/bin/tiarmclang
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+ PYTHON=python
+else
+ PYTHON=python3
+endif
+
+PROFILE?=release
+ConfigName:=$(PROFILE)
+
+OUTNAME:=bissc_diagnostic_single_channel.$(PROFILE).out
+
+BOOTIMAGE_PATH=$(abspath .)
+BOOTIMAGE_NAME:=bissc_diagnostic_single_channel.$(PROFILE).appimage
+BOOTIMAGE_NAME_XIP:=bissc_diagnostic_single_channel.$(PROFILE).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=bissc_diagnostic_single_channel.$(PROFILE).appimage.signed
+BOOTIMAGE_RPRC_NAME:=bissc_diagnostic_single_channel.$(PROFILE).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=bissc_diagnostic_single_channel.$(PROFILE).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=bissc_diagnostic_single_channel.$(PROFILE).rprc_tmp
+BOOTIMAGE_NAME_HS:=bissc_diagnostic_single_channel.$(PROFILE).appimage.hs
+BOOTIMAGE_NAME_HS_FS:=bissc_diagnostic_single_channel.$(PROFILE).appimage.hs_fs
+TARGETS := $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+ TARGETS += $(BOOTIMAGE_NAME_HS)
+endif
+
+FILES_common := \
+ bissc_diagnostic.c \
+ main.c \
+ ti_drivers_config.c \
+ ti_drivers_open_close.c \
+ ti_board_config.c \
+ ti_board_open_close.c \
+ ti_dpl_config.c \
+ ti_pinmux_config.c \
+ ti_power_clock_config.c \
+
+FILES_PATH_common = \
+ .. \
+ ../../../.. \
+ generated \
+
+INCLUDES_common := \
+ -I${CG_TOOL_ROOT}/include/c \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source \
+ -I${MOTOR_CONTROL_SDK_PATH}/source \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \
+ -Igenerated \
+
+DEFINES_common := \
+ -DSOC_AM243X \
+ -DSOC_AM243X \
+
+CFLAGS_common := \
+ -mcpu=cortex-r5 \
+ -mfloat-abi=hard \
+ -mfpu=vfpv3-d16 \
+ -mthumb \
+ -Wall \
+ -Werror \
+ -g \
+ -Wno-gnu-variable-sized-type-not-at-end \
+ -Wno-unused-function \
+
+CFLAGS_cpp_common := \
+ -Wno-c99-designator \
+ -Wno-extern-c-compat \
+ -Wno-c++11-narrowing \
+ -Wno-reorder-init-list \
+ -Wno-deprecated-register \
+ -Wno-writable-strings \
+ -Wno-enum-compare \
+ -Wno-reserved-user-defined-literal \
+ -Wno-unused-const-variable \
+ -x c++ \
+
+CFLAGS_debug := \
+ -D_DEBUG_=1 \
+
+CFLAGS_release := \
+ -Os \
+
+LNK_FILES_common = \
+ linker.cmd \
+
+LIBS_PATH_common = \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib \
+ -Wl,-i${CG_TOOL_ROOT}/lib \
+
+LIBS_common = \
+ -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -lmotorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -llibc.a \
+ -llibsysbm.a \
+
+LFLAGS_common = \
+ -Wl,--diag_suppress=10063 \
+ -Wl,--ram_model \
+ -Wl,--reread_libs \
+
+
+LIBS_NAME = \
+ freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ motorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ libc.a \
+ libsysbm.a \
+
+LIBS_PATH_NAME = \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib \
+ ${CG_TOOL_ROOT}/lib \
+
+FILES := $(FILES_common) $(FILES_$(PROFILE))
+ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
+FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
+CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
+INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
+LIBS := $(LIBS_common) $(LIBS_$(PROFILE))
+LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE))
+LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE))
+LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE))
+LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE))
+
+OBJDIR := obj/$(PROFILE)/
+OBJS := $(FILES:%.c=%.obj)
+OBJS += $(ASMFILES:%.S=%.obj)
+DEPS := $(FILES:%.c=%.d)
+
+vpath %.obj $(OBJDIR)
+vpath %.c $(FILES_PATH)
+vpath %.S $(FILES_PATH)
+vpath %.lib $(LIBS_PATH_NAME)
+vpath %.a $(LIBS_PATH_NAME)
+
+$(OBJDIR)/%.obj %.obj: %.c
+ @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $<
+ $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.S
+ @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $<
+ $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
+
+all: $(TARGETS)
+
+SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h
+SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h
+SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h
+SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c
+SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h
+SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h
+
+$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME)
+ @echo .
+ @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ...
+ $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES)
+ @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
+ @echo .
+
+clean:
+ @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
+ $(RMDIR) $(OBJDIR)
+ $(RM) $(OUTNAME)
+ $(RM) $(BOOTIMAGE_NAME)
+ $(RM) $(BOOTIMAGE_NAME_XIP)
+ $(RM) $(BOOTIMAGE_NAME_SIGNED)
+ $(RM) $(BOOTIMAGE_NAME_HS)
+ $(RM) $(BOOTIMAGE_NAME_HS_FS)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+ $(RMDIR) generated/
+
+scrub:
+ @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang bissc_diagnostic_single_channel ...
+ $(RMDIR) obj
+ifeq ($(OS),Windows_NT)
+ $(RM) \*.out
+ $(RM) \*.map
+ $(RM) \*.appimage*
+ $(RM) \*.rprc*
+ $(RM) \*.tiimage*
+ $(RM) \*.bin
+else
+ $(RM) *.out
+ $(RM) *.map
+ $(RM) *.appimage*
+ $(RM) *.rprc*
+ $(RM) *.tiimage*
+ $(RM) *.bin
+endif
+ $(RMDIR) generated
+
+$(OBJS): | $(OBJDIR)
+
+$(OBJDIR):
+ $(MKDIR) $@
+
+
+.NOTPARALLEL:
+
+.INTERMEDIATE: syscfg
+$(SYSCFG_GEN_FILES): syscfg
+
+syscfg: ../example.syscfg
+ @echo Generating SysConfig files ...
+ $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg
+
+syscfg-gui:
+ $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALV_beta --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+ BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+ BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+ $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+ $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+$(BOOTIMAGE_NAME): $(OUTNAME)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
+ifneq ($(OS),Windows_NT)
+ $(CHMOD) a+x $(XIPGEN_CMD)
+endif
+ $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
+ $(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!!
+ @echo .
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+ @echo .
+
+$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+ @echo Boot image signing: Encryption is disabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+else
+ @echo Boot image signing: Encryption is enabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
+ $(RM) $(BOOTIMAGE_NAME)-enc
+endif
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
+ @echo .
+endif
+-include $(addprefix $(OBJDIR)/, $(DEPS))
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
new file mode 100644
index 0000000..8666cfd
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@@ -0,0 +1,106 @@
+#
+# Auto generated makefile
+#
+
+# Below variables need to be defined outside this file or via command line
+# - MOTOR_CONTROL_SDK_PATH
+# - PROFILE
+# - CG_TOOL_ROOT
+# - OUTNAME
+# - CCS_INSTALL_DIR
+# - CCS_IDE_MODE
+
+CCS_PATH=$(CCS_INSTALL_DIR)
+include ${MOTOR_CONTROL_SDK_PATH}/imports.mak
+include ${MOTOR_CONTROL_SDK_PATH}/devconfig/devconfig.mak
+
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+ PYTHON=python
+else
+ PYTHON=python3
+endif
+
+OUTFILE=$(PROFILE)/$(OUTNAME).out
+BOOTIMAGE_PATH=$(abspath ${PROFILE})
+BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
+BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
+BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+ BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+ BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+ $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+ $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+all:
+ifeq ($(CCS_IDE_MODE),cloud)
+# No post build steps
+else
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ...
+ $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
+ $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
+ifeq ($(DEVICE_TYPE),HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+ @echo Boot image signing: Encryption is disabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
+else
+ @echo Boot image signing: Encryption is enabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
+ $(RM) $(BOOTIMAGE_NAME)-enc
+endif
+endif
+ $(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
+ @echo .
+ifeq ($(DEVICE_TYPE),HS)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
+ @echo .
+else
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+ @echo .
+endif
+endif
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
new file mode 100644
index 0000000..c62927a
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
@@ -0,0 +1,20 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=bissc_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang
+
+all:
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+ $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
new file mode 100644
index 0000000..472ab38
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
@@ -0,0 +1,8 @@
+/*
+ * ======== syscfg_c.rov.xs ========
+ * This file contains the information needed by the Runtime Object
+ * View (ROV) tool.
+ */
+var crovFiles = [
+ "kernel/freertos/rov/FreeRTOS.rov.js",
+];
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/example.syscfg b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/example.syscfg
new file mode 100644
index 0000000..1387048
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/example.syscfg
@@ -0,0 +1,124 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM243x_ALX_beta" --package "ALX" --part "ALX" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK@09.01.00"
+ * @versions {"tool":"1.18.0+3266"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false);
+const gpio1 = gpio.addInstance();
+const gpio2 = gpio.addInstance();
+const gpio3 = gpio.addInstance();
+const gpio4 = gpio.addInstance();
+const gpio5 = gpio.addInstance();
+const gpio6 = gpio.addInstance();
+const debug_log = scripting.addModule("/kernel/dpl/debug_log");
+const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
+const mpu_armv71 = mpu_armv7.addInstance();
+const mpu_armv72 = mpu_armv7.addInstance();
+const mpu_armv73 = mpu_armv7.addInstance();
+const mpu_armv74 = mpu_armv7.addInstance();
+const mpu_armv75 = mpu_armv7.addInstance();
+const bissc = scripting.addModule("/position_sense/bissc", {}, false);
+const bissc1 = bissc.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+debug_log.enableUartLog = true;
+debug_log.enableCssLog = false;
+debug_log.uartLog.$name = "CONFIG_UART_CONSOLE";
+debug_log.uartLog.UART.$assign = "USART0";
+
+mpu_armv71.$name = "CONFIG_MPU_REGION0";
+mpu_armv71.size = 31;
+mpu_armv71.attributes = "Device";
+mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv71.allowExecute = false;
+
+mpu_armv72.$name = "CONFIG_MPU_REGION1";
+mpu_armv72.size = 15;
+mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv73.$name = "CONFIG_MPU_REGION2";
+mpu_armv73.baseAddr = 0x41010000;
+mpu_armv73.size = 15;
+mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv74.$name = "CONFIG_MPU_REGION3";
+mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv74.baseAddr = 0x70000000;
+mpu_armv74.size = 21;
+
+mpu_armv75.$name = "CONFIG_MPU_REGION4";
+mpu_armv75.baseAddr = 0x60000000;
+mpu_armv75.size = 28;
+mpu_armv75.accessPermissions = "Supervisor RD, User RD";
+
+bissc1.$name = "CONFIG_BISSC0";
+bissc1.Booster_Pack = true;
+bissc1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1";
+bissc1.PRU_ICSSG0_PRU.GPO4.$used = false;
+bissc1.PRU_ICSSG0_PRU.GPO3.$used = false;
+bissc1.PRU_ICSSG0_PRU.GPI14.$used = false;
+
+bissc1.ENC1_EN = gpio1;
+gpio1.$name = "ENC1_EN";
+gpio1.GPIO.$assign = "GPIO1";
+gpio1.GPIO.gpioPin.pu_pd = "pu";
+gpio1.GPIO.gpioPin.rx = false;
+
+bissc1.BISSC_CH0_OUT_EN = gpio2;
+gpio2.$name = "BISSC_CH0_OUT_EN";
+gpio2.GPIO.gpioPin.rx = false;
+gpio2.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO2";
+
+bissc1.BISSC_CH2_OUT_EN = gpio3;
+gpio3.$name = "BISSC_CH2_OUT_EN";
+gpio3.GPIO.gpioPin.rx = false;
+gpio3.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO8";
+
+bissc1.ENC2_EN = gpio4;
+gpio4.$name = "ENC2_EN";
+gpio4.GPIO.gpioPin.pu_pd = "pu";
+gpio4.GPIO.gpioPin.rx = false;
+gpio4.GPIO.gpioPin.$assign = "MMC1_SDCD";
+
+bissc1.BISSC_CH1_OUT_EN = gpio5;
+gpio5.$name = "BISSC_CH1_OUT_EN";
+gpio5.GPIO.gpioPin.rx = false;
+gpio5.GPIO.gpioPin.$assign = "PRG0_PRU1_GPO5";
+
+gpio6.$name = "ENC0_EN";
+gpio6.pinDir = "OUTPUT";
+bissc1.ENC0_EN = gpio6;
+gpio6.GPIO.gpioPin.$assign = "MMC1_SDWP";
+
+const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
+const pruicss1 = pruicss.addInstance({}, false);
+pruicss1.$name = "CONFIG_PRU_ICSS0";
+bissc1.pru = pruicss1;
+pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
+
+/**
+ * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
+ * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to
+ * re-solve from scratch.
+ */
+debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD";
+debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD";
+bissc1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1";
+bissc1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0";
+bissc1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13";
+bissc1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12";
+bissc1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6";
+bissc1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11";
+gpio1.GPIO.gpioPin.$suggestSolution = "PRG0_PRU0_GPO0";
+gpio2.GPIO.$suggestSolution = "GPIO1";
+gpio3.GPIO.$suggestSolution = "GPIO1";
+gpio4.GPIO.$suggestSolution = "GPIO1";
+gpio5.GPIO.$suggestSolution = "GPIO1";
+gpio6.GPIO.$suggestSolution = "GPIO1";
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/main.c b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/main.c
new file mode 100644
index 0000000..de5e3bb
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/main.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include "ti_drivers_config.h"
+#include "ti_board_config.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define MAIN_TASK_PRI (5)
+
+#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE))
+StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
+
+StaticTask_t gMainTaskObj;
+TaskHandle_t gMainTask;
+
+void bissc_main(void *args);
+
+void freertos_main(void *args)
+{
+ bissc_main(NULL);
+
+ vTaskDelete(NULL);
+}
+
+
+int main(void)
+{
+ /* init SOC specific modules */
+ System_init();
+ Board_init();
+
+ /* This task is created at highest priority, it should create more tasks and then delete itself */
+ gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */
+ "freertos_main", /* Text name for the task. This is to facilitate debugging only. */
+ MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
+ NULL, /* We are not using the task parameter. */
+ MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
+ gMainTaskStack, /* pointer to stack base */
+ &gMainTaskObj ); /* pointer to statically allocated task object memory */
+ configASSERT(gMainTask != NULL);
+
+ /* Start the scheduler to start the tasks executing. */
+ vTaskStartScheduler();
+
+ /* The following line should never be reached because vTaskStartScheduler()
+ will only return if there was not enough FreeRTOS heap memory available to
+ create the Idle and (if configured) Timer tasks. Heap management, and
+ techniques for trapping heap exhaustion, are described in the book text. */
+ DebugP_assertNoLog(0);
+
+ return 0;
+}
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
new file mode 100644
index 0000000..a8181e1
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec
@@ -0,0 +1,114 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
new file mode 100644
index 0000000..69640f4
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -0,0 +1,148 @@
+
+/* This is the stack that is used by code running within main()
+ * In case of NORTOS,
+ * - This means all the code outside of ISR uses this stack
+ * In case of FreeRTOS
+ * - This means all the code until vTaskStartScheduler() is called in main()
+ * uses this stack.
+ * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
+ */
+--stack_size=16384
+/* This is the heap size for malloc() API in NORTOS and FreeRTOS
+ * This is also the heap used by pvPortMalloc in FreeRTOS
+ */
+--heap_size=32768
+-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
+
+/* This is the size of stack when R5 is in IRQ mode
+ * In NORTOS,
+ * - Here interrupt nesting is enabled
+ * - This is the stack used by ISRs registered as type IRQ
+ * In FreeRTOS,
+ * - Here interrupt nesting is disabled
+ * - This is stack that is used initally when a IRQ is received
+ * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
+ * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
+ */
+__IRQ_STACK_SIZE = 256;
+/* This is the size of stack when R5 is in IRQ mode
+ * - In both NORTOS and FreeRTOS nesting is disabled for FIQ
+ */
+__FIQ_STACK_SIZE = 256;
+__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
+__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */
+__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */
+
+SECTIONS
+{
+ /* This has the R5F entry point and vector table, this MUST be at 0x0 */
+ .vectors:{} palign(8) > R5F_VECS
+
+ /* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
+ * i.e this cannot be placed in DDR
+ */
+ GROUP {
+ .text.hwi: palign(8)
+ .text.cache: palign(8)
+ .text.mpu: palign(8)
+ .text.boot: palign(8)
+ .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
+ } > MSRAM
+
+ /* This is rest of code. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .text: {} palign(8) /* This is where code resides */
+ .rodata: {} palign(8) /* This is where const's go */
+ } > MSRAM
+
+ /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .data: {} palign(8) /* This is where initialized globals and static go */
+ } > MSRAM
+
+ /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
+ GROUP {
+ .bss: {} palign(8) /* This is where uninitialized globals go */
+ RUN_START(__BSS_START)
+ RUN_END(__BSS_END)
+ .sysmem: {} palign(8) /* This is where the malloc heap goes */
+ .stack: {} palign(8) /* This is where the main() stack goes */
+ } > MSRAM
+
+ /* This is where the stacks for different R5F modes go */
+ GROUP {
+ .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+ .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
+ RUN_START(__UNDEFINED_STACK_START)
+ RUN_END(__UNDEFINED_STACK_END)
+ } > MSRAM
+
+ /* Sections needed for C++ projects */
+ GROUP {
+ .ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
+ .init_array: {} palign(8) /* Contains function pointers called before main */
+ .fini_array: {} palign(8) /* Contains function pointers called after main */
+ } > MSRAM
+
+ /* General purpose user shared memory, used in some examples */
+ .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
+ /* this is used when Debug log's to shared memory are enabled, else this is not used */
+ .bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
+ /* this is used only when IPC RPMessage is enabled, else this is not used */
+ .bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
+ /* General purpose non cacheable memory, used in some examples */
+ .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
+}
+
+/*
+NOTE: Below memory is reserved for DMSC usage
+ - During Boot till security handoff is complete
+ 0x701E0000 - 0x701FFFFF (128KB)
+ - After "Security Handoff" is complete (i.e at run time)
+ 0x701F4000 - 0x701FFFFF (48KB)
+
+ Security handoff is complete when this message is sent to the DMSC,
+ TISCI_MSG_SEC_HANDOVER
+
+ This should be sent once all cores are loaded and all application
+ specific firewall calls are setup.
+*/
+
+MEMORY
+{
+ R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
+ R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
+ R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+
+ /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
+ NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
+
+ /* when using multi-core application's i.e more than one R5F/M4F active, make sure
+ * this memory does not overlap with other R5F's
+ */
+ MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x40000
+
+ /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
+ * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
+ */
+ FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000
+
+ /* shared memory segments */
+ /* On R5F,
+ * - make sure there is a MPU entry which maps below regions as non-cache
+ */
+ USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x180
+ LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x180, LENGTH = 0x00004000 - 0x180
+ RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
+}
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
new file mode 100644
index 0000000..ab46074
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile
@@ -0,0 +1,308 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak
+
+CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
+
+CC=$(CG_TOOL_ROOT)/bin/tiarmclang
+LNK=$(CG_TOOL_ROOT)/bin/tiarmclang
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+ PYTHON=python
+else
+ PYTHON=python3
+endif
+
+PROFILE?=release
+ConfigName:=$(PROFILE)
+
+OUTNAME:=bissc_diagnostic_single_channel.$(PROFILE).out
+
+BOOTIMAGE_PATH=$(abspath .)
+BOOTIMAGE_NAME:=bissc_diagnostic_single_channel.$(PROFILE).appimage
+BOOTIMAGE_NAME_XIP:=bissc_diagnostic_single_channel.$(PROFILE).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=bissc_diagnostic_single_channel.$(PROFILE).appimage.signed
+BOOTIMAGE_RPRC_NAME:=bissc_diagnostic_single_channel.$(PROFILE).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=bissc_diagnostic_single_channel.$(PROFILE).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=bissc_diagnostic_single_channel.$(PROFILE).rprc_tmp
+BOOTIMAGE_NAME_HS:=bissc_diagnostic_single_channel.$(PROFILE).appimage.hs
+BOOTIMAGE_NAME_HS_FS:=bissc_diagnostic_single_channel.$(PROFILE).appimage.hs_fs
+TARGETS := $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+ TARGETS += $(BOOTIMAGE_NAME_HS)
+endif
+
+FILES_common := \
+ bissc_diagnostic.c \
+ main.c \
+ ti_drivers_config.c \
+ ti_drivers_open_close.c \
+ ti_board_config.c \
+ ti_board_open_close.c \
+ ti_dpl_config.c \
+ ti_pinmux_config.c \
+ ti_power_clock_config.c \
+
+FILES_PATH_common = \
+ .. \
+ ../../../.. \
+ generated \
+
+INCLUDES_common := \
+ -I${CG_TOOL_ROOT}/include/c \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source \
+ -I${MOTOR_CONTROL_SDK_PATH}/source \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \
+ -Igenerated \
+
+DEFINES_common := \
+ -DSOC_AM243X \
+ -DSOC_AM243X \
+
+CFLAGS_common := \
+ -mcpu=cortex-r5 \
+ -mfloat-abi=hard \
+ -mfpu=vfpv3-d16 \
+ -mthumb \
+ -Wall \
+ -Werror \
+ -g \
+ -Wno-gnu-variable-sized-type-not-at-end \
+ -Wno-unused-function \
+
+CFLAGS_cpp_common := \
+ -Wno-c99-designator \
+ -Wno-extern-c-compat \
+ -Wno-c++11-narrowing \
+ -Wno-reorder-init-list \
+ -Wno-deprecated-register \
+ -Wno-writable-strings \
+ -Wno-enum-compare \
+ -Wno-reserved-user-defined-literal \
+ -Wno-unused-const-variable \
+ -x c++ \
+
+CFLAGS_debug := \
+ -D_DEBUG_=1 \
+
+CFLAGS_release := \
+ -Os \
+
+LNK_FILES_common = \
+ linker.cmd \
+
+LIBS_PATH_common = \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+ -Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib \
+ -Wl,-i${CG_TOOL_ROOT}/lib \
+
+LIBS_common = \
+ -lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -lmotorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ -llibc.a \
+ -llibsysbm.a \
+
+LFLAGS_common = \
+ -Wl,--diag_suppress=10063 \
+ -Wl,--ram_model \
+ -Wl,--reread_libs \
+
+
+LIBS_NAME = \
+ freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ motorcontrol_bissc.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+ libc.a \
+ libsysbm.a \
+
+LIBS_PATH_NAME = \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+ ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/lib \
+ ${CG_TOOL_ROOT}/lib \
+
+FILES := $(FILES_common) $(FILES_$(PROFILE))
+ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
+FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
+CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
+INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
+LIBS := $(LIBS_common) $(LIBS_$(PROFILE))
+LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE))
+LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE))
+LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE))
+LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE))
+
+OBJDIR := obj/$(PROFILE)/
+OBJS := $(FILES:%.c=%.obj)
+OBJS += $(ASMFILES:%.S=%.obj)
+DEPS := $(FILES:%.c=%.d)
+
+vpath %.obj $(OBJDIR)
+vpath %.c $(FILES_PATH)
+vpath %.S $(FILES_PATH)
+vpath %.lib $(LIBS_PATH_NAME)
+vpath %.a $(LIBS_PATH_NAME)
+
+$(OBJDIR)/%.obj %.obj: %.c
+ @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $<
+ $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.S
+ @echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $<
+ $(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
+
+all: $(TARGETS)
+
+SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h
+SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h
+SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h
+SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c
+SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h
+SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h
+
+$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME)
+ @echo .
+ @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ...
+ $(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES)
+ @echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
+ @echo .
+
+clean:
+ @echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
+ $(RMDIR) $(OBJDIR)
+ $(RM) $(OUTNAME)
+ $(RM) $(BOOTIMAGE_NAME)
+ $(RM) $(BOOTIMAGE_NAME_XIP)
+ $(RM) $(BOOTIMAGE_NAME_SIGNED)
+ $(RM) $(BOOTIMAGE_NAME_HS)
+ $(RM) $(BOOTIMAGE_NAME_HS_FS)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+ $(RMDIR) generated/
+
+scrub:
+ @echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang bissc_diagnostic_single_channel ...
+ $(RMDIR) obj
+ifeq ($(OS),Windows_NT)
+ $(RM) \*.out
+ $(RM) \*.map
+ $(RM) \*.appimage*
+ $(RM) \*.rprc*
+ $(RM) \*.tiimage*
+ $(RM) \*.bin
+else
+ $(RM) *.out
+ $(RM) *.map
+ $(RM) *.appimage*
+ $(RM) *.rprc*
+ $(RM) *.tiimage*
+ $(RM) *.bin
+endif
+ $(RMDIR) generated
+
+$(OBJS): | $(OBJDIR)
+
+$(OBJDIR):
+ $(MKDIR) $@
+
+
+.NOTPARALLEL:
+
+.INTERMEDIATE: syscfg
+$(SYSCFG_GEN_FILES): syscfg
+
+syscfg: ../example.syscfg
+ @echo Generating SysConfig files ...
+ $(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg
+
+syscfg-gui:
+ $(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALX_beta --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+ BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+ BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+ $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+ $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+$(BOOTIMAGE_NAME): $(OUTNAME)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
+ifneq ($(OS),Windows_NT)
+ $(CHMOD) a+x $(XIPGEN_CMD)
+endif
+ $(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
+ $(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!!
+ @echo .
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+ @echo .
+
+$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+ @echo Boot image signing: Encryption is disabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+else
+ @echo Boot image signing: Encryption is enabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
+ $(RM) $(BOOTIMAGE_NAME)-enc
+endif
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
+ @echo .
+endif
+-include $(addprefix $(OBJDIR)/, $(DEPS))
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
new file mode 100644
index 0000000..8666cfd
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
@@ -0,0 +1,106 @@
+#
+# Auto generated makefile
+#
+
+# Below variables need to be defined outside this file or via command line
+# - MOTOR_CONTROL_SDK_PATH
+# - PROFILE
+# - CG_TOOL_ROOT
+# - OUTNAME
+# - CCS_INSTALL_DIR
+# - CCS_IDE_MODE
+
+CCS_PATH=$(CCS_INSTALL_DIR)
+include ${MOTOR_CONTROL_SDK_PATH}/imports.mak
+include ${MOTOR_CONTROL_SDK_PATH}/devconfig/devconfig.mak
+
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+ PYTHON=python
+else
+ PYTHON=python3
+endif
+
+OUTFILE=$(PROFILE)/$(OUTNAME).out
+BOOTIMAGE_PATH=$(abspath ${PROFILE})
+BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
+BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
+BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+ BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+ BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+ XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+ $(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+ $(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+all:
+ifeq ($(CCS_IDE_MODE),cloud)
+# No post build steps
+else
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ...
+ $(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
+ $(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+ $(RM) $(BOOTIMAGE_RPRC_NAME)
+ $(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+ $(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
+ifeq ($(DEVICE_TYPE),HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+ @echo Boot image signing: Encryption is disabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
+else
+ @echo Boot image signing: Encryption is enabled.
+ $(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
+ $(RM) $(BOOTIMAGE_NAME)-enc
+endif
+endif
+ $(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
+ @echo .
+ifeq ($(DEVICE_TYPE),HS)
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
+ @echo .
+else
+ @echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+ @echo .
+endif
+endif
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
new file mode 100644
index 0000000..1c5f4f2
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
@@ -0,0 +1,20 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=bissc_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang
+
+all:
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+ $(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
+ $(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full
diff --git a/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
new file mode 100644
index 0000000..472ab38
--- /dev/null
+++ b/examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
@@ -0,0 +1,8 @@
+/*
+ * ======== syscfg_c.rov.xs ========
+ * This file contains the information needed by the Runtime Object
+ * View (ROV) tool.
+ */
+var crovFiles = [
+ "kernel/freertos/rov/FreeRTOS.rov.js",
+];
diff --git a/examples/position_sense/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index 68996ec..69640f4 100644
--- a/examples/position_sense/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/position_sense/endat_diagnostic/multi_channel_load_share/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -103,9 +103,6 @@ SECTIONS
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
-
- /* TCM used by ICSS PRU to write endat channel Info */
- .gEnDatChInfo : {} align(4) > R5F_TCMB0
}
/*
diff --git a/examples/position_sense/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index 8bf6d08..c4848c3 100644
--- a/examples/position_sense/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/position_sense/endat_diagnostic/multi_channel_load_share/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -103,10 +103,6 @@ SECTIONS
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
-
- /* TCM used by ICSS PRU to write endat channel Info */
- .gEnDatChInfo : {} align(4) > R5F_TCMB0
-
}
/*
@@ -150,5 +146,3 @@ MEMORY
LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
}
-
-
diff --git a/examples/position_sense/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index 68996ec..69640f4 100644
--- a/examples/position_sense/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/position_sense/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -103,9 +103,6 @@ SECTIONS
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
-
- /* TCM used by ICSS PRU to write endat channel Info */
- .gEnDatChInfo : {} align(4) > R5F_TCMB0
}
/*
diff --git a/examples/position_sense/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index 47c06e6..c4848c3 100644
--- a/examples/position_sense/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/position_sense/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -103,9 +103,6 @@ SECTIONS
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
-
- /* TCM used by ICSS PRU to write endat channel Info */
- .gEnDatChInfo : {} align(4) > R5F_TCMB0
}
/*
@@ -127,7 +124,7 @@ MEMORY
R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
-
+
/* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
diff --git a/examples/position_sense/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index 68996ec..69640f4 100644
--- a/examples/position_sense/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/position_sense/endat_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -103,9 +103,6 @@ SECTIONS
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
-
- /* TCM used by ICSS PRU to write endat channel Info */
- .gEnDatChInfo : {} align(4) > R5F_TCMB0
}
/*
diff --git a/examples/position_sense/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index 886a65d..69640f4 100644
--- a/examples/position_sense/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/position_sense/endat_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -103,9 +103,6 @@ SECTIONS
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
-
- /* TCM used by ICSS PRU to write endat channel Info */
- .gEnDatChInfo : {} align(4) > R5F_TCMB0
}
/*
@@ -127,7 +124,6 @@ MEMORY
R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
-
/* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
diff --git a/examples/position_sense/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd b/examples/position_sense/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
index 9b6e533..c4848c3 100644
--- a/examples/position_sense/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
+++ b/examples/position_sense/endat_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
@@ -103,9 +103,6 @@ SECTIONS
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
-
- /* TCM used by ICSS PRU to write endat channel Info */
- .gEnDatChInfo : {} align(4) > R5F_TCMB0
}
/*
@@ -127,7 +124,6 @@ MEMORY
R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
-
/* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
diff --git a/makefile.am243x b/makefile.am243x
index 6fbaa5d..b82783e 100644
--- a/makefile.am243x
+++ b/makefile.am243x
@@ -36,6 +36,7 @@ help:
@echo $(MAKE) -s -f makefile.am243x motorcontrol_endat_r5f.ti-arm-clang
@echo $(MAKE) -s -f makefile.am243x motorcontrol_hdsl_r5f.ti-arm-clang
@echo $(MAKE) -s -f makefile.am243x motorcontrol_tamagawa_r5f.ti-arm-clang
+ @echo $(MAKE) -s -f makefile.am243x motorcontrol_bissc_r5f.ti-arm-clang
@echo .
@echo Library clean targets,
@echo ======================
@@ -43,6 +44,7 @@ help:
@echo $(MAKE) -s -f makefile.am243x motorcontrol_endat_r5f.ti-arm-clang_clean
@echo $(MAKE) -s -f makefile.am243x motorcontrol_hdsl_r5f.ti-arm-clang_clean
@echo $(MAKE) -s -f makefile.am243x motorcontrol_tamagawa_r5f.ti-arm-clang_clean
+ @echo $(MAKE) -s -f makefile.am243x motorcontrol_bissc_r5f.ti-arm-clang_clean
@echo .
@echo Example build targets,
@echo ======================
@@ -64,6 +66,9 @@ help:
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
+ @echo $(MAKE) -s -C examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
+ @echo $(MAKE) -s -C examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
+ @echo $(MAKE) -s -C examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
@@ -81,6 +86,11 @@ help:
@echo $(MAKE) -s -C source/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C source/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C source/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
+ @echo $(MAKE) -s -C source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
+ @echo $(MAKE) -s -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
+ @echo $(MAKE) -s -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
+ @echo $(MAKE) -s -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
+ @echo $(MAKE) -s -C source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
@echo .
@echo System Example build targets,
@echo =============================
@@ -91,9 +101,10 @@ BUILD_COMBO_motorcontrol_sdfm = motorcontrol_sdfm_r5f.ti-arm-clang
BUILD_COMBO_motorcontrol_endat = motorcontrol_endat_r5f.ti-arm-clang
BUILD_COMBO_motorcontrol_hdsl = motorcontrol_hdsl_r5f.ti-arm-clang
BUILD_COMBO_motorcontrol_tamagawa = motorcontrol_tamagawa_r5f.ti-arm-clang
+BUILD_COMBO_motorcontrol_bissc = motorcontrol_bissc_r5f.ti-arm-clang
# Combine all Components
-BUILD_COMBO_ALL = $(BUILD_COMBO_motorcontrol_sdfm) $(BUILD_COMBO_motorcontrol_endat) $(BUILD_COMBO_motorcontrol_hdsl) $(BUILD_COMBO_motorcontrol_tamagawa)
+BUILD_COMBO_ALL = $(BUILD_COMBO_motorcontrol_sdfm) $(BUILD_COMBO_motorcontrol_endat) $(BUILD_COMBO_motorcontrol_hdsl) $(BUILD_COMBO_motorcontrol_tamagawa) $(BUILD_COMBO_motorcontrol_bissc)
# Combine all Pre-built Components
BUILD_COMBO_PREBUILT_ALL =
@@ -119,15 +130,19 @@ $(BUILD_COMBO_motorcontrol_hdsl):
$(BUILD_COMBO_motorcontrol_tamagawa):
$(MAKE) -C source/position_sense/tamagawa -f makefile.am243x.$(subst motorcontrol_tamagawa_,,$@) all
+$(BUILD_COMBO_motorcontrol_bissc):
+ $(MAKE) -C source/position_sense/bissc -f makefile.am243x.$(subst motorcontrol_bissc_,,$@) all
+
# Various Component Clean Targets
BUILD_COMBO_CLEAN_motorcontrol_sdfm = motorcontrol_sdfm_r5f.ti-arm-clang_clean
BUILD_COMBO_CLEAN_motorcontrol_endat = motorcontrol_endat_r5f.ti-arm-clang_clean
BUILD_COMBO_CLEAN_motorcontrol_hdsl = motorcontrol_hdsl_r5f.ti-arm-clang_clean
BUILD_COMBO_CLEAN_motorcontrol_tamagawa = motorcontrol_tamagawa_r5f.ti-arm-clang_clean
+BUILD_COMBO_CLEAN_motorcontrol_bissc = motorcontrol_bissc_r5f.ti-arm-clang_clean
# Combine all Components Clean
-BUILD_COMBO_CLEAN_ALL = $(BUILD_COMBO_CLEAN_motorcontrol_sdfm) $(BUILD_COMBO_CLEAN_motorcontrol_endat) $(BUILD_COMBO_CLEAN_motorcontrol_hdsl) $(BUILD_COMBO_CLEAN_motorcontrol_tamagawa)
+BUILD_COMBO_CLEAN_ALL = $(BUILD_COMBO_CLEAN_motorcontrol_sdfm) $(BUILD_COMBO_CLEAN_motorcontrol_endat) $(BUILD_COMBO_CLEAN_motorcontrol_hdsl) $(BUILD_COMBO_CLEAN_motorcontrol_tamagawa) $(BUILD_COMBO_CLEAN_motorcontrol_bissc)
# Combine all Pre-built Components Clean
BUILD_COMBO_PREBUILT_CLEAN_ALL =
@@ -148,15 +163,19 @@ $(BUILD_COMBO_CLEAN_motorcontrol_hdsl):
$(BUILD_COMBO_CLEAN_motorcontrol_tamagawa):
$(MAKE) -C source/position_sense/tamagawa -f makefile.am243x.$(subst motorcontrol_tamagawa_,,$(subst _clean,,$@)) clean
+$(BUILD_COMBO_CLEAN_motorcontrol_bissc):
+ $(MAKE) -C source/position_sense/bissc -f makefile.am243x.$(subst motorcontrol_bissc_,,$(subst _clean,,$@)) clean
+
# Various Component Scrub Targets
BUILD_COMBO_SCRUB_motorcontrol_sdfm = motorcontrol_sdfm_r5f.ti-arm-clang_scrub_scrub
BUILD_COMBO_SCRUB_motorcontrol_endat = motorcontrol_endat_r5f.ti-arm-clang_scrub_scrub
BUILD_COMBO_SCRUB_motorcontrol_hdsl = motorcontrol_hdsl_r5f.ti-arm-clang_scrub_scrub
BUILD_COMBO_SCRUB_motorcontrol_tamagawa = motorcontrol_tamagawa_r5f.ti-arm-clang_scrub_scrub
+BUILD_COMBO_SCRUB_motorcontrol_bissc = motorcontrol_bissc_r5f.ti-arm-clang_scrub_scrub
# Combine all Components Scrub Targets
-BUILD_COMBO_SCRUB_ALL = $(BUILD_COMBO_SCRUB_motorcontrol_sdfm) $(BUILD_COMBO_SCRUB_motorcontrol_endat) $(BUILD_COMBO_SCRUB_motorcontrol_hdsl) $(BUILD_COMBO_SCRUB_motorcontrol_tamagawa)
+BUILD_COMBO_SCRUB_ALL = $(BUILD_COMBO_SCRUB_motorcontrol_sdfm) $(BUILD_COMBO_SCRUB_motorcontrol_endat) $(BUILD_COMBO_SCRUB_motorcontrol_hdsl) $(BUILD_COMBO_SCRUB_motorcontrol_tamagawa) $(BUILD_COMBO_SCRUB_motorcontrol_bissc)
# Combine all Pre-built Components Scrub Targets
BUILD_COMBO_PREBUILT_SCRUB_ALL =
@@ -177,6 +196,9 @@ $(BUILD_COMBO_SCRUB_motorcontrol_hdsl):
$(BUILD_COMBO_SCRUB_motorcontrol_tamagawa):
$(MAKE) -C source/position_sense/tamagawa -f makefile.am243x.$(subst motorcontrol_tamagawa_,,$(subst _scrub,,$@)) scrub
+$(BUILD_COMBO_SCRUB_motorcontrol_bissc):
+ $(MAKE) -C source/position_sense/bissc -f makefile.am243x.$(subst motorcontrol_bissc_,,$(subst _scrub,,$@)) scrub
+
BUILD_COMBO_EXAMPLE_ALL =
# Various Example Targets
@@ -198,6 +220,9 @@ BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_fre
BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang
+BUILD_COMBO_EXAMPLE_ALL += bissc_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang
+BUILD_COMBO_EXAMPLE_ALL += bissc_diagnostic_multi_channel_load_share_am243x-lp_r5fss0-0_freertos_ti-arm-clang
+BUILD_COMBO_EXAMPLE_ALL += bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang
# Various System Example Targets
@@ -219,6 +244,11 @@ BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pr
BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt
+BUILD_COMBO_EXAMPLE_PRIVATE_ALL += bissc_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
+BUILD_COMBO_EXAMPLE_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
+BUILD_COMBO_EXAMPLE_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt
+BUILD_COMBO_EXAMPLE_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt
+BUILD_COMBO_EXAMPLE_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
# Various Private System Example Targets
examples: $(BUILD_COMBO_EXAMPLE_ALL)
@@ -279,6 +309,15 @@ examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL)
tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile all
+ bissc_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile all
+
+ bissc_diagnostic_multi_channel_load_share_am243x-lp_r5fss0-0_freertos_ti-arm-clang:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile all
+
+ bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile all
+
icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang:
$(MAKE) -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all
@@ -330,6 +369,21 @@ examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL)
tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt:
$(MAKE) -C source/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile all
+ bissc_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt:
+ $(MAKE) -C source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile all
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile all
+
+ bissc_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
+
BUILD_COMBO_EXAMPLE_CLEAN_ALL =
# Various Example Clean Targets
@@ -351,6 +405,9 @@ BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0
BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
+BUILD_COMBO_EXAMPLE_CLEAN_ALL += bissc_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
+BUILD_COMBO_EXAMPLE_CLEAN_ALL += bissc_diagnostic_multi_channel_load_share_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
+BUILD_COMBO_EXAMPLE_CLEAN_ALL += bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
# Various System Example Clean Targets
@@ -372,6 +429,11 @@ BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_sync_225_mhz_am243x-evm_ics
BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += bissc_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += bissc_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
# Various Private System Example Targets
examples-clean: $(BUILD_COMBO_EXAMPLE_CLEAN_ALL)
@@ -432,6 +494,15 @@ examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL)
tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile clean
+ bissc_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile clean
+
+ bissc_diagnostic_multi_channel_load_share_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile clean
+
+ bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile clean
+
icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean
@@ -483,6 +554,21 @@ examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL)
tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_clean:
$(MAKE) -C source/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
+ bissc_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
+ $(MAKE) -C source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_clean:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile clean
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_clean:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile clean
+
+ bissc_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
+
BUILD_COMBO_EXAMPLE_SCRUB_ALL =
# Various Example Scrub Targets
@@ -504,6 +590,9 @@ BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0
BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
+BUILD_COMBO_EXAMPLE_SCRUB_ALL += bissc_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
+BUILD_COMBO_EXAMPLE_SCRUB_ALL += bissc_diagnostic_multi_channel_load_share_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
+BUILD_COMBO_EXAMPLE_SCRUB_ALL += bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
# Various System Example Scrub Targets
@@ -525,6 +614,11 @@ BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_sync_225_mhz_am243x-evm_ics
BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_scrub
+BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += bissc_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
+BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
+BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_scrub
+BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_scrub
+BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += bissc_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
# Various Private System Example Targets
examples-scrub: $(BUILD_COMBO_EXAMPLE_SCRUB_ALL)
@@ -585,6 +679,15 @@ examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL)
tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
+ bissc_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
+
+ bissc_diagnostic_multi_channel_load_share_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
+
+ bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
+
icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub:
$(MAKE) -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
@@ -636,6 +739,21 @@ examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL)
tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_scrub:
$(MAKE) -C source/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
+ bissc_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
+ $(MAKE) -C source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_scrub:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile scrub
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_scrub:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile scrub
+
+ bissc_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
+
.PHONY: all clean scrub help
.PHONY: libs libs-clean libs-scrub
diff --git a/makefile_projectspec.am243x b/makefile_projectspec.am243x
index e4cbee4..8fad01a 100644
--- a/makefile_projectspec.am243x
+++ b/makefile_projectspec.am243x
@@ -25,6 +25,9 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_single_channel_am24
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += bissc_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += bissc_diagnostic_multi_channel_load_share_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
# Various System Example Projectspec Build Targets
@@ -46,6 +49,11 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_sync_225_mhz_am
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += bissc_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build
# Various Private System Example Projectspec Build Targets
all: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL)
@@ -106,6 +114,15 @@ all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL)
tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
+ bissc_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
+
+ bissc_diagnostic_multi_channel_load_share_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
+
+ bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
+
icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build:
$(MAKE) -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
@@ -157,6 +174,21 @@ all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL)
tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_build:
$(MAKE) -C source/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
+ bissc_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
+ $(MAKE) -C source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_build:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile_projectspec all
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_build:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile_projectspec all
+
+ bissc_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
+
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL =
@@ -179,6 +211,9 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_single_channel_am24
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += bissc_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += bissc_diagnostic_multi_channel_load_share_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
# Various System Example Projectspec Clean Targets
@@ -200,6 +235,11 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_sync_225_mhz_am
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += bissc_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
# Various Private System Example Projectspec Clean Targets
clean: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL)
@@ -260,6 +300,15 @@ clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL)
tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
+ bissc_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
+
+ bissc_diagnostic_multi_channel_load_share_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
+
+ bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
+
icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
@@ -311,6 +360,21 @@ clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL)
tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_clean:
$(MAKE) -C source/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
+ bissc_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
+ $(MAKE) -C source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_clean:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile_projectspec clean
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_clean:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile_projectspec clean
+
+ bissc_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
+
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL =
@@ -333,6 +397,9 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_single_channel_am2
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += bissc_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += bissc_diagnostic_multi_channel_load_share_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += icss_sdfm_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
# Various System Example Projectspec Export Targets
@@ -354,6 +421,11 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_sync_225_mhz_a
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_single_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += bissc_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += bissc_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export
# Various Private System Example Projectspec Export Targets
export: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL)
@@ -414,6 +486,15 @@ export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL)
tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
+ bissc_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
+
+ bissc_diagnostic_multi_channel_load_share_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
+
+ bissc_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export:
+ $(MAKE) -C examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
+
icss_sdfm_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export:
$(MAKE) -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
@@ -465,6 +546,21 @@ export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL)
tamagawa_single_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_export:
$(MAKE) -C source/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
+ bissc_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
+ $(MAKE) -C source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt_export:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile_projectspec export
+
+ bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt_export:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile_projectspec export
+
+ bissc_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
+ $(MAKE) -C source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
+
# Import extra components into CCS workspace before creating a project
# Setup dependency separately so that it runs if one or all projects are built via the makefile
@@ -512,6 +608,9 @@ help:
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
+ @echo $(MAKE) -s -C examples/position_sense/bissc_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
+ @echo $(MAKE) -s -C examples/position_sense/bissc_diagnostic/multi_channel_load_share/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
+ @echo $(MAKE) -s -C examples/position_sense/bissc_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/current_sense/icss_sdfm/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/current_sense/icss_sdfm/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C source/current_sense/sdfm/firmware/am243x-evm/icssg0-pru0_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
@@ -529,6 +628,11 @@ help:
@echo $(MAKE) -s -C source/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C source/position_sense/tamagawa/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C source/position_sense/tamagawa/firmware/single_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
+ @echo $(MAKE) -s -C source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
+ @echo $(MAKE) -s -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
+ @echo $(MAKE) -s -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
+ @echo $(MAKE) -s -C source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
+ @echo $(MAKE) -s -C source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
@echo .
@echo System Example ProjectSpec build targets,
@echo =========================================
diff --git a/source/.meta/position_sense/bissc.syscfg.js b/source/.meta/position_sense/bissc.syscfg.js
new file mode 100644
index 0000000..e39d496
--- /dev/null
+++ b/source/.meta/position_sense/bissc.syscfg.js
@@ -0,0 +1,191 @@
+
+let common = system.getScript("/common");
+let bissc_pins = system.getScript("/position_sense/bissc_pins.js");
+let device = common.getDeviceName();
+let is_am243x_lp_device = (device === "am243x-lp") ? true : false;
+
+let bissc_module_name = "/position_sense/bissc";
+
+function onValidate(inst, validation) {
+ for (let instance_index in inst.$module.$instances)
+ {
+ let instance = inst.$module.$instances[instance_index];
+ if ((!instance.channel_0)&&(!instance.channel_1)&&(!instance.channel_2))
+ validation.logError("Select atleast one channel",inst,"channel_0"
+ );
+
+ /* validation for booster pack */
+ if((device!="am243x-lp")&&(instance.Booster_Pack))
+ {
+ validation.logError("Select only when using Booster Pack with LP",inst,"Booster_Pack");
+ }
+ }
+}
+
+let bissc_module = {
+
+ displayName: "BiSSC Position Encoder",
+ templates: {
+ "/drivers/system/system_config.h.xdt": {
+ driver_config: "/position_sense/bissc/bissc.h.xdt",
+ moduleName: bissc_module_name,
+ },
+
+ "/drivers/pinmux/pinmux_config.c.xdt": {
+ moduleName: bissc_module_name,
+ },
+ },
+ defaultInstanceName: "CONFIG_BISSC",
+ config: [
+ {
+ name: "instance",
+ displayName: "Instance",
+ default: "ICSSG0",
+ options: [
+ {
+ name: "ICSSG0",
+ },
+ {
+ name: "ICSSG1",
+ }
+ ],
+ },
+ {
+ name: "channel_0",
+ displayName: "Select Channel 0",
+ description: "Channel 0 Selection ",
+ default: true,
+
+ },
+ {
+ name: "channel_1",
+ displayName: "Select Channel 1",
+ description: "Channel 1 Selection ",
+ default: false,
+
+ },
+ {
+ name: "channel_2",
+ displayName: "Select Channel 2",
+ description: "Channel 2 Selection ",
+ default: false,
+
+ },
+ {
+ name: "baudrate",
+ displayName: "Select Baud Rate(in Mbps)",
+ description: "Data Speed Selection ",
+ default: 1,
+ options: [
+ {
+ name: 1,
+ },
+ {
+ name: 2,
+ },
+ {
+ name: 5,
+ },
+ {
+ name: 8,
+ },
+ {
+ name: 10,
+ },
+ ],
+ },
+ {
+ name: "Multi_Channel_Load_Share",
+ displayName: "Multi Channel Load Share",
+ description: "Selected Channels have different make",
+ default: false,
+ },
+ {
+ name: "Booster_Pack",
+ displayName: "Booster Pack",
+ description: "Only for Booster Pack",
+ default: false,
+ },
+ ],
+ moduleStatic: {
+ modules: function(inst) {
+ return [{
+ name: "system_common",
+ moduleName: "/system_common",
+ }]
+ },
+ },
+ pinmuxRequirements: bissc_pins.pinmuxRequirements,
+ getInterfaceName: bissc_pins.getInterfaceName,
+ getPeripheralPinNames: bissc_pins.getPeripheralPinNames,
+ sharedModuleInstances: sharedModuleInstances,
+ validate: onValidate,
+};
+
+function sharedModuleInstances(instance) {
+ let modInstances = new Array();
+
+ modInstances.push({
+ name: "pru",
+ displayName: "PRU ICSS Configuration",
+ moduleName: '/drivers/pruicss/pruicss',
+ requiredArgs: {
+ instance: instance.instance,
+ coreClk: 200*1000000,
+ },
+ });
+ if(device == "am243x-lp")
+ {
+ modInstances.push({
+ name: "ENC0_EN",
+ displayName: "Booster Pack Ch0 Enable Pin",
+ moduleName: "/drivers/gpio/gpio",
+ requiredArgs: {
+ pinDir: "OUTPUT"
+ },
+ });
+ modInstances.push({
+ name: "ENC1_EN",
+ displayName: "Booster Pack Ch1 Enable Pin",
+ moduleName: "/drivers/gpio/gpio",
+ requiredArgs: {
+ pinDir: "OUTPUT"
+ },
+ });
+ modInstances.push({
+ name: "ENC2_EN",
+ displayName: "Booster Pack Ch2 Enable Pin",
+ moduleName: "/drivers/gpio/gpio",
+ requiredArgs: {
+ pinDir: "OUTPUT"
+ },
+ });
+ modInstances.push({
+ name: "BISSC_CH0_OUT_EN",
+ displayName: "ENDAT Ch0 TX Enable Pin",
+ moduleName: "/drivers/gpio/gpio",
+ requiredArgs: {
+ pinDir: "OUTPUT"
+ },
+ });
+ modInstances.push({
+ name: "BISSC_CH1_OUT_EN",
+ displayName: "ENDAT Ch1 TX Enable Pin",
+ moduleName: "/drivers/gpio/gpio",
+ requiredArgs: {
+ pinDir: "OUTPUT"
+ },
+ });
+ modInstances.push({
+ name: "BISSC_CH2_OUT_EN",
+ displayName: "ENDAT Ch2 TX Enable Pin",
+ moduleName: "/drivers/gpio/gpio",
+ requiredArgs: {
+ pinDir: "OUTPUT"
+ },
+ });
+ }
+ return (modInstances);
+}
+
+exports = bissc_module;
diff --git a/source/.meta/position_sense/bissc/bissc.h.xdt b/source/.meta/position_sense/bissc/bissc.h.xdt
new file mode 100644
index 0000000..ceac0f4
--- /dev/null
+++ b/source/.meta/position_sense/bissc/bissc.h.xdt
@@ -0,0 +1,49 @@
+%%{
+ let module = system.modules[args[0]];
+%%}
+/*
+ * BiSSC
+ */
+
+/* BiSSC Instance Macros */
+#define CONFIG_BISSC_NUM_INSTANCES `module.$instances.length`
+% for(let i = 0; i < module.$instances.length; i++) {
+ % let instance = module.$instances[i];
+ % let Mode = 0;
+ % let sliceVal = 1;
+ % let icssValue = 0;
+ % if(instance.instance === "ICSSG0")
+ % {
+ % if(instance.PRU_ICSSG0_PRU.$assign === "PRU_ICSSG0_PRU0")
+ % {
+ % sliceVal = 0;
+ % }
+ % }
+ % else if(instance.instance === "ICSSG1")
+ % {
+ % icssValue = 1;
+ % if(instance.PRU_ICSSG1_PRU.$assign === "PRU_ICSSG1_PRU0")
+ % {
+ % sliceVal = 0;
+ % }
+ % }
+ %if(((instance.channel_0 & 1)&&(instance.channel_1 & 1))||((instance.channel_1 & 1)&&(instance.channel_2 & 1))||((instance.channel_2 & 1)&&(instance.channel_0 & 1)))
+ %{
+ % Mode = 1;
+ %}
+ %if(instance.Multi_Channel_Load_Share & 1)
+ %{
+ % Mode = 2;
+ %}
+
+#define `instance.$name` (`i`)
+#define `instance.$name`_CHANNEL0 (`instance.channel_0 & 1`)
+#define `instance.$name`_CHANNEL1 (`instance.channel_1 & 1`)
+#define `instance.$name`_CHANNEL2 (`instance.channel_2 & 1`)
+#define `instance.$name`_BAUDRATE (`instance.baudrate`)
+#define `instance.$name`_LOAD_SHARE_MODE `instance.Multi_Channel_Load_Share & 1`
+#define `instance.$name`_MODE `Mode`
+#define `instance.$name`_BOOSTER_PACK (`instance.Booster_Pack & 1`)
+#define PRUICSS_PRUx (`sliceVal`)
+#define PRUICSSx (`icssValue`)
+% }
diff --git a/source/.meta/position_sense/bissc_pins.js b/source/.meta/position_sense/bissc_pins.js
new file mode 100644
index 0000000..c47b7b9
--- /dev/null
+++ b/source/.meta/position_sense/bissc_pins.js
@@ -0,0 +1,82 @@
+
+let common = system.getScript("/common");
+let pinmux = system.getScript("/drivers/pinmux/pinmux");
+
+
+function getInterfaceName(inst)
+{
+ return `PRU_${inst.instance}_PRU`;
+}
+
+function getInterfacePinList(inst)
+{
+ let pinList = [];
+
+ /* BISSC_CHANNEL0_TX_ENABLE - is configured as soc gpio and kept low forever */
+ /*pinList.push({ pinName: "GPO2", displayName: "BISSC_CHANNEL0_TX_ENABLE", rx: false});*/
+ pinList.push({ pinName: "GPO1", displayName: "BISSC_CHANNEL0_TX", rx: false});
+ pinList.push({ pinName: "GPO0", displayName: "BISSC_CHANNEL0_CLK", rx: false});
+ pinList.push({ pinName: "GPI13", displayName: "BISSC_CHANNEL0_RX", rx: true});
+
+ /* BISSC_CHANNEL1_TX_ENABLE - is configured as soc gpio and kept low forever */
+ /*pinList.push({ pinName: "GPO5", displayName: "BISSC_CHANNEL1_TX_ENABLE", rx: false});*/
+ pinList.push({ pinName: "GPO4", displayName: "BISSC_CHANNEL1_TX", rx: false});
+ pinList.push({ pinName: "GPO3", displayName: "BISSC_CHANNEL1_CLK", rx: false});
+ pinList.push({ pinName: "GPI14", displayName: "BISSC_CHANNEL1_RX", rx: true});
+
+ /* BISSC_CHANNEL2_TX_ENABLE - is configured as soc gpio and kept low forever */
+ /*pinList.push({ pinName: "GPO8", displayName: "BISSC_CHANNEL2_TX_ENABLE", rx: false});*/
+ pinList.push({ pinName: "GPO12", displayName: "BISSC_CHANNEL2_TX", rx: false});
+ pinList.push({ pinName: "GPO6", displayName: "BISSC_CHANNEL2_CLK", rx: false});
+ pinList.push({ pinName: "GPI11", displayName: "BISSC_CHANNEL2_RX", rx: true});
+
+ return pinList;
+}
+
+function pinmuxRequirements(inst) {
+
+ let interfaceName = getInterfaceName(inst);
+ let pinList = getInterfacePinList(inst);
+ let resources = [];
+
+ for(let pin of pinList)
+ {
+ let pinResource = pinmux.getPinRequirements(interfaceName, pin.pinName, pin.displayName);
+
+ pinmux.setConfigurableDefault( pinResource, "rx", pin.rx );
+
+ resources.push( pinResource );
+ }
+
+ let peripheralRequirements = {
+ name: interfaceName,
+ displayName: interfaceName,
+ interfaceName: interfaceName,
+ resources: resources,
+ };
+
+ return [peripheralRequirements];
+}
+
+function getPeripheralPinNames(inst)
+{
+ let pinList = [];
+ let pinNameList = [];
+
+ pinList = getInterfacePinList(inst);
+
+ for(let pin of pinList)
+ {
+ pinNameList.push( pin.pinName );
+ }
+
+ return pinNameList;
+}
+
+
+exports = {
+
+ pinmuxRequirements,
+ getInterfaceName,
+ getPeripheralPinNames,
+};
diff --git a/source/.meta/soc/motor_control_am243x.syscfg.js b/source/.meta/soc/motor_control_am243x.syscfg.js
index 8665649..77e8ab4 100644
--- a/source/.meta/soc/motor_control_am243x.syscfg.js
+++ b/source/.meta/soc/motor_control_am243x.syscfg.js
@@ -5,6 +5,7 @@ const topModules_main = [
"/position_sense/endat",
"/position_sense/hdsl",
"/position_sense/tamagawa",
+ "/position_sense/bissc",
];
diff --git a/source/position_sense/bissc/.project/project.js b/source/position_sense/bissc/.project/project.js
new file mode 100644
index 0000000..f6c2d16
--- /dev/null
+++ b/source/position_sense/bissc/.project/project.js
@@ -0,0 +1,14 @@
+function getComponentProperty(device)
+{
+ return require(`./project_${device}`).getComponentProperty();
+};
+
+function getComponentBuildProperty(buildOption)
+{
+ return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption);
+};
+
+module.exports = {
+ getComponentProperty,
+ getComponentBuildProperty,
+};
diff --git a/source/position_sense/bissc/.project/project_am243x.js b/source/position_sense/bissc/.project/project_am243x.js
new file mode 100644
index 0000000..980b360
--- /dev/null
+++ b/source/position_sense/bissc/.project/project_am243x.js
@@ -0,0 +1,52 @@
+let path = require('path');
+
+let device = "am243x";
+
+const files = {
+ common: [
+ "bissc_drv.c",
+ ],
+};
+
+const filedirs = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/driver",
+ ],
+};
+
+const includes = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/include",
+ ],
+};
+
+const buildOptionCombos = [
+ { device: device, cpu: "r5f", cgt: "ti-arm-clang"},
+];
+
+function getComponentProperty() {
+ let property = {};
+
+ property.dirPath = path.resolve(__dirname, "..");
+ property.type = "library";
+ property.name = "motorcontrol_bissc";
+ property.isInternal = false;
+ property.buildOptionCombos = buildOptionCombos;
+
+ return property;
+}
+
+function getComponentBuildProperty(buildOption) {
+ let build_property = {};
+
+ build_property.files = files;
+ build_property.filedirs = filedirs;
+ build_property.includes = includes;
+
+ return build_property;
+}
+
+module.exports = {
+ getComponentProperty,
+ getComponentBuildProperty,
+};
diff --git a/source/position_sense/bissc/driver/bissc_drv.c b/source/position_sense/bissc/driver/bissc_drv.c
new file mode 100644
index 0000000..10ef985
--- /dev/null
+++ b/source/position_sense/bissc/driver/bissc_drv.c
@@ -0,0 +1,527 @@
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include
+#include
+static struct bissc_priv bissc_priv;
+
+void bissc_command_send(struct bissc_priv *priv)
+{
+ struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
+ if(priv->load_share)
+ {
+ pruicss_xchg->cycle_trigger[0] = (pruicss_xchg->channel & 0x1)?0x1:0;
+ pruicss_xchg->cycle_trigger[1] = (pruicss_xchg->channel & 0x2)?0x1:0;
+ pruicss_xchg->cycle_trigger[2] = (pruicss_xchg->channel & 0x4)?0x1:0;
+
+ }
+ else
+ {
+ pruicss_xchg->cycle_trigger[0] = 0x1;
+ }
+
+}
+
+int32_t bissc_command_wait(struct bissc_priv *priv)
+{
+ struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
+ uint32_t timeout;
+ /*Wait for max of 5 ms*/
+ timeout = BISSC_MAX_CYCLE_TIMEOUT;
+ while(1)
+ {
+ if(priv->load_share){
+ if((pruicss_xchg->cycle_trigger[0] == 0 ) && (pruicss_xchg->cycle_trigger[1] == 0) && (pruicss_xchg->cycle_trigger[2] == 0)){
+ break;
+ }
+ }
+ else if(pruicss_xchg->cycle_trigger[0] == 0)
+ {
+ break;
+ }
+ ClockP_usleep(1000);
+ timeout--;
+ if(timeout == 0)
+ {
+ return SystemP_FAILURE;
+ }
+ }
+ return SystemP_SUCCESS;
+}
+
+int32_t bissc_command_process(struct bissc_priv *priv)
+{
+ int32_t ret = SystemP_FAILURE;
+ bissc_command_send(priv);
+ ret = bissc_command_wait(priv);
+ return ret;
+}
+
+int32_t bissc_get_pos_res(struct bissc_priv *priv)
+{
+ uint32_t raw_data0, raw_data1, shift, sl_num, max, ch_num, numslaves, ls_ch;
+ int32_t ch = 0;
+ if(bissc_command_process(priv) < 0)
+ {
+ return SystemP_FAILURE;
+ }
+ for(ch_num = 0; ch_num < priv->totalchannels; ch_num++)
+ {
+ ch = priv->channel[ch_num];
+ if(priv->load_share)
+ {
+ numslaves = priv->num_slaves[ch];
+ ls_ch = ch;
+ }
+ else
+ {
+ numslaves = priv->num_slaves[0];
+ ls_ch = 0;
+ }
+ for(sl_num = 0; sl_num < numslaves; sl_num++)
+ {
+ raw_data0 = priv->pruicss_xchg->pos_data_res[sl_num].raw_data[ch].pos_data_word0;
+ raw_data1 = priv->pruicss_xchg->pos_data_res[sl_num].raw_data[ch].pos_data_word1;
+ max = pow(2, priv->single_turn_len[ls_ch][sl_num]);
+ if((priv->data_len[ls_ch][sl_num] + BISSC_POS_CRC_LEN + BISSC_EW_LEN) <= 32)
+ {
+ priv->raw_data = (uint64_t) raw_data0;
+ priv->enc_pos_data[ch].position[sl_num] = (uint64_t) (raw_data0 >> (BISSC_POS_CRC_LEN + BISSC_EW_LEN));
+ priv->enc_pos_data[ch].ew[sl_num] = ((raw_data0 >> (BISSC_POS_CRC_LEN )) & 0x03);
+ priv->enc_pos_data[ch].num_of_turns[sl_num] = priv->enc_pos_data[ch].position[sl_num] >> priv->single_turn_len[ls_ch][sl_num];
+ priv->enc_pos_data[ch].angle[sl_num] = (float)(priv->enc_pos_data[ch].position[sl_num] & (max - 1)) / max * (float)360;
+ priv->enc_pos_data[ch].rcv_crc[sl_num] = raw_data0 & 0x3F;
+ priv->enc_pos_data[ch].otf_crc[sl_num] = priv->pruicss_xchg->pos_data_res[sl_num].pos_data_otf_crc[ch];
+ priv->pd_crc_err_cnt[ch][sl_num] = priv->pruicss_xchg->pos_data_res[sl_num].pd_crc_err_cnt[ch];
+ }
+ else
+ {
+ shift = ((priv->data_len[ls_ch][sl_num] + BISSC_POS_CRC_LEN + BISSC_EW_LEN) - 32);
+ priv->raw_data = (uint64_t) raw_data0 << shift | raw_data1;
+ priv->enc_pos_data[ch].position[sl_num] = (uint64_t) (priv->raw_data >> (BISSC_POS_CRC_LEN + BISSC_EW_LEN));
+ priv->enc_pos_data[ch].ew[sl_num] = ((priv->raw_data >> (BISSC_POS_CRC_LEN )) & 0x03);
+ priv->enc_pos_data[ch].num_of_turns[sl_num] = priv->enc_pos_data[ch].position[sl_num] >> priv->single_turn_len[ls_ch][sl_num];
+ priv->enc_pos_data[ch].angle[sl_num] = (float)(priv->enc_pos_data[ch].position[sl_num] & (max - 1)) / max * (float)360;
+ priv->enc_pos_data[ch].rcv_crc[sl_num] = priv->raw_data & 0x3F;
+ priv->enc_pos_data[ch].otf_crc[sl_num] = priv->pruicss_xchg->pos_data_res[sl_num].pos_data_otf_crc[ch];
+ priv->pd_crc_err_cnt[ch][sl_num] = priv->pruicss_xchg->pos_data_res[sl_num].pd_crc_err_cnt[ch];
+ }
+ }
+ }
+ return SystemP_SUCCESS;
+}
+void bissc_config_clock(struct bissc_priv *priv,
+ struct bissc_clk_cfg *clk_cfg)
+{
+ void *pruicss_cfg = priv->pruicss_cfg;
+ struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
+ /* Set PRU1_ED_RX_SB_POL polarity bit to 0 for bissc, required for ICSSG (don't care for ICSSM) */
+ if(priv->pruicss_slicex)
+ {
+ HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU1RXCFGREGISTER, ((clk_cfg->rx_div << 16) |
+ (clk_cfg->is_ocp << 4) | (clk_cfg->rx_div_attr)));
+ HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, clk_cfg->tx_div << 16 |
+ (clk_cfg->is_ocp << 4));
+ }
+ else
+ {
+ HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU0RXCFGREGISTER, ((clk_cfg->rx_div << 16) |
+ (clk_cfg->is_ocp << 4) | (clk_cfg->rx_div_attr)));
+ HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER, clk_cfg->tx_div << 16 |
+ (clk_cfg->is_ocp << 4));
+ }
+ if(priv->load_share)
+ bissc_enable_load_share_mode(priv);
+ /* Clock configuration has changed - Indicate fw to measure the delay again */
+ pruicss_xchg->measure_proc_delay = 1;
+
+}
+
+void bissc_config_channel(struct bissc_priv *priv, int32_t mask, int32_t totalch)
+{
+ struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
+ int32_t ch_num;
+ pruicss_xchg->channel = mask;
+ priv->totalchannels = totalch;
+ for(ch_num = 0; ch_num < totalch; ch_num++){
+ if((mask & 1) && ch_num == 0)
+ priv->channel[ch_num] = 0;
+ else if((mask & 2) && (ch_num == 0 || ch_num == 1))
+ priv->channel[ch_num] = 1;
+ else if((mask & 4))
+ priv->channel[ch_num] = 2;
+ }
+}
+void bissc_config_load_share(struct bissc_priv *priv, int32_t mask, int32_t loadshare)
+{
+ priv->load_share = loadshare;
+ bissc_config_primary_core_mask(priv, mask);
+ bissc_enable_load_share_mode(priv);
+}
+void bissc_enable_load_share_mode(struct bissc_priv *priv)
+{
+ void *pruss_cfg = priv->pruicss_cfg;
+ //HW_WR_REG32(0x30026104) |= 0x0800;
+ uint32_t rgval;
+ if(priv->pruicss_slicex)
+ {
+ rgval = HW_RD_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER);
+ rgval |= CSL_ICSSCFG_EDPRU1TXCFGREGISTER_PRU1_ENDAT_SHARE_EN_MASK;
+ HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, rgval);
+ }
+ else
+ {
+ rgval = HW_RD_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER);
+ rgval |= CSL_ICSSCFG_EDPRU0TXCFGREGISTER_PRU0_ENDAT_SHARE_EN_MASK;
+ HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER, rgval);
+ }
+}
+void bissc_config_primary_core_mask(struct bissc_priv *priv, uint8_t mask)
+{
+ switch (mask)
+ {
+ case 1: /*only channel0 connected*/
+ priv->pruicss_xchg->primary_core_mask=0x1;
+ break;
+ case 2: /*channel1 connected*/
+ priv->pruicss_xchg->primary_core_mask=0x2;
+ break;
+ case 3: /*channel0 and channel1 connected*/
+ priv->pruicss_xchg->primary_core_mask=0x1;
+ break;
+ case 4: /*channel2 connected*/
+ priv->pruicss_xchg->primary_core_mask=0x4;
+ break;
+ case 5: /*channel0 and channel2 connnected*/
+ priv->pruicss_xchg->primary_core_mask=0x4;
+ break;
+ case 6: /*channel1 and channel2 connected*/
+ priv->pruicss_xchg->primary_core_mask=0X4;
+ break;
+ case 7: /*all three channel connected*/
+ priv->pruicss_xchg->primary_core_mask=0x4;
+ break;
+ }
+}
+int32_t bissc_wait_for_fw_initialization(struct bissc_priv *priv, uint32_t timeout, uint8_t mask)
+{
+ int32_t i;
+ struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
+ for(i = 0; i < timeout; i++)
+ {
+ if(priv->load_share) /* for loadshare mode*/
+ {
+ switch (mask) {
+ case 1: /*channel 0 connected*/
+ if((pruicss_xchg->status[0] & 1))
+ return SystemP_SUCCESS;
+ break;
+ case 2: /*channel 1 connected*/
+ if((pruicss_xchg->status[1] & 1))
+ return SystemP_SUCCESS;
+ break;
+ case 3: /*channel 0 and 1 connected*/
+ if((pruicss_xchg->status[0] & 1) && (pruicss_xchg->status[1] & 1))
+ return SystemP_SUCCESS;
+ break;
+ case 4: /*channel 2 connected*/
+ if((pruicss_xchg->status[2] & 1))
+ return SystemP_SUCCESS;
+ break;
+ case 5: /*channel 0 and 2 connnected*/
+ if((pruicss_xchg->status[0] & 1) && (pruicss_xchg->status[2] & 1))
+ return SystemP_SUCCESS;
+ break;
+ case 6: /*channel 1 and 2 connected*/
+ if((pruicss_xchg->status[1] & 1) && (pruicss_xchg->status[2] & 1))
+ return SystemP_SUCCESS;
+ break;
+ case 7: /*all three channel connected*/
+ if((pruicss_xchg->status[0] & 1) && (pruicss_xchg->status[1] & 1) && ( pruicss_xchg->status[2] & 1))
+ return SystemP_SUCCESS;
+ break;
+ }
+ ClockP_usleep(1000 * 1);
+ }
+ else if(pruicss_xchg->status[0] & 1)
+ {
+ break;
+ }
+ else
+ {
+ ClockP_usleep(1000 * 1);
+ }
+ }
+ if(i == timeout)
+ {
+ return SystemP_FAILURE;
+ }
+ return SystemP_SUCCESS;
+}
+
+void bissc_config_clr_cfg0(struct bissc_priv *priv)
+{
+ void *pruicss_cfg = priv->pruicss_cfg;
+ if(priv->pruicss_slicex)
+ {
+ HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU1CH0CFG0REGISTER, 0);
+ HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU1CH1CFG0REGISTER, 0);
+ HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU1CH2CFG0REGISTER, 0);
+ }
+ else
+ {
+ HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU0CH0CFG0REGISTER, 0);
+ HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU0CH1CFG0REGISTER, 0);
+ HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU0CH2CFG0REGISTER, 0);
+ }
+}
+
+void bissc_config_endat_mode(struct bissc_priv *priv)
+{
+ void *pruicss_cfg = priv->pruicss_cfg;
+ if(priv->pruicss_slicex)
+ {
+ HW_WR_REG8((uint8_t *)pruicss_cfg + CSL_ICSSCFG_GPCFG1 + 3, 4);
+ }
+ else
+ {
+ HW_WR_REG8((uint8_t *)pruicss_cfg + CSL_ICSSCFG_GPCFG0 + 3, 4);
+ }
+}
+int32_t bissc_calc_clock(uint32_t freq, struct bissc_clk_cfg *clk_cfg)
+{
+ clk_cfg->rx_div_attr = BISSC_RX_SAMPLE_SIZE;
+ if((freq == 1) || (freq == 5))
+ {
+ freq = freq * 1000 * 1000;
+ clk_cfg->tx_div = (BISSC_INPUT_CLOCK_OCP_FREQUENCY / freq) - 1;
+ clk_cfg->rx_div = (BISSC_INPUT_CLOCK_OCP_FREQUENCY / (freq * 8)) - 1;
+ clk_cfg->is_ocp = 1;
+ }
+ else if((freq == 2) || (freq == 8))
+ {
+ freq = freq * 1000 * 1000;
+ clk_cfg->tx_div = (BISSC_INPUT_CLOCK_FREQUENCY_UART / freq) - 1;
+ clk_cfg->rx_div = (BISSC_INPUT_CLOCK_FREQUENCY_UART / (freq * 8)) - 1;
+ clk_cfg->is_ocp = 0;
+ }
+ else if(freq == 10)
+ {
+ freq = freq* 1000 * 1000;
+ clk_cfg->tx_div = (BISSC_INPUT_CLOCK_OCP_FREQUENCY / freq) - 1;
+ clk_cfg->rx_div = (BISSC_INPUT_CLOCK_OCP_FREQUENCY / (freq * 4)) - 1;
+ clk_cfg->is_ocp = 1;
+ clk_cfg->rx_div_attr = BISSC_RX_SAMPLE_SIZE_10MHZ;
+ }
+ else
+ {
+ return SystemP_FAILURE;
+ }
+ return SystemP_SUCCESS;
+}
+
+static void bissc_hw_init(struct bissc_priv *priv, uint32_t frequency)
+{
+ struct bissc_clk_cfg clk_cfg;
+ bissc_calc_clock(frequency, &clk_cfg);
+ bissc_config_endat_mode(priv);
+ bissc_config_clock(priv, &clk_cfg);
+ bissc_config_clr_cfg0(priv);
+}
+
+
+struct bissc_priv *bissc_init(PRUICSS_Handle gPruIcssXHandle, int32_t slice, uint32_t frequency)
+{
+ struct bissc_pruicss_xchg *pruicss_xchg;
+ void *pruicss_cfg;
+ pruicss_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcssXHandle->hwAttrs))->cfgRegBase);
+ if(slice)
+ pruicss_xchg = (struct bissc_pruicss_xchg *)((PRUICSS_HwAttrs *)(gPruIcssXHandle->hwAttrs))->pru1DramBase;
+ else
+ pruicss_xchg = (struct bissc_pruicss_xchg *)((PRUICSS_HwAttrs *)(gPruIcssXHandle->hwAttrs))->pru0DramBase;
+ bissc_priv.pruicss_xchg = pruicss_xchg;
+ bissc_priv.pruicss_cfg = pruicss_cfg;
+ bissc_priv.pruicss_slicex = slice;
+ bissc_hw_init(&bissc_priv, frequency);
+ return &bissc_priv;
+}
+
+void bissc_update_max_proc_delay(struct bissc_priv *priv, uint32_t frequency)
+{
+ struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
+ pruicss_xchg->fifo_bit_idx = 4; /* 8x over clock - middle bit*/
+ if(frequency == 1)
+ pruicss_xchg->max_proc_delay = BISSC_MAX_PROC_DELAY_1MHZ;
+ else if(frequency == 2)
+ pruicss_xchg->max_proc_delay = BISSC_MAX_PROC_DELAY_2MHZ;
+ else if(frequency == 5)
+ pruicss_xchg->max_proc_delay = BISSC_MAX_PROC_DELAY_5MHZ;
+ else if(frequency == 8)
+ pruicss_xchg->max_proc_delay = BISSC_MAX_PROC_DELAY_8MHZ;
+ else if(frequency == 10)
+ {
+ pruicss_xchg->max_proc_delay = BISSC_MAX_PROC_DELAY_10MHZ;
+ pruicss_xchg->fifo_bit_idx = 2; /* 4x over clock - middle bit*/
+ }
+}
+
+int32_t bissc_wait_measure_proc_delay(struct bissc_priv *priv, uint32_t timeout)
+{
+ int32_t i;
+ struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
+ for(i = 0; i < timeout; i++)
+ {
+ if(pruicss_xchg->measure_proc_delay & 1)
+ {
+ break;
+ }
+ else
+ {
+ ClockP_usleep(1000);
+ }
+ }
+ if(i == timeout)
+ {
+ return SystemP_FAILURE;
+ }
+ return SystemP_SUCCESS;
+}
+
+void bissc_set_default_initialization(struct bissc_priv *priv, uint32_t frequency, uint64_t icssgclk)
+{
+ int8_t pru_num, totalprus, ls_ch;
+ struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
+ /* Initialize parameters to default values */
+ if(priv->load_share)
+ totalprus = priv->totalchannels;
+ else
+ totalprus = 1;
+ for( pru_num = 0; pru_num < totalprus; pru_num++)
+ {
+ if(priv->load_share)
+ ls_ch = priv->channel[pru_num];
+ else
+ ls_ch = 0;
+ pruicss_xchg->enc_len[ls_ch].data_len[0] = BISSC_POS_DATA_LEN_DEFAULT;
+ priv->data_len[ls_ch][0] = BISSC_POS_DATA_LEN_DEFAULT;
+ priv->single_turn_len[ls_ch][0] = BISSC_POS_DATA_LEN_DEFAULT;
+ pruicss_xchg->enc_len[ls_ch].num_slaves = 1;
+ priv->num_slaves[ls_ch] = 1;
+ priv->multi_turn_len[ls_ch][0] = 0;
+ pruicss_xchg->ctrl_cmd[ls_ch] = 0;
+ }
+ pruicss_xchg->pos_crc_len = BISSC_POS_CRC_LEN;
+ pruicss_xchg->ctrl_cmd_crc_len = BISSC_CTRL_CMD_CRC_LEN;
+ pruicss_xchg->rx_clk_freq = frequency;
+ bissc_update_max_proc_delay(priv, frequency);
+ pruicss_xchg->delay_40us = ((icssgclk*40)/1000000);
+ pruicss_xchg->delay_100ms = (icssgclk / 10); /*((icssgclk*100000) / 1000000)*/
+ pruicss_xchg->icssg_clk = icssgclk;
+ pruicss_xchg->valid_bit_idx = 24;
+ pruicss_xchg->measure_proc_delay = 1;
+ pruicss_xchg->execution_state[0] = 0;
+ pruicss_xchg->execution_state[1] = 0;
+ pruicss_xchg->execution_state[2] = 0;
+}
+
+void bissc_update_data_len(struct bissc_priv *priv, uint32_t single_turn_len[], uint32_t multi_turn_len[], int32_t pru_num)
+{
+ struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
+ uint32_t sl_num, ls_ch;
+ if(priv->load_share)
+ ls_ch = priv->channel[pru_num];
+ else
+ ls_ch = 0;
+ for( sl_num = 0; sl_num < NUM_SLAVE_MAX; sl_num++)
+ {
+ if(single_turn_len[sl_num])
+ {
+ priv->single_turn_len[ls_ch][sl_num] = single_turn_len[sl_num];
+ priv->multi_turn_len[ls_ch][sl_num] = multi_turn_len[sl_num];
+ priv->data_len[ls_ch][sl_num] = single_turn_len[sl_num] + multi_turn_len[sl_num];
+ pruicss_xchg->enc_len[ls_ch].data_len[sl_num] = single_turn_len[sl_num] + multi_turn_len[sl_num];
+ priv->num_slaves[ls_ch]++;
+ }
+ }
+ pruicss_xchg->enc_len[0].num_slaves = priv->num_slaves[0];
+ pruicss_xchg->enc_len[1].num_slaves = priv->num_slaves[1];
+ pruicss_xchg->enc_len[2].num_slaves = priv->num_slaves[2];
+}
+
+int32_t bissc_set_ctrl_cmd_and_process(struct bissc_priv *priv, uint32_t ctrl_cmd[])
+{
+ struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
+ pruicss_xchg->ctrl_cmd[0] = ctrl_cmd[0];
+ pruicss_xchg->ctrl_cmd[1] = ctrl_cmd[1];
+ pruicss_xchg->ctrl_cmd[2] = ctrl_cmd[2];
+ int32_t ch = 0, ch_num;
+ if(priv->load_share){
+ pruicss_xchg->ctrl_cmd_status[0] = (pruicss_xchg->channel & 0x1)?1:0;
+ pruicss_xchg->ctrl_cmd_status[1] = (pruicss_xchg->channel & 0x2)?1:0;
+ pruicss_xchg->ctrl_cmd_status[2] = (pruicss_xchg->channel & 0x4)?1:0;
+ while(pruicss_xchg->ctrl_cmd_status[0] + pruicss_xchg->ctrl_cmd_status[1] + pruicss_xchg->ctrl_cmd_status[2])
+ {
+ if(bissc_command_process(priv) < 0)
+ {
+ return SystemP_FAILURE;
+ }
+ ClockP_usleep(1000);
+ }
+ }
+ else{
+ pruicss_xchg->ctrl_cmd_status[0] = 1;
+ while(pruicss_xchg->ctrl_cmd_status[0] & 1)
+ {
+ if(bissc_command_process(priv) < 0)
+ {
+ return SystemP_FAILURE;
+ }
+ ClockP_usleep(1000);
+ }
+ }
+ /*supplying 2 extra cycles for ctrl communication stop bit */
+ bissc_command_process(priv);
+ ClockP_usleep(1000);
+ bissc_command_process(priv);
+ ClockP_usleep(1000);
+ for(ch_num = 0; ch_num < priv->totalchannels; ch_num++)
+ {
+ ch = priv->channel[ch_num];
+ priv->enc_ctrl_data[ch].cmd_result = pruicss_xchg->ctrl_res[ch].ctrl_cds_res;
+ priv->enc_ctrl_data[ch].cmd_rcv_crc = pruicss_xchg->ctrl_res[ch].ctrl_rcvd_crc;
+ priv->enc_ctrl_data[ch].cmd_otf_crc = pruicss_xchg->ctrl_res[ch].ctrl_otf_crc;
+ priv->ctrl_crc_err_cnt[ch] = pruicss_xchg->ctrl_res[ch].ctrl_crc_err_cnt;
+ }
+ return SystemP_SUCCESS;
+}
diff --git a/source/position_sense/bissc/firmware/bissc_diagnostic.cmd b/source/position_sense/bissc/firmware/bissc_diagnostic.cmd
new file mode 100644
index 0000000..3d7c8fd
--- /dev/null
+++ b/source/position_sense/bissc/firmware/bissc_diagnostic.cmd
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+MEMORY
+{
+ PAGE 0:
+ PRUIMEM: o = 0x00000000 l = 0x00001800 /* 6kB PRU Instruction RAM */
+ PAGE 1:
+ PRUDMEM: o = 0x00000000 l = 0x00002000 /* 8kB PRU Data RAM */
+}
+
+SECTIONS
+{
+ .text > PRUIMEM, PAGE 0
+}
diff --git a/source/position_sense/bissc/firmware/bissc_icss_reg_defs.h b/source/position_sense/bissc/firmware/bissc_icss_reg_defs.h
new file mode 100644
index 0000000..f8cd577
--- /dev/null
+++ b/source/position_sense/bissc/firmware/bissc_icss_reg_defs.h
@@ -0,0 +1,95 @@
+
+;
+; Copyright (C) 2023 Texas Instruments Incorporated
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions
+; are met:
+;
+; Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+;
+; Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the
+; distribution.
+;
+; Neither the name of Texas Instruments Incorporated nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+
+;************************************************************************************
+;* File: bissc_icss_reg_defs.h *
+;* *
+;* Brief: Defining R30, R31 register bits as specific status bits for different*
+;* channels. *
+;* Defining the Clock Modes with their respective values *
+;************************************************************************************
+
+ .include "../../../../mcu_plus_sdk/source/pru_io/firmware/common/icss_regs.inc"
+ .include "../../../../mcu_plus_sdk/source/pru_io/firmware/common/icss_cfg_regs.inc"
+
+ .asg R30.t24, BISSC_CH0_RX_EN
+ .asg R31.t27, BISSC_CH0_RX_CLR_OVF
+ .asg R31.t24, BISSC_CH0_RX_CLR_VALID
+ .asg R31.t27, BISSC_CH0_RX_OVF
+ .asg R31.t24, BISSC_CH0_RX_VALID
+
+ .asg R30.t25, BISSC_CH1_RX_EN
+ .asg R31.t28, BISSC_CH1_RX_CLR_OVF
+ .asg R31.t25, BISSC_CH1_RX_CLR_VALID
+ .asg R31.t28, BISSC_CH1_RX_OVF
+ .asg R31.t25, BISSC_CH1_RX_VALID
+
+ .asg R30.t26, BISSC_CH2_RX_EN
+ .asg R31.t29, BISSC_CH2_RX_CLR_OVF
+ .asg R31.t26, BISSC_CH2_RX_CLR_VALID
+ .asg R31.t29, BISSC_CH2_RX_OVF
+ .asg R31.t26, BISSC_CH2_RX_VALID
+
+
+; Channel select bits R30[17:16]
+BISSC_TX_CH0_SEL .set 0
+BISSC_TX_CH1_SEL .set 1
+BISSC_TX_CH2_SEL .set 2
+
+; CLK MODE bits R30[20:19]
+BISSC_TX_CLK_MODE_FREERUN_STOPLOW .set (0 << 3)
+BISSC_TX_CLK_MODE_FREERUN_STOPHIGH .set (1 << 3)
+BISSC_TX_CLK_MODE_FREERUN .set (2 << 3)
+BISSC_TX_CLK_MODE_STOPHIGH_AFTER_TX .set (3 << 3)
+
+ .asg R31.t18, BISSC_TX_CHANNEL_GO
+ .asg R31.t19, BISSC_TX_GLOBAL_REINIT
+ .asg R31.t20, BISSC_TX_GLOBAL_GO
+
+ .asg R31.t5, BISSC_CH0_TX_GLOBAL_REINIT_ACTIVE
+ .asg R31.t5, BISSC_CH0_TX_BUSY
+ .asg R31.t0, BISSC_CH0_TX_OVERUN
+ .asg R31.t1, BISSC_CH0_TX_UNDERRUN
+
+ .asg R31.t13, BISSC_CH1_TX_GLOBAL_REINIT_ACTIVE
+ .asg R31.t13, BISSC_CH1_TX_BUSY
+ .asg R31.t8, BISSC_CH1_TX_OVERUN
+ .asg R31.t9, BISSC_CH1_TX_UNDERRUN
+
+ .asg R31.t21, BISSC_CH2_TX_GLOBAL_REINIT_ACTIVE
+ .asg R31.t21, BISSC_CH2_TX_BUSY
+ .asg R31.t16, BISSC_CH2_TX_OVERUN
+ .asg R31.t17, BISSC_CH2_TX_UNDERRUN
+
+
+; BISSC
diff --git a/source/position_sense/bissc/firmware/bissc_interface.h b/source/position_sense/bissc/firmware/bissc_interface.h
new file mode 100644
index 0000000..698ac81
--- /dev/null
+++ b/source/position_sense/bissc/firmware/bissc_interface.h
@@ -0,0 +1,167 @@
+
+;
+; Copyright (C) 2023 Texas Instruments Incorporated
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions
+; are met:
+;
+; Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+;
+; Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the
+; distribution.
+;
+; Neither the name of Texas Instruments Incorporated nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+
+;************************************************************************************
+;* File: bissc_interface.h *
+;* *
+;* Brief: Defining Data Memory Offsets *
+;************************************************************************************
+
+BISSC_POS_CRC_LEN_CONFIG_OFFSET .set 0x0 ;slave data crc length
+BISSC_RX_CLK_FREQ_CONFIG_OFFSET .set 0x1 ;clock freq
+BISSC_CTRL_CMD_CRC_LEN_CONFIG_OFFSET .set 0x2 ;register access crc length
+BISSC_CHANNEL_CONFIG_OFFSET .set 0x3 ;channel config
+
+BISSC_STATUS_CH0_CONFIG_OFFSET .set 0x4 ;Firmware init status for RTU
+BISSC_STATUS_CH1_CONFIG_OFFSET .set 0x5 ;Firmware init status for PRU
+BISSC_STATUS_CH2_CONFIG_OFFSET .set 0x6 ;Firmware init status for TXPRU
+BISSC_MASK_FOR_PRIMARY_CORE .set 0x7 ;mask for core set
+BISSC_CYCLE_TRIGGER_CH0_STATUS_OFFSET .set 0x8 ;Status of current cycle for RTU
+BISSC_CYCLE_TRIGGER_CH1_STATUS_OFFSET .set 0x9 ;Status of current cycle for PRU
+BISSC_CYCLE_TRIGGER_CH2_STATUS_OFFSET .set 0xA ;Status of current cycle for TXPRU
+BISSC_MEAS_PROC_DELAY_OFFSET .set 0xB ;Measure proc delay and line delay, set when there is a change in config
+
+BISSC_NUM_SLAVE_CH0_CONFIG_OFFSET .set 0xC ;number of slaves connected in daisy chain
+BISSC_DATA_LEN_CH0_CONFIG_OFFSET .set 0xD ;slave 0 data length
+BISSC_DATA_LEN_SLAVE1_CH0_CONFIG_OFFSET .set 0xE ;slave 1 data length
+BISSC_DATA_LEN_SLAVE2_CH0_CONFIG_OFFSET .set 0xF ;slave 2 data length
+
+BISSC_NUM_SLAVE_CH1_CONFIG_OFFSET .set 0x10 ;number of slaves connected in daisy chain
+BISSC_DATA_LEN_CH1_CONFIG_OFFSET .set 0x11 ;slave 0 data length
+BISSC_DATA_LEN_SLAVE1_CH1_CONFIG_OFFSET .set 0x12 ;slave 1 data length
+BISSC_DATA_LEN_SLAVE2_CH1_CONFIG_OFFSET .set 0x13 ;slave 2 data length
+
+BISSC_NUM_SLAVE_CH2_CONFIG_OFFSET .set 0x14 ;number of slaves connected in daisy chain
+BISSC_DATA_LEN_CH2_CONFIG_OFFSET .set 0x15 ;slave 0 data length
+BISSC_DATA_LEN_SLAVE1_CH2_CONFIG_OFFSET .set 0x16 ;slave 1 data length
+BISSC_DATA_LEN_SLAVE2_CH2_CONFIG_OFFSET .set 0x17 ;slave 2 data length
+
+BISSC_VALID_BIT_IDX_OFFSET .set 0x18 ;offset for valid bit index
+BISSC_FIFO_BIT_IDX_OFFSET .set 0x19 ;offset for fifo bit index
+BISSC_CTRL_CMD_CH0_STATUS_OFFSET .set 0x1A ;control command complete status; 1 - pending; 0 - completed
+BISSC_CTRL_CMD_CH1_STATUS_OFFSET .set 0x1B ;control command complete status; 1 - pending; 0 - completed
+BISSC_CTRL_CMD_CH2_STATUS_OFFSET .set 0x1C ;control command complete status; 1 - pending; 0 - completed
+
+BISSC_CH0_PROC_DELAY_OFFSET .set 0x1E ;Measured Processing delay for ch0
+BISSC_CH1_PROC_DELAY_OFFSET .set 0x20 ;Measured Processing delay for ch1
+BISSC_CH2_PROC_DELAY_OFFSET .set 0x22 ;Measured Processing delay for ch2
+
+
+BISSC_CTRL_CMD_CH0_CONFIG_OFFSET .set 0x24 ;register access commad
+
+BISSC_CTRL_CMD_CH1_CONFIG_OFFSET .set 0x28 ;register access commad
+
+BISSC_CTRL_CMD_CH2_CONFIG_OFFSET .set 0x2C ;register access commad
+
+BISSC_MAX_PROC_DELAY_OFFSET .set 0x30 ;Max Processing delay
+
+BISSC_POS_DATA_RES_SLAVE0_OFFSET .set 0x34 ;position data results offset for slave 0
+BISSC_POS_DATA_RES_SLAVE1_OFFSET .set 0x5C ;position data results offset for slave 1
+BISSC_POS_DATA_RES_SLAVE2_OFFSET .set 0X84 ;position data results offset for slave 2
+
+BISSC_POS_DATA_WORD_CH0_OFFSET .set 0x0 ;position data results offset for ch 0
+BISSC_POS_DATA_WORD_CH1_OFFSET .set 0x8 ;position data results offset for ch 1
+BISSC_POS_DATA_WORD_CH2_OFFSET .set 0x10 ;position data results offset for ch 2
+BISSC_POS_CRC_ERR_COUNT_CH0_OFFSET .set 0x18 ;position data crc error count for ch 0
+BISSC_POS_CRC_ERR_COUNT_CH1_OFFSET .set 0x1C ;position data crc error count for ch 1
+BISSC_POS_CRC_ERR_COUNT_CH2_OFFSET .set 0x20 ;position data crc error count for ch 2
+BISSC_POS_OTF_CRC_CH0_OFFSET .set 0x24 ;position data otf crc for ch 0
+BISSC_POS_OTF_CRC_CH1_OFFSET .set 0x25 ;position data otf crc for ch 1
+BISSC_POS_OTF_CRC_CH2_OFFSET .set 0x26 ;position data otf crc for ch 2
+
+
+BISSC_POSITION_DATA_WORD0_CH0_SLAVE0_OFFSET .set 0X34 ;Lower word of position data from ch0 slave 0
+BISSC_POSITION_DATA_WORD1_CH0_SLAVE0_OFFSET .set 0x38 ;Upper word of position data(0 if length < 32) from ch0 slave 0
+BISSC_POSITION_DATA_WORD0_CH1_SLAVE0_OFFSET .set 0X3C ;Lower word of position data from ch1 slave 0
+BISSC_POSITION_DATA_WORD1_CH1_SLAVE0_OFFSET .set 0x40 ;Upper word of position data(0 if length < 32) from ch1 slave 0
+BISSC_POSITION_DATA_WORD0_CH2_SLAVE0_OFFSET .set 0X44 ;Lower word of position data from ch2 slave 0
+BISSC_POSITION_DATA_WORD1_CH2_SLAVE0_OFFSET .set 0x48 ;Upper word of position data(0 if length < 32) from ch2 slave 0
+BISSC_POS_DATA_CRC_ERROR_COUNT_CH0_SLAVE0_OFFSET .set 0x4C ;offset for position data crc errors of ch0 slave 0
+BISSC_POS_DATA_CRC_ERROR_COUNT_CH1_SLAVE0_OFFSET .set 0x50 ;offset for position data crc errors of ch1 slave 0
+BISSC_POS_DATA_CRC_ERROR_COUNT_CH2_SLAVE0_OFFSET .set 0x54 ;offset for position data crc errors of ch2 slave 0
+BISSC_POS_DATA_OTF_CRC_CH0_SLAVE0_OFFSET .set 0x58 ;6-bit calculated otf pos data CRC of ch0 slave 0
+BISSC_POS_DATA_OTF_CRC_CH1_SLAVE0_OFFSET .set 0x59 ;6-bit calculated otf pos data CRC of ch1 slave 0
+BISSC_POS_DATA_OTF_CRC_CH2_SLAVE0_OFFSET .set 0x5A ;6-bit calculated otf pos data CRC of ch2 slave 0
+
+BISSC_POSITION_DATA_WORD0_CH0_SLAVE1_OFFSET .set 0X5C ;Lower word of position data from ch0 slave 1
+BISSC_POSITION_DATA_WORD1_CH0_SLAVE1_OFFSET .set 0x60 ;Upper word of position data(0 if length < 32) from ch0 slave 1
+BISSC_POSITION_DATA_WORD0_CH1_SLAVE1_OFFSET .set 0X64 ;Lower word of position data from ch1 slave 1
+BISSC_POSITION_DATA_WORD1_CH1_SLAVE1_OFFSET .set 0x68 ;Upper word of position data(0 if length < 32) from ch1 slave 1
+BISSC_POSITION_DATA_WORD0_CH2_SLAVE1_OFFSET .set 0X6C ;Lower word of position data from ch2 slave 1
+BISSC_POSITION_DATA_WORD1_CH2_SLAVE1_OFFSET .set 0x70 ;Upper word of position data(0 if length < 32) from ch2 slave 1
+BISSC_POS_DATA_CRC_ERROR_COUNT_CH0_SLAVE1_OFFSET .set 0x74 ;offset for position data crc errors of ch0 slave 1
+BISSC_POS_DATA_CRC_ERROR_COUNT_CH1_SLAVE1_OFFSET .set 0x78 ;offset for position data crc errors of ch1 slave 1
+BISSC_POS_DATA_CRC_ERROR_COUNT_CH2_SLAVE1_OFFSET .set 0x7C ;offset for position data crc errors of ch2 slave 1
+BISSC_POS_DATA_OTF_CRC_CH0_SLAVE1_OFFSET .set 0x80 ;6-bit calculated otf pos data CRC of ch0 slave 1
+BISSC_POS_DATA_OTF_CRC_CH1_SLAVE1_OFFSET .set 0x81 ;6-bit calculated otf pos data CRC of ch1 slave 1
+BISSC_POS_DATA_OTF_CRC_CH2_SLAVE1_OFFSET .set 0x82 ;6-bit calculated otf pos data CRC of ch2 slave 1
+
+
+BISSC_POSITION_DATA_WORD0_CH0_SLAVE2_OFFSET .set 0X84 ;Lower word of position data from ch0 slave 2
+BISSC_POSITION_DATA_WORD1_CH0_SLAVE2_OFFSET .set 0x88 ;Upper word of position data(0 if length < 32) from ch0 slave 2
+BISSC_POSITION_DATA_WORD0_CH1_SLAVE2_OFFSET .set 0X8C ;Lower word of position data from ch1 slave 2
+BISSC_POSITION_DATA_WORD1_CH1_SLAVE2_OFFSET .set 0x90 ;Upper word of position data(0 if length < 32) from ch1 slave 2
+BISSC_POSITION_DATA_WORD0_CH2_SLAVE2_OFFSET .set 0X94 ;Lower word of position data from ch2 slave 2
+BISSC_POSITION_DATA_WORD1_CH2_SLAVE2_OFFSET .set 0x98 ;Upper word of position data(0 if length < 32) from ch2 slave 2
+BISSC_POS_DATA_CRC_ERROR_COUNT_CH0_SLAVE2_OFFSET .set 0x9C ;offset for position data crc errors of ch0 slave 2
+BISSC_POS_DATA_CRC_ERROR_COUNT_CH1_SLAVE2_OFFSET .set 0xA0 ;offset for position data crc errors of ch1 slave 2
+BISSC_POS_DATA_CRC_ERROR_COUNT_CH2_SLAVE2_OFFSET .set 0xA4 ;offset for position data crc errors of ch2 slave 2
+BISSC_POS_DATA_OTF_CRC_CH0_SLAVE2_OFFSET .set 0xA8 ;6-bit calculated otf pos data CRC of ch0 slave 2
+BISSC_POS_DATA_OTF_CRC_CH1_SLAVE2_OFFSET .set 0xA9 ;6-bit calculated otf pos data CRC of ch1 slave 2
+BISSC_POS_DATA_OTF_CRC_CH2_SLAVE2_OFFSET .set 0xAA ;6-bit calculated otf pos data CRC of ch2 slave 2
+
+BISSC_CH0_CTRL_BASE_OFFSET .set 0xAC ;channel 0 control communication base offset
+
+BISSC_CTRL_CMD_CRC_ERROR_COUNT_OFFSET .set 0x00 ;offset for control command crc errors
+
+BISSC_CTRL_CMD_RESULT_OFFSET .set 0x04 ;8-bit control communication result
+BISSC_CTRL_CMD_DATA_CRC_OFFSET .set 0x05 ;4-bit control communication CRC received
+BISSC_CTRL_CMD_OTF_CRC_OFFSET .set 0x06 ;4-bit otf control communication CRC calculated
+
+BISSC_CH1_CTRL_BASE_OFFSET .set 0xB4 ;channel 1 control communication base offset(ch0 base offset + last defined offset)
+
+BISSC_CH2_CTRL_BASE_OFFSET .set 0xBC ;channel 2 control communication base offset(ch1 base offset + last defined offset)
+
+BISSC_LS_EXEC_RTU_STATE .set 0xC4 ;RTU execution state offset
+BISSC_LS_EXEC_PRU_STATE .set 0xC5 ;PRU execution state offset
+BISSC_LS_EXEC_TXPRU_STATE .set 0xC6 ;TXPRU execution state offset
+
+BISSC_REG_BACKUP .set 0xC8 ;register backup for different channels
+
+BISSC_RE_MEASURE_PROC_DELAY .set 0xE0
+
+BISSC_CONFIG_DELAY_40US_OFFSET .set 0xE4 ;40 micro second delay offest
+
+BISSC_CONFIG_DELAY_100MS_OFFSET .set 0xE8 ;100 milli second delay offset
+
+BISSC_CONFIG_ICSSG_CLK_OFFSET .set 0xF0 ;icssg clock configuration offset
diff --git a/source/position_sense/bissc/firmware/bissc_macros.h b/source/position_sense/bissc/firmware/bissc_macros.h
new file mode 100644
index 0000000..b047a61
--- /dev/null
+++ b/source/position_sense/bissc/firmware/bissc_macros.h
@@ -0,0 +1,910 @@
+;
+; Copyright (C) 2023 Texas Instruments Incorporated
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions
+; are met:
+;
+; Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+;
+; Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the
+; distribution.
+;
+; Neither the name of Texas Instruments Incorporated nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+
+
+;************************************************************************************
+;* File: bissc_macros.h *
+;* *
+;* Brief: Macros for calculating On the Fly CRC of position data and returning *
+;* the CRC status with RAW data *
+;* Macros for call and return(branching) *
+;* Macro for enabling pru cycle counter *
+;* Macro for Measuring processing delay
+;* Macro for synchronizing PRUs in load share. *
+;************************************************************************************
+
+
+ .include "bissc_icss_reg_defs.h"
+ .include "bissc_params.h"
+ .include "bissc_interface.h"
+ .include "firmware_version.h"
+
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+; Macros: CALL, CALL2
+; Branch to defined function and stores the return address.
+; Macros: RET, RET2
+; Returns to address stored in defined registers.
+; Registers:
+; LINK_REG.w0: Holds the address of function specified in CALL macro.
+; LINK_REG.w2: Holds the address of function specified in CALL2 macro.
+;
+; PseudoCode:
+; (start code)
+; 1.Jump to specified function for CALL or CALL2 macros and stores the return
+; address in LINK_REG.w0 or LINK_REG.w2.
+; 2.Returns to address stored in SCRTACH5.w0 or SCRATCH.w2 when RET or RET2 macro is called.
+; (end code)
+;
+; Worst case peak cycle usage: 1
+;
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+CALL .macro function
+ JAL LINK_REG.w0, function
+ .endm
+RET .macro
+ JMP LINK_REG.w0
+ .endm
+
+CALL2 .macro function
+ JAL LINK_REG.w2, function
+ .endm
+RET2 .macro
+ JMP LINK_REG.w2
+ .endm
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+; Macro: M_ENABLE_PRU_CYCLE_COUNTER
+; Enable PRU cycle counter.
+; Registers:
+; SCRATCH2: Holds PRU control configurations.
+;
+; PseudoCode:
+; (start code)
+; 1.Load the ICSS_PRU_CTRL_CONST to SCRATCH2 and SET the 3rd bit to enable PRU cycle counter.
+; 2.Store the updated SCRATCH2 at ICSS_PRU_CTRL_CONST offset in shared memory.
+; (end code)
+;
+; Worst case peak cycle usage: 13
+;
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+
+M_ENABLE_PRU_CYCLE_COUNTER .macro
+ LBCO &SCRATCH2, ICSS_PRU_CTRL_CONST, 0, 4
+ SET SCRATCH2, SCRATCH2, 3
+ SBCO &SCRATCH2, ICSS_PRU_CTRL_CONST, 0, 4
+ .endm
+
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+; Macro: M_BISSC_LS_WAIT_FOR_SYNC
+; Loop till all channels are synchronized in load share mode.
+; Registers:
+; LS_SYNC_STATE: Holds the execution status of individual PRU in load share.
+; SCRATCH1.b1: Holds the combine execution status of all PRUs in load share.
+; SCRATCH2.b0: Holds channel mask.
+;
+; PseudoCode:
+; (start code)
+; 1.Set LS_SYNC_STATE for the PRU which enters this macro.
+; 2.Store the execution state at specific PRU offset.
+; 3.Load the execution state back for all PRUs(in use) and perform 'or' operation for all execution states in SCRATCH1.b1.
+; 4.Check whether execution states and channel mask is equal.
+; 5.Repeat step 3 and 4 till all PRUs(in use) execution state is set.
+; (end code)
+;
+; Worst case peak cycle usage: 14
+;
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+M_BISSC_LS_WAIT_FOR_SYNC .macro
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ LDI LS_SYNC_STATE, 1
+ SBCO &LS_SYNC_STATE, PRUx_DMEM, BISSC_LS_EXEC_RTU_STATE, 1
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ LDI LS_SYNC_STATE, (1<<1)
+ SBCO &LS_SYNC_STATE, PRUx_DMEM, BISSC_LS_EXEC_PRU_STATE, 1
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ LDI LS_SYNC_STATE, (1<<2)
+ SBCO &LS_SYNC_STATE, PRUx_DMEM, BISSC_LS_EXEC_TXPRU_STATE, 1
+ .endif
+ LBCO &SCRATCH1.b0, PRUx_DMEM, BISSC_CHANNEL_CONFIG_OFFSET , 1
+BISSC_IS_SYNCED?:
+ LBCO &LS_SYNC_STATE, PRUx_DMEM, BISSC_LS_EXEC_RTU_STATE, 1
+ MOV SCRATCH1.b1, LS_SYNC_STATE
+ LBCO &LS_SYNC_STATE, PRUx_DMEM, BISSC_LS_EXEC_PRU_STATE, 1
+ OR SCRATCH1.b1, SCRATCH1.b1, LS_SYNC_STATE
+ LBCO &LS_SYNC_STATE, PRUx_DMEM, BISSC_LS_EXEC_TXPRU_STATE, 1
+ OR SCRATCH1.b1, SCRATCH1.b1, LS_SYNC_STATE
+ QBNE BISSC_IS_SYNCED?, SCRATCH1.b1, SCRATCH1.b0
+ .endm
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+; Macro: M_BISSC_CLK_CONFIG
+; Configure Rx, Tx frame sizes at ICSS_CFG_PRUx_BISSC_CHx_CFGx offset specific to channels in use.
+; Registers:
+; mask: Holds the channel mask.
+; reg: Holds the frame sizes.
+; BISSC_ICSSG_CHx_CFG0: Holds the confiugation register offset as per channel.
+;
+; PseudoCode:
+; (start code)
+; 1.Check the channel mask bits for respective numbered channel.
+; 2.Hold the offset for channel in use.
+; 3.Store the reg for the enabled channel at specified offset.
+; (end code)
+;
+; Worst case peak cycle usage: 18
+;
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+
+M_BISSC_CLK_CONFIG .macro mask, reg
+ QBBC BISSC_CLK_CFG_CH1?, mask, 0
+ LDI BISSC_ICSSG_CHx_CFG0, ICSS_CFG_PRUx_BISSC_CH0_CFG0
+ SBCO ®, ICSS_CFG, BISSC_ICSSG_CHx_CFG0, 4
+BISSC_CLK_CFG_CH1?:
+ QBBC BISSC_CLK_CFG_CH2?, mask, 1
+ LDI BISSC_ICSSG_CHx_CFG0, ICSS_CFG_PRUx_BISSC_CH1_CFG0
+ SBCO ®, ICSS_CFG, BISSC_ICSSG_CHx_CFG0, 4
+BISSC_CLK_CFG_CH2?:
+ QBBC BISSC_SKIP_CLK_CFG?, mask, 2
+ LDI BISSC_ICSSG_CHx_CFG0, ICSS_CFG_PRUx_BISSC_CH2_CFG0
+ SBCO ®, ICSS_CFG, BISSC_ICSSG_CHx_CFG0, 4
+BISSC_SKIP_CLK_CFG?:
+ .endm
+;*************************************************************************************************************************************
+; Macro: M_MEASURE_MAX_PROC_TIME
+; Measure the Processing Delay and compensate in the Rx frame size.
+; Registers:
+; SCRATCH3.w2 - Holds Rx frame size
+; SCRATCH3.w0 - Holds Tx frame size
+; SCRATCH.w2 - Holds Processing delay for one BissC Cycle
+; SCRATCH.w0 - Holds Maximum time to wait for encoder to respond then holds maximum processing delay acceptable.
+; SCRATCH2.w0 - Stores the average processing delay for 8 BissC cycles
+; SCRATCH3.b0 - Holds processing delay remeasurement status
+; PseudoCode:
+; (start code)
+; 1.Check for the channel in use and load the register with channel specific parameters.
+; 2.Load the clock mode for selected channels by writing to R30.w2
+; 3.Load the Rx frame size to maximum and decrement upon detecting the valid bits and Tx frame size to 0.
+; 4.Increment the SCRATCH.w2 until start bit is detected then add it to SCRATCH2.w0.
+; 5.If it exceeds the maximum processing delay allowed, then set proc delay remeasure flag and restart the loop from first iteration.
+; 6.Loop the steps 1-4 for 8 times and compensate the average in Rx frame size.
+; 7.If step 5 is encountered the repeat step 6.
+; (end code)
+;
+; Worst case peak cycle usage:
+;**************************************************************************************************************************************
+
+M_MEASURE_MAX_PROC_TIME .macro
+ QBBC BISSC_IS_CH1_IN_USE?, CH_MASK, 0
+ LDI BISSC_ENABLE_CHx_IN_USE, 0
+ LDI VALID_BIT_IDX, BISSC_CH0_VALID_BIT_IDX
+ LDI BISSC_ICSSG_CHx_CFG0, ICSS_CFG_PRUx_BISSC_CH0_CFG0
+ QBA BISSC_PROC_MEASURE_CHN_SEL_CMPLT?
+BISSC_IS_CH1_IN_USE?:
+ QBBC BISSC_IS_CH2_IN_USE?, CH_MASK, 1
+ LDI BISSC_ENABLE_CHx_IN_USE, 1
+ LBCO &FIFO_BIT_IDX, PRUx_DMEM, BISSC_FIFO_BIT_IDX_OFFSET, 1
+ ADD FIFO_BIT_IDX, FIFO_BIT_IDX, 8
+ LDI VALID_BIT_IDX, BISSC_CH1_VALID_BIT_IDX
+ LDI BISSC_ICSSG_CHx_CFG0, ICSS_CFG_PRUx_BISSC_CH1_CFG0
+ QBA BISSC_PROC_MEASURE_CHN_SEL_CMPLT?
+BISSC_IS_CH2_IN_USE?:
+ QBBC BISSC_END_PROC_MEASURE_PER_CH?, CH_MASK, 2
+ LDI BISSC_ENABLE_CHx_IN_USE, 2
+ LBCO &FIFO_BIT_IDX, PRUx_DMEM, BISSC_FIFO_BIT_IDX_OFFSET, 1
+ ADD FIFO_BIT_IDX, FIFO_BIT_IDX, 16
+ LDI VALID_BIT_IDX, BISSC_CH2_VALID_BIT_IDX
+ LDI BISSC_ICSSG_CHx_CFG0, ICSS_CFG_PRUx_BISSC_CH2_CFG0
+BISSC_PROC_MEASURE_CHN_SEL_CMPLT?:
+BISSC_PROC_MEASURE_AGAIN?:
+ LDI SCRATCH2.w0, 0
+ LOOP BISSC_PROC_DELAY_END?, 8
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ M_BISSC_LS_WAIT_FOR_SYNC
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ M_BISSC_LS_WAIT_FOR_SYNC
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ M_BISSC_LS_WAIT_FOR_SYNC
+ .endif
+ QBNE BISSC_IS_CH1_SEL?, BISSC_ENABLE_CHx_IN_USE, 0
+ LDI R30.w2, (BISSC_TX_CLK_MODE_FREERUN_STOPHIGH | BISSC_TX_CH0_SEL)
+ LDI R30.b0, 0 ;Not needed?
+BISSC_IS_CH1_SEL?:
+ QBNE BISSC_IS_CH2_SEL?, BISSC_ENABLE_CHx_IN_USE, 1
+ LDI R30.w2, (BISSC_TX_CLK_MODE_FREERUN_STOPHIGH | BISSC_TX_CH1_SEL)
+ LDI R30.b0, 0 ;Not needed?
+BISSC_IS_CH2_SEL?:
+ QBNE BISSC_SKIP_CH_SEL?, BISSC_ENABLE_CHx_IN_USE, 2
+ LDI R30.w2, (BISSC_TX_CLK_MODE_FREERUN_STOPHIGH | BISSC_TX_CH2_SEL)
+ LDI R30.b0, 0 ;Not needed?
+BISSC_SKIP_CH_SEL?:
+ ; loading rx frame size to maximum bits we can receive from BiSSC encoder
+ LDI SCRATCH3.w2, 256
+ LDI SCRATCH3.w0, 0
+ ; store Rx and Tx frame size to ICSS_CFG_PRUx_ED_CHx for all configured channels
+ SBCO &SCRATCH3, ICSS_CFG, BISSC_ICSSG_CHx_CFG0, 4
+BISSC_PROC_WAIT_TILL_TX_CH_BUSY?
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ QBBC BISSC_SKIP_TX_CH_BUSY?, PRIMARY_CORE, 0
+ LDI SCRATCH1.w0, ICSS_CFG_PRUx_BISSC_TXCFG
+ LBCO &SCRATCH3.b0, ICSS_CFG, SCRATCH1.w0, 1
+ QBBS BISSC_PROC_WAIT_TILL_TX_CH_BUSY?, SCRATCH3.b0, 5
+ LDI SCRATCH3.b0, 0
+ SBCO &SCRATCH3.b0, PRUx_DMEM, BISSC_RE_MEASURE_PROC_DELAY, 1
+ LDI R30.b0, 0
+ SET R31, BISSC_TX_GLOBAL_GO
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ QBBC BISSC_SKIP_TX_CH_BUSY?, PRIMARY_CORE, 1
+ LDI SCRATCH1.w0, ICSS_CFG_PRUx_BISSC_TXCFG
+ LBCO &SCRATCH3.b0, ICSS_CFG, SCRATCH1.w0, 1
+ QBBS BISSC_PROC_WAIT_TILL_TX_CH_BUSY?, SCRATCH3.b0, 6
+ LDI SCRATCH3.b0, 0
+ SBCO &SCRATCH3.b0, PRUx_DMEM, BISSC_RE_MEASURE_PROC_DELAY, 1
+ LDI R30.b0, 0
+ SET R31, BISSC_TX_GLOBAL_GO
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ QBBC BISSC_SKIP_TX_CH_BUSY?, PRIMARY_CORE, 2
+ LDI SCRATCH1.w0, ICSS_CFG_PRUx_BISSC_TXCFG
+ LBCO &SCRATCH3.b0, ICSS_CFG, SCRATCH1.w0, 1
+ QBBS BISSC_PROC_WAIT_TILL_TX_CH_BUSY?, SCRATCH3.b0, 7
+ LDI SCRATCH3.b0, 0
+ SBCO &SCRATCH3.b0, PRUx_DMEM, BISSC_RE_MEASURE_PROC_DELAY, 1
+ LDI R30.b0, 0
+ SET R31, BISSC_TX_GLOBAL_GO
+ .else
+ LDI SCRATCH1.w0, ICSS_CFG_PRUx_BISSC_TXCFG
+ LBCO &SCRATCH3.b0, ICSS_CFG, SCRATCH1.w0, 1
+ QBBS BISSC_PROC_WAIT_TILL_TX_CH_BUSY?, SCRATCH3.b0, 5
+ LDI R30.b0, 0
+ SET R31, BISSC_TX_GLOBAL_GO
+ .endif
+BISSC_SKIP_TX_CH_BUSY?:
+ SET R30, R30, BISSC_RX_EN
+ LDI SCRATCH.w0,10000
+ LDI SCRATCH.w2,0
+
+BISSC_ACK_BIT?:
+ ; wait for valid bit
+ QBBC BISSC_ACK_BIT?, R31, VALID_BIT_IDX
+ ADD SCRATCH.w2,SCRATCH.w2,1
+ QBLT BISSC_END_PROC_ENC_NOT_DETECTED?, SCRATCH.w2, SCRATCH.w0
+ MOV SCRATCH1, R31
+ ;Set the valid bit for clearing flag so that next bit can come.
+ SET R31, R31, BISSC_RX_VALID
+ ;must maintain 3 cycles before checking next valid bit
+ NOP
+ NOP
+ QBBS BISSC_ACK_BIT?, SCRATCH1, FIFO_BIT_IDX
+ SUB SCRATCH3.w2, SCRATCH3.w2, 1
+ LBCO &SCRATCH.w0, PRUx_DMEM, BISSC_MAX_PROC_DELAY_OFFSET, 2
+ LDI SCRATCH.w2,0
+
+ ;start bit
+BISSC_START_BIT?:
+ ; wait for valid bit
+ QBBC BISSC_START_BIT?, R31, VALID_BIT_IDX
+ ADD SCRATCH.w2,SCRATCH.w2,1
+ QBLT BISSC_END_PROC_MAX_PROC_TIME_EXCEEDED?, SCRATCH.w2, SCRATCH.w0
+ MOV SCRATCH1, R31
+ ;Set the valid bit for clearing flag so that next bit can come.
+ SET R31, R31, BISSC_RX_VALID
+ ;must maintain 3 cycles before checking next valid bit
+ NOP
+ NOP
+ QBBC BISSC_START_BIT?, SCRATCH1, FIFO_BIT_IDX
+ SUB SCRATCH3.w2, SCRATCH3.w2, 1
+ ;Accumulate proc time for this iteration
+ ADD SCRATCH2.w0, SCRATCH2.w0, SCRATCH.w2
+ ZERO &SCRATCH1, 4
+ SBCO &SCRATCH1, PRUx_DMEM, BISSC_LS_EXEC_RTU_STATE, 4
+ ;loop here for all data bits
+BISSC_LOOP_OVER_BITS?:
+ ; wait for valid bit
+ QBBC BISSC_LOOP_OVER_BITS?, R31, VALID_BIT_IDX
+ SET R31, R31, BISSC_RX_VALID
+ SUB SCRATCH3.w2, SCRATCH3.w2, 1
+ ;must maintain 3 cycles before checking next valid bit
+ NOP
+ NOP
+ QBNE BISSC_LOOP_OVER_BITS?, SCRATCH3.w2, 0
+
+BISSC_PROC_WAIT_FOR_ALL_CORES?:
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ LBCO &SCRATCH3, PRUx_DMEM, BISSC_LS_EXEC_RTU_STATE, 1
+ QBNE BISSC_PROC_WAIT_FOR_ALL_CORES?, SCRATCH3.b0, 0
+ M_BISSC_LS_WAIT_FOR_SYNC
+ QBBC BISSC_SKIP_GLOBAL_REINIT1?, PRIMARY_CORE, 0
+ SET R31, R31, 19 ;ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low
+ ; rx_en = 0 : Disable RX mode
+ LDI R30.b3, 0
+BISSC_SKIP_GLOBAL_REINIT1?:
+ LBCO &SCRATCH2.b3, PRUx_DMEM, BISSC_RE_MEASURE_PROC_DELAY, 1
+ QBEQ BISSC_PROC_MEASURE_AGAIN?, SCRATCH2.b3, 1
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ LBCO &SCRATCH3, PRUx_DMEM, BISSC_LS_EXEC_PRU_STATE, 1
+ QBNE BISSC_PROC_WAIT_FOR_ALL_CORES?, SCRATCH3.b0, 0
+ M_BISSC_LS_WAIT_FOR_SYNC
+ QBBC BISSC_SKIP_GLOBAL_REINIT1?, PRIMARY_CORE, 1
+ SET R31, R31, 19 ;ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low
+ ; rx_en = 0 : Disable RX mode
+ LDI R30.b3, 0
+BISSC_SKIP_GLOBAL_REINIT1?:
+ LBCO &SCRATCH2.b3, PRUx_DMEM, BISSC_RE_MEASURE_PROC_DELAY, 1
+ QBEQ BISSC_PROC_MEASURE_AGAIN?, SCRATCH2.b3, 1
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ LBCO &SCRATCH3, PRUx_DMEM, BISSC_LS_EXEC_TXPRU_STATE, 1
+ QBNE BISSC_PROC_WAIT_FOR_ALL_CORES?, SCRATCH3.b0, 0
+ M_BISSC_LS_WAIT_FOR_SYNC
+ QBBC BISSC_SKIP_GLOBAL_REINIT1?, PRIMARY_CORE, 2
+ SET R31, R31, 19 ;ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low
+ ; rx_en = 0 : Disable RX mode
+ LDI R30.b3, 0
+BISSC_SKIP_GLOBAL_REINIT1?:
+ LBCO &SCRATCH2.b3, PRUx_DMEM, BISSC_RE_MEASURE_PROC_DELAY, 1
+ QBEQ BISSC_PROC_MEASURE_AGAIN?, SCRATCH2.b3, 1
+ .else
+ SET R31, R31, 19 ;ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low
+ ; rx_en = 0 : Disable RX mode
+ LDI R30.b3, 0
+ .endif
+
+ LBCO &SCRATCH3, PRUx_DMEM, BISSC_CONFIG_DELAY_100MS_OFFSET, 4
+BISSC_DELAY_LOOP?:
+ SUB SCRATCH3, SCRATCH3, 1
+ QBNE BISSC_DELAY_LOOP?, SCRATCH3, 0
+ NOP
+BISSC_PROC_DELAY_END?:
+ LSR SCRATCH2.w0, SCRATCH2.w0, 3
+ QBA BISSC_END_PROC_MEASURE?
+BISSC_END_PROC_ENC_NOT_DETECTED?:
+
+ ZERO &SCRATCH1, 4
+ SBCO &SCRATCH1, PRUx_DMEM, BISSC_LS_EXEC_RTU_STATE, 4
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ M_BISSC_LS_WAIT_FOR_SYNC
+ QBBC BISSC_SKIP_GLOBAL_REINIT2?, PRIMARY_CORE, 0
+ SET R31, R31, 19 ;ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low
+ ; rx_en = 0 : Disable RX mode
+ LDI R30.b3, 0
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ M_BISSC_LS_WAIT_FOR_SYNC
+ QBBC BISSC_SKIP_GLOBAL_REINIT2?, PRIMARY_CORE, 1
+ SET R31, R31, 19 ;ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low
+ ; rx_en = 0 : Disable RX mode
+ LDI R30.b3, 0
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ M_BISSC_LS_WAIT_FOR_SYNC
+ QBBC BISSC_SKIP_GLOBAL_REINIT2?, PRIMARY_CORE, 2
+ SET R31, R31, 19 ;ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low
+ ; rx_en = 0 : Disable RX mode
+ LDI R30.b3, 0
+ .else
+ SET R31, R31, 19 ;ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low
+ ; rx_en = 0 : Disable RX mode
+ LDI R30.b3, 0
+ .endif
+BISSC_SKIP_GLOBAL_REINIT2?:
+ HALT
+
+BISSC_END_PROC_MAX_PROC_TIME_EXCEEDED?:
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ LBCO &SCRATCH, PRUx_DMEM, BISSC_CONFIG_DELAY_100MS_OFFSET, 4 ;100ms delay loop
+BISSC_DELAY_LOOP2?:
+ SUB SCRATCH, SCRATCH, 1
+ QBNE BISSC_DELAY_LOOP2?, SCRATCH, 0
+ LDI SCRATCH2.b3, 1
+ SBCO &SCRATCH2.b3, PRUx_DMEM, BISSC_RE_MEASURE_PROC_DELAY, 1
+ QBA BISSC_PROC_WAIT_FOR_ALL_CORES?
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ LBCO &SCRATCH, PRUx_DMEM, BISSC_CONFIG_DELAY_100MS_OFFSET, 4 ;100ms delay loop
+BISSC_DELAY_LOOP3?:
+ SUB SCRATCH, SCRATCH, 1
+ QBNE BISSC_DELAY_LOOP3?, SCRATCH, 0
+ LDI SCRATCH2.b3, 1
+ SBCO &SCRATCH2.b3, PRUx_DMEM, BISSC_RE_MEASURE_PROC_DELAY, 1
+ QBA BISSC_PROC_WAIT_FOR_ALL_CORES?
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ LBCO &SCRATCH, PRUx_DMEM, BISSC_CONFIG_DELAY_100MS_OFFSET, 4 ;100ms delay loop
+BISSC_DELAY_LOOP4?:
+ SUB SCRATCH, SCRATCH, 1
+ QBNE BISSC_DELAY_LOOP4?, SCRATCH, 0
+ LDI SCRATCH2.b3, 1
+ SBCO &SCRATCH2.b3, PRUx_DMEM, BISSC_RE_MEASURE_PROC_DELAY, 1
+ QBA BISSC_PROC_WAIT_FOR_ALL_CORES?
+ .else
+ SET R31, R31, 19 ;ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low
+ ; rx_en = 0 : Disable RX mode
+ LDI R30.b3, 0
+ LDI SCRATCH2.w0, 0
+ ;Delay loop
+ LBCO &SCRATCH, PRUx_DMEM, BISSC_CONFIG_DELAY_100MS_OFFSET, 4 ;100ms delay loop
+BISSC_DELAY_LOOP1?:
+ SUB SCRATCH, SCRATCH, 1
+ QBNE BISSC_DELAY_LOOP1?, SCRATCH, 0
+ QBA BISSC_PROC_MEASURE_AGAIN?
+ .endif
+BISSC_END_PROC_MEASURE?:
+ QBEQ BISSC_STORE_CH0_PROC_DELAY?, BISSC_ENABLE_CHx_IN_USE, 0
+ QBEQ BISSC_STORE_CH1_PROC_DELAY?, BISSC_ENABLE_CHx_IN_USE, 1
+ SBCO &SCRATCH2.w0, PRUx_DMEM, BISSC_CH2_PROC_DELAY_OFFSET, 2
+ JMP BISSC_END_PROC_MEASURE_PER_CH?
+BISSC_STORE_CH0_PROC_DELAY?:
+ SBCO &SCRATCH2.w0, PRUx_DMEM, BISSC_CH0_PROC_DELAY_OFFSET, 2
+ JMP BISSC_IS_CH1_IN_USE?
+BISSC_STORE_CH1_PROC_DELAY?:
+ SBCO &SCRATCH2.w0, PRUx_DMEM, BISSC_CH1_PROC_DELAY_OFFSET, 2
+ JMP BISSC_IS_CH2_IN_USE?
+BISSC_END_PROC_MEASURE_PER_CH?:
+ LDI SCRATCH1.b1, 0
+ SBCO &SCRATCH1.b1, PRUx_DMEM, BISSC_MEAS_PROC_DELAY_OFFSET, 1
+ .endm
+
+
+
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+; Macro: M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC
+; Receive and Downample the position data and do not invoke for CRC bits.
+; Registers:
+; Rx: Holds the raw data received - caller has to zero or provide value to continue
+; valid_bit: Holds the valid bit for selected channel.
+; bit_idx: Holds the bit index(middle bit of oversampled data) of rx fifo.
+; cnt: Number of bits to receive which should be less than less than 32 as we are returning only one register Rx
+; ex: Temporary variable
+;
+; PseudoCode:
+; (start code)
+; 1.Left shift the Rx and Wait for valid bit then check the Middle Bit of Rx fifo and store the same in Rx.
+; 2.Do the On the fly crc algorithm for received bit.
+; 3.Loop through the steps 1-2 for cnt iterations.
+; (end code)
+;
+; Worst case peak cycle usage: 14(each iteration)
+;
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+
+M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC .macro Rx, cnt, bit_idx, ff0, ff1, ff2, ff3, ff4, ff5, ex
+
+ LOOP BISSC_RX_RECEIVE_DOWNSAMPLE_CRC_LOOP?, cnt ; Run loop for receive bits
+ LSL Rx, Rx, 1
+WB1?:
+ AND SCRATCH.b0, R31.b3, CH_MASK
+ QBNE WB1?, SCRATCH.b0, CH_MASK ; wait for valid
+ QBBS BISSC_SET_POS_BIT_CHx?, R31, bit_idx ; Check the Mid bit of received oversampled data
+ MOV ex, ff5 ; if code[i] = 0, ex = ff5 (ex = ff5 ^ 0)
+ JMP BISSC_SKIP_POS_BIT_CHx?
+BISSC_SET_POS_BIT_CHx?:
+ NOT ex, ff5 ; if code[i] = 1, ex = !ff5 (ex = ff5 ^ 1)
+ OR Rx, Rx, 1
+BISSC_SKIP_POS_BIT_CHx?:
+ MOV R31.b3, SCRATCH.b0 ; clear valid bit
+ MOV ff5, ff4
+ MOV ff4, ff3
+ MOV ff3, ff2
+ MOV ff2, ff1
+ XOR ff1, ff0, ex
+ MOV ff0, ex
+BISSC_RX_RECEIVE_DOWNSAMPLE_CRC_LOOP?:
+ .endm
+
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+; Macro: M_OTF_RECEIVE_DOWNSAMPLE
+; Receive and Downample the CRC bits.
+; Registers:
+; Rx: Holds the raw data received - caller has to zero or provide value to continue
+; Ry: Holds received CRC
+; valid_bit: Holds the valid bit for selected channel.
+; bit_idx: Holds the bit index(middle bit of oversampled data) of rx fifo.
+; cnt: Number of bits to receive which should be 6 as we are receiving the CRC.
+;
+; PseudoCode:
+; (start code)
+; 1.Left shift Rx, Ry and Wait for valid bit then check the Middle Bit of Rx fifo and store the same in Rx and Ry.
+; 2.Clear the valid bit
+; 3.Loop through the steps 1-2 for cnt iterations.
+; (end code)
+;
+; Worst case peak cycle usage: 10(each iteration)
+;
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+
+M_OTF_RECEIVE_AND_DOWNSAMPLE .macro Rx, Ry, cnt, bit_idx
+ LOOP BISSC_RX_RECEIVE_DOWNSAMPLE_LOOP?, cnt ; Run loop for receive bits
+ LSL Rx, Rx, 1
+ LSL Ry, Ry, 1
+WB2?:
+ AND SCRATCH.b0, R31.b3, CH_MASK
+ QBNE WB2?, SCRATCH.b0, CH_MASK ; wait for valid
+ QBBS BISSC_SET_CRC_BIT_CHx?, R31, bit_idx ; Check the Mid bit of received oversampled data
+ QBA BISSC_SKIP_CRC_BIT_CHx?
+BISSC_SET_CRC_BIT_CHx?:
+ OR Rx, Rx, 1
+ OR Ry, Ry, 1
+BISSC_SKIP_CRC_BIT_CHx?:
+ MOV R31.b3, SCRATCH.b0 ; clear valid bit
+BISSC_RX_RECEIVE_DOWNSAMPLE_LOOP?:
+ .endm
+
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+; Macro: M_CALC_CRC
+; Store and return the calculated CRC.
+; Registers:
+; ff[0-5]: Holds calculated CRC bits separately
+; crc: Returns the overall CRC computation value.
+;
+; PseudoCode:
+; (start code)
+; 1.Load crc with 0
+; 2.Check for individual bit(bit-0) from ff[0-5]
+; 3.Set the bits required to be high in crc
+; 4.Repeat step 2 and 3 for 6 ff.
+; (end code)
+;
+; Worst case peak cycle usage: 13
+;
+ ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+
+M_CALC_CRC .macro crc, ff0, ff1, ff2, ff3, ff4, ff5
+ LDI crc, 0
+ QBBS BISSC_CRC_BIT1?, ff0, 0
+ SET crc, crc, 0
+BISSC_CRC_BIT1?:
+ QBBS BISSC_CRC_BIT2?, ff1, 0
+ SET crc, crc, 1
+BISSC_CRC_BIT2?:
+ QBBS BISSC_CRC_BIT3?, ff2, 0
+ SET crc, crc, 2
+BISSC_CRC_BIT3?:
+ QBBS BISSC_CRC_BIT4?, ff3, 0
+ SET crc, crc, 3
+BISSC_CRC_BIT4?:
+ QBBS BISSC_CRC_BIT5?, ff4, 0
+ SET crc, crc, 4
+BISSC_CRC_BIT5?:
+ QBBS BISSC_CRC_END?, ff5, 0
+ SET crc, crc, 5
+BISSC_CRC_END?:
+ .endm
+
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+; Macro: M_OTF_RECEIVE
+; Receive and downsaple the raw data then calculate the CRC.
+; Registers:
+; Ra, Rb: Holds the raw data received - caller has to zero or provide value to continue
+; SCRATCH3.b3: rx_size
+; RAW_DATA_LEN: position data length with crc and error warning length
+; ff[0-5]: FF0to3_0, FF4_0, FF5_0 - otf crc calculation.
+; BISSC_RCV_CRC: used for ex and returns the otf crc results.
+;
+; PseudoCode:
+; (start code)
+; 1.Load ff[0-5] to 0 .
+; 2.Receive position data Ra and Rb with respect to the data length and Register length by calling onto
+; M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC.
+; 3.Receive CRC bits into Rb and BISSC_RCV_CRC_0.
+; 4.Load the Calculated CRC result in SCRATCH3.b3 by calling onto M_CALC_CRC.
+; 5.Store the position data and crc to thier respective offsets and check for CRC validation between BISSC_RCV_CRC_0 and SCRATCH3.b3.
+; 6.Increment the error counter if CRC not matched.
+; (end code)
+;
+; Worst case peak cycle usage: 920
+; REVISIT: More optimization may be required or can be done at least in M_INIT_CRC_FLIP_FLOPS - defer those till a requirement comes
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+
+M_OTF_RECEIVE .macro Ra, Rb, slave_offset
+ ZERO &FF0, 6
+ ; initialize CRC flip-flops, i.e. ff[0-5] = 0
+ SUB SCRATCH3.b3, RAW_DATA_LEN, 6 ; pos data + e+ w
+ ; receive data
+ QBGE BISSC_RX_LE_32_BITS?, SCRATCH3.b3, 32
+ M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC Ra, 32, FIFO_BIT_IDX, FF0.b0, FF0.b1, FF0.b2, FF0.b3, FF1.b0, FF1.b1, EX.b0
+ SUB SCRATCH3.b3, RAW_DATA_LEN, (32 + 6) ; note taking care of CRC bits
+ M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC Rb, SCRATCH3.b3, FIFO_BIT_IDX, FF0.b0, FF0.b1, FF0.b2, FF0.b3, FF1.b0, FF1.b1, EX.b0
+ LDI BISSC_RCV_CRC.b0, 0 ; clear crc_recvd
+ LDI SCRATCH3.b3, 6 ; CRC length, assuming 6 bit crc
+ M_OTF_RECEIVE_AND_DOWNSAMPLE Rb,BISSC_RCV_CRC.b0, SCRATCH3.b3, FIFO_BIT_IDX
+ JMP BISSC_RX_CRC?
+
+BISSC_RX_LE_32_BITS?:
+ M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC Ra, SCRATCH3.b3, FIFO_BIT_IDX, FF0.b0, FF0.b1, FF0.b2, FF0.b3, FF1.b0, FF1.b1, EX.b0
+ LDI BISSC_RCV_CRC.b0, 0 ; clear crc_recvd
+ RSB SCRATCH3.b3, SCRATCH3.b3, 32
+ MIN SCRATCH3.b3, SCRATCH3.b3, 6 ; CRC length, assuming 6 bit crc
+ M_OTF_RECEIVE_AND_DOWNSAMPLE Ra, BISSC_RCV_CRC.b0, SCRATCH3.b3, FIFO_BIT_IDX
+ QBEQ BISSC_RX_CRC?, SCRATCH3.b3, 6
+ RSB SCRATCH3.b3, SCRATCH3.b3, 6 ; CRC length, assuming 6 bit crc
+ M_OTF_RECEIVE_AND_DOWNSAMPLE Rb, BISSC_RCV_CRC.b0, SCRATCH3.b3, FIFO_BIT_IDX
+
+BISSC_RX_CRC?:
+ ADD SLAVE_OFFSET, SCRATCH2.b0, SCRATCH2.b3
+ SBCO &Ra, PRUx_DMEM, SLAVE_OFFSET, 8
+ ADD SLAVE_OFFSET, SCRATCH2.b0, SCRATCH2.b1
+ M_CALC_CRC SCRATCH3.b3, FF0.b0, FF0.b1, FF0.b2, FF0.b3, FF1.b0, FF1.b1
+
+ QBEQ BISSC_CRC_SUCCESS?, SCRATCH3.b3, BISSC_RCV_CRC.b0 ; crc: calculated - SCRATCH3.b3, received - BISSC_RCV_CRC_0
+ LBCO &SCRATCH, PRUx_DMEM, SLAVE_OFFSET, 4
+ ADD SCRATCH, SCRATCH, 1
+ SBCO &SCRATCH, PRUx_DMEM, SLAVE_OFFSET , 4
+
+BISSC_CRC_SUCCESS?:
+ ADD SLAVE_OFFSET, SCRATCH2.b0, SCRATCH2.b2
+ SBCO &SCRATCH3.b3, PRUx_DMEM, SLAVE_OFFSET , 1
+ .endm
+
+
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+; Macro: M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC_MC
+; Receive and Downample the position data for multi channel and do not invoke for CRC bits.
+; Registers:
+; Rx, Ry, Rz: Holds the raw data received for all channels- caller has to zero or provide value to continue.
+; ff0 - ff5: flip flops for otf crc calculation.
+; bit_idx: Holds the bit index(middle bit of oversampled data) of rx fifo.
+; cnt: Number of bits to receive which should be less than less than 32 as we are returning only one register per channel.
+; ex: Temporary variable.
+;
+; PseudoCode:
+; (start code)
+; 1.Left shift the Rx, Ry, Rz and Wait for valid bit then check the Middle Bit of Rx fifo for all channels and store the same in Rx, Ry, Rz.
+; 2.Do the On the fly crc algorithm for received bits.
+; 3.Loop through the steps 1-2 for cnt iterations.
+; (end code)
+;
+; Worst case peak cycle usage: 22(each iteration)
+;
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+
+M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC_MC .macro Rx, Ry, Rz, cnt, bit_idx, ff0, ff1, ff2, ff3, ff4, ff5, ex
+ LOOP BISSC_RX_RECEIVE_DOWNSAMPLE_CRC_LOOP?, cnt ; Run loop for receive bits
+ LSL Rx, Rx, 1
+ LSL Ry, Ry, 1
+ LSL Rz, Rz, 1
+WB1?:
+ AND SCRATCH.b0, R31.b3, CH_MASK
+ QBNE WB1?, SCRATCH.b0, CH_MASK ; wait for valid
+
+ QBBS BISSC_SET_POS_BIT_CH0?, R31.b0, bit_idx ; Check the Mid bit of received oversampled data
+ MOV ex.b0, ff5.b0 ; if code[i] = 0, ex = ff5 (ex = ff4 ^ 0)
+ JMP BISSC_SKIP_POS_BIT_CH0?
+BISSC_SET_POS_BIT_CH0?:
+ NOT ex.b0, ff5.b0 ; if code[i] = 1, ex = !ff4 (ex = ff4 ^ 1)
+ OR Rx, Rx, 1
+BISSC_SKIP_POS_BIT_CH0?:
+
+ QBBS BISSC_SET_POS_BIT_CH1?, R31.b1, bit_idx ; Check the Mid bit of received oversampled data
+ MOV ex.b1, ff5.b1 ; if code[i] = 0, ex = ff4 (ex = ff4 ^ 0)
+ JMP BISSC_SKIP_POS_BIT_CH1?
+BISSC_SET_POS_BIT_CH1?:
+ NOT ex.b1, ff5.b1 ; if code[i] = 1, ex = !ff4 (ex = ff4 ^ 1)
+ OR Ry, Ry, 1
+BISSC_SKIP_POS_BIT_CH1?:
+
+ QBBS BISSC_SET_POS_BIT_CH2?, R31.b2, bit_idx ; Check the Mid bit of received oversampled data
+ MOV ex.b2, ff5.b2 ; if code[i] = 0, ex = ff4 (ex = ff4 ^ 0)
+ JMP BISSC_SKIP_POS_BIT_CH2?
+BISSC_SET_POS_BIT_CH2?:
+ NOT ex.b2, ff5.b2 ; if code[i] = 1, ex = !ff4 (ex = ff4 ^ 1)
+ OR Rz, Rz, 1
+BISSC_SKIP_POS_BIT_CH2?:
+
+ MOV R31.b3, SCRATCH.b0 ; clear valid bit
+ MOV ff5, ff4
+ MOV ff4, ff3
+ MOV ff3, ff2
+ MOV ff2, ff1
+ XOR ff1, ff0, ex
+ MOV ff0, ex
+BISSC_RX_RECEIVE_DOWNSAMPLE_CRC_LOOP?:
+ .endm
+
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+; Macro: M_OTF_RECEIVE_DOWNSAMPLE_MC
+; Receive and Downample the CRC bits for multi channel.
+; Registers:
+; Rx, Ry, Rz: Holds the raw data received for all channels - caller has to zero or provide value to continue
+; Ra: Holds received CRC for all channels.
+; bit_idx: Holds the bit index(middle bit of oversampled data) of rx fifo.
+; cnt: Number of bits to receive which should be 6 as we are receiving the CRC.
+;
+; PseudoCode:
+; (start code)
+; 1.Left shift Rx, Ry, Rz, Ra and Wait for valid bit then check the Middle Bit of Rx fifo for all channels and store the same in Rx, Ry, Rz and Ra.
+; 2.Clear the valid bit
+; 3.Loop through the steps 1-2 for cnt iterations.
+; (end code)
+;
+; Worst case peak cycle usage: 18(each iteration)
+;
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+
+M_OTF_RECEIVE_AND_DOWNSAMPLE_MC .macro Rx, Ry, Rz, Ra, cnt, bit_idx
+ LOOP BISSC_RX_RECEIVE_DOWNSAMPLE_LOOP?, cnt ; Run loop for receive bits
+ LSL Rx, Rx, 1
+ LSL Ry, Ry, 1
+ LSL Rz, Rz, 1
+ LSL Ra, Ra, 1 ; this will do for all 3 channels
+WB2?:
+ AND SCRATCH.b0, R31.b3, CH_MASK
+ QBNE WB2?, SCRATCH.b0, CH_MASK ; wait for valid
+
+ QBBS BISSC_SET_CRC_BIT_CH0?, R31.b0, bit_idx ; Check the Mid bit of received oversampled data
+ JMP BISSC_SKIP_CRC_BIT_CH0?
+BISSC_SET_CRC_BIT_CH0?:
+ OR Rx, Rx, 1
+ OR Ra.b0, Ra.b0, 1
+BISSC_SKIP_CRC_BIT_CH0?:
+
+ QBBS BISSC_SET_CRC_BIT_CH1?, R31.b1, bit_idx ; Check the Mid bit of received oversampled data
+ JMP BISSC_SKIP_CRC_BIT_CH1?
+BISSC_SET_CRC_BIT_CH1?:
+ OR Ry, Ry, 1
+ OR Ra.b1, Ra.b1, 1
+BISSC_SKIP_CRC_BIT_CH1?:
+
+ QBBS BISSC_SET_CRC_BIT_CH2?, R31.b2, bit_idx ; Check the Mid bit of received oversampled data
+ JMP BISSC_SKIP_CRC_BIT_CH2?
+BISSC_SET_CRC_BIT_CH2?:
+ OR Rz, Rz, 1
+ OR Ra.b2, Ra.b2, 1
+BISSC_SKIP_CRC_BIT_CH2?:
+
+ MOV R31.b3, SCRATCH.b0 ; clear valid bit
+BISSC_RX_RECEIVE_DOWNSAMPLE_LOOP?:
+ .endm
+
+
+
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+; Macro: M_CALC_CRC
+; Store and return the calculated CRC for all channels.
+; Registers:
+; ff[0-5]: Holds calculated CRC bits separately for all channels.
+; crc: Returns the overall CRC computation value.
+;
+; PseudoCode:
+; (start code)
+; 1.Load crc with 0
+; 2.Left shift ff0-5 and crc by 1 byte, ch2 data will be available in b3 for ff0-5,
+; ch2 data will overflow and ch1 data will be available in b3 for next iteration.
+; 3.Check for individual bit(bit-0) from ff[0-5]
+; 4.Set the bits required to be high in crc
+; 5.Repeat step 2 and 4 for 6 ff.
+; (end code)
+;
+; Worst case peak cycle usage:1+20(each iteration)
+;
+ ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+
+M_CALC_CRC_MC .macro crc, ff0, ff1, ff2, ff3, ff4, ff5
+ ZERO &crc, 4
+
+ LOOP BISSC_CRC_CH0_END?, 3
+
+ LSL ff0, ff0, 8
+ LSL ff1, ff1, 8
+ LSL ff2, ff2, 8
+ LSL ff3, ff3, 8
+ LSL ff4, ff4, 8
+ LSL ff5, ff5, 8
+
+ ; ch2 would be initially in b0, at the end of the loop it would have reached b2, finally ch[0-2] would end up @b[0-2] as reqd.
+ ; no-op in first interation
+ LSL crc, crc, 8
+
+ QBBS BISSC_CRC_CH0_BIT1?, ff0.b3, 0
+ SET crc.b0, crc.b0, 0
+BISSC_CRC_CH0_BIT1?:
+ QBBS BISSC_CRC_CH0_BIT2?, ff1.b3, 0
+ SET crc.b0, crc.b0, 1
+BISSC_CRC_CH0_BIT2?:
+ QBBS BISSC_CRC_CH0_BIT3?, ff2.b3, 0
+ SET crc.b0, crc.b0, 2
+BISSC_CRC_CH0_BIT3?:
+ QBBS BISSC_CRC_CH0_BIT4?, ff3.b3, 0
+ SET crc.b0, crc.b0, 3
+BISSC_CRC_CH0_BIT4?:
+ QBBS BISSC_CRC_CH0_BIT5?, ff4.b3, 0
+ SET crc.b0, crc.b0, 4
+BISSC_CRC_CH0_BIT5?:
+ QBBS BISSC_CRC_CH0_END?, ff5.b3, 0
+ SET crc.b0, crc.b0, 5
+BISSC_CRC_CH0_END?:
+ .endm
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+; Macro: M_OTF_RECEIVE_MC
+; Receive and downsaple the raw data then calculate the CRC for multichannel.
+; Registers:
+; Ra, Rb, Rc, Rd, Re, Rf: Holds the raw data received - caller has to zero or provide value to continue
+; SCRATCH3.b3: rx_size
+; RAW_DATA_LEN: position data length with crc and error warning length
+; ff[0-5]: FF0to3_0, FF4_0, FF5_0 - otf crc calculation.
+; BISSC_RCV_CRC_0: used for ex and returns the otf crc results.
+;
+; PseudoCode:
+; (start code)
+; 1.Load ff[0-5] to 0 .
+; 2.Receive position data Ra and Rb with respect to the data length and Register length by calling onto
+; M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC.
+; 3.Receive CRC bits into Rb and BISSC_RCV_CRC_0.
+; 4.Load the Calculated CRC result in SCRATCH3.b3 by calling onto M_CALC_CRC.
+; 5.Store the position data and crc to thier respective offsets and check for CRC validation between BISSC_RCV_CRC_0 and SCRATCH3.b3.
+; 6.Increment the error counter if CRC not matched.
+; (end code)
+;
+; Worst case peak cycle usage: 1530
+; REVISIT: More optimization may be required or can be done at least in M_INIT_CRC_FLIP_FLOPS - defer those till a requirement comes
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
+
+M_OTF_RECEIVE_MC .macro Ra, Rb, Rc, Rd, Re, Rf, slave_offset
+
+ ; initialize CRC flip-flops, i.e. ff[0-5] = 0
+ ZERO &FF0, 24
+ SUB SCRATCH3.b3, RAW_DATA_LEN, 6 ; pos data + e+ w
+ ; receive data
+ QBGE BISSC_RX_LE_32_BITS?, SCRATCH3.b3, 32
+ M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC_MC Ra, Rc, Re, 32, FIFO_BIT_IDX, FF0, FF1, FF2, FF3, FF4, FF5, EX
+ SUB SCRATCH3.b3, RAW_DATA_LEN, (32 + 6) ; note taking care of CRC bits
+ M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC_MC Rb, Rd, Rf, SCRATCH3.b3, FIFO_BIT_IDX, FF0, FF1, FF2, FF3, FF4, FF5, EX
+ LDI BISSC_RCV_CRC, 0 ; clear crc_recvd
+ M_OTF_RECEIVE_AND_DOWNSAMPLE_MC Rb, Rd, Rf, BISSC_RCV_CRC, 6, FIFO_BIT_IDX
+ JMP BISSC_RX_CRC?
+
+BISSC_RX_LE_32_BITS?:
+ M_OTF_RECEIVE_DOWNSAMPLE_AND_CRC_MC Ra, Rc, Re, SCRATCH3.b3, FIFO_BIT_IDX, FF0, FF1, FF2, FF3, FF4, FF5, EX
+ RSB SCRATCH3.b3, SCRATCH3.b3, 32
+ MIN SCRATCH3.b3, SCRATCH3.b3, 6 ; CRC length, assuming 6 bit crc
+ LDI BISSC_RCV_CRC, 0
+ M_OTF_RECEIVE_AND_DOWNSAMPLE_MC Ra, Rc, Re, BISSC_RCV_CRC, SCRATCH3.b3, FIFO_BIT_IDX
+ QBEQ BISSC_RX_CRC?, SCRATCH3.b3, 6
+ RSB SCRATCH3.b3, SCRATCH3.b3, 6 ; CRC length, assuming 6 bit crc
+ M_OTF_RECEIVE_AND_DOWNSAMPLE_MC Rb, Rd, Rf, BISSC_RCV_CRC, SCRATCH3.b3, FIFO_BIT_IDX
+
+BISSC_RX_CRC?:
+ SBCO &Ra, PRUx_DMEM, slave_offset, 24
+ ADD slave_offset, slave_offset, 24
+ M_CALC_CRC_MC SCRATCH, FF0, FF1, FF2, FF3, FF4, FF5
+
+ QBEQ BISSC_CH0_CRC_SUCCESS?, SCRATCH.b0, BISSC_RCV_CRC.b0 ; crc: calculated - SCRATCH, received - BISSC_RCV_CRC
+ LBCO &SCRATCH3, PRUx_DMEM, slave_offset, 4
+ ADD SCRATCH3, SCRATCH3, 1
+ SBCO &SCRATCH3, PRUx_DMEM, slave_offset , 4
+BISSC_CH0_CRC_SUCCESS?:
+ ADD slave_offset, slave_offset, 4
+ QBEQ BISSC_CH2_CRC_SUCCESS?, SCRATCH.b1, BISSC_RCV_CRC.b1 ; crc: calculated - SCRATCH, received - BISSC_RCV_CRC
+ LBCO &SCRATCH3, PRUx_DMEM, slave_offset, 4
+ ADD SCRATCH3, SCRATCH3, 1
+ SBCO &SCRATCH3, PRUx_DMEM, slave_offset , 4
+BISSC_CH2_CRC_SUCCESS?:
+ ADD slave_offset, slave_offset, 4
+ QBEQ BISSC_CRC_SUCCESS?, SCRATCH.b2, BISSC_RCV_CRC.b2 ; crc: calculated - SCRATCH, received - BISSC_RCV_CRC
+ LBCO &SCRATCH3, PRUx_DMEM, slave_offset, 4
+ ADD SCRATCH3, SCRATCH3, 1
+ SBCO &SCRATCH3, PRUx_DMEM, slave_offset , 4
+BISSC_CRC_SUCCESS?:
+ ADD slave_offset, slave_offset, 4
+ SBCO &SCRATCH, PRUx_DMEM, slave_offset , 4
+ .endm
diff --git a/source/position_sense/bissc/firmware/bissc_main.asm b/source/position_sense/bissc/firmware/bissc_main.asm
new file mode 100644
index 0000000..548a8ee
--- /dev/null
+++ b/source/position_sense/bissc/firmware/bissc_main.asm
@@ -0,0 +1,664 @@
+
+;
+; Copyright (C) 2023 Texas Instruments Incorporated
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions
+; are met:
+;
+; Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+;
+; Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the
+; distribution.
+;
+; Neither the name of Texas Instruments Incorporated nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+
+;************************************************************************************
+;* File: bissc_main.asm *
+;* *
+;* Brief: Firmware initialization, Storing position data, Control communication*
+;************************************************************************************
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;/
+; Assembler Directives Section
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;/
+ .sect ".text"
+ .retain ; Required for building .out with assembly file
+ .retainrefs ; Required for building .out with assembly file
+ .global BISSC_INIT
+
+
+ .include "bissc_icss_reg_defs.h"
+ .include "bissc_params.h"
+ .include "bissc_interface.h"
+ .include "firmware_version.h"
+ .include "bissc_macros.h"
+
+ ;bissc main starts from here
+BISSC_INIT:
+ JMP BISSC_MAIN
+ .word ICSS_FIRMWARE_RELEASE_1, ICSS_FIRMWARE_RELEASE_2
+BISSC_MAIN:
+ .if $isdefed("PRU0")
+ .asg PRU0_DMEM, PRUx_DMEM
+ .asg ICSS_CFG_PRU0_ENDAT_CH0_CFG1, ICSS_CFG_PRUx_BISSC_CH0_CFG1
+ .asg ICSS_CFG_PRU0_ENDAT_CH1_CFG1, ICSS_CFG_PRUx_BISSC_CH1_CFG1
+ .asg ICSS_CFG_PRU0_ENDAT_CH2_CFG1, ICSS_CFG_PRUx_BISSC_CH2_CFG1
+ .asg ICSS_CFG_PRU0_ENDAT_CH0_CFG0, ICSS_CFG_PRUx_BISSC_CH0_CFG0
+ .asg ICSS_CFG_PRU0_ENDAT_CH1_CFG0, ICSS_CFG_PRUx_BISSC_CH1_CFG0
+ .asg ICSS_CFG_PRU0_ENDAT_CH2_CFG0, ICSS_CFG_PRUx_BISSC_CH2_CFG0
+ .asg ICSS_CFG_PRU0_ENDAT_TXCFG, ICSS_CFG_PRUx_BISSC_TXCFG
+ .asg ICSS_CFG_PRU0_ENDAT_RXCFG, ICSS_CFG_PRUx_BISSC_RXCFG
+ .endif
+
+ .if $isdefed("PRU1")
+ .asg PRU1_DMEM, PRUx_DMEM
+ .asg ICSS_CFG_PRU1_ENDAT_CH0_CFG1, ICSS_CFG_PRUx_BISSC_CH0_CFG1
+ .asg ICSS_CFG_PRU1_ENDAT_CH1_CFG1, ICSS_CFG_PRUx_BISSC_CH1_CFG1
+ .asg ICSS_CFG_PRU1_ENDAT_CH2_CFG1, ICSS_CFG_PRUx_BISSC_CH2_CFG1
+ .asg ICSS_CFG_PRU1_ENDAT_CH0_CFG0, ICSS_CFG_PRUx_BISSC_CH0_CFG0
+ .asg ICSS_CFG_PRU1_ENDAT_CH1_CFG0, ICSS_CFG_PRUx_BISSC_CH1_CFG0
+ .asg ICSS_CFG_PRU1_ENDAT_CH2_CFG0, ICSS_CFG_PRUx_BISSC_CH2_CFG0
+ .asg ICSS_CFG_PRU1_ENDAT_TXCFG, ICSS_CFG_PRUx_BISSC_TXCFG
+ .asg ICSS_CFG_PRU1_ENDAT_RXCFG, ICSS_CFG_PRUx_BISSC_RXCFG
+ .endif
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ M_BISSC_LS_WAIT_FOR_SYNC
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ M_BISSC_LS_WAIT_FOR_SYNC
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ M_BISSC_LS_WAIT_FOR_SYNC
+ .endif
+ ; clear all registers
+ ZERO &R0, 120
+ SBCO &R0, PRUx_DMEM, BISSC_REG_BACKUP, 24
+ LBCO &FIFO_BIT_IDX, PRUx_DMEM, BISSC_FIFO_BIT_IDX_OFFSET, 1 ;bit_idx - 4 th bit(middle one) of 8x over clock or 2nd bit for 4x oversampling
+ LDI VALID_BIT_IDX, BISSC_CH0_VALID_BIT_IDX ;Valid bit index base(24)
+ LBCO &PRIMARY_CORE, PRUx_DMEM, BISSC_MASK_FOR_PRIMARY_CORE, 1 ;load the primary core mask
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ ZERO &SCRATCH1, 1
+ SBCO &SCRATCH1, PRUx_DMEM, BISSC_LS_EXEC_RTU_STATE, 1
+ QBBC BISSC_SKIP_GLOBAL_REINIT0?, PRIMARY_CORE, 0 ;global reinit to be done only by primary core
+ SET R31, BISSC_TX_GLOBAL_REINIT ; Set TX_EN low
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ ZERO &SCRATCH1, 1
+ SBCO &SCRATCH1, PRUx_DMEM, BISSC_LS_EXEC_PRU_STATE, 1
+ QBBC BISSC_SKIP_GLOBAL_REINIT0?, PRIMARY_CORE, 1
+ SET R31, BISSC_TX_GLOBAL_REINIT
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ ZERO &SCRATCH1, 1
+ SBCO &SCRATCH1, PRUx_DMEM, BISSC_LS_EXEC_TXPRU_STATE, 1
+ QBBC BISSC_SKIP_GLOBAL_REINIT0?, PRIMARY_CORE, 2
+ SET R31, BISSC_TX_GLOBAL_REINIT
+ .else
+ SET R31, BISSC_TX_GLOBAL_REINIT
+ .endif
+BISSC_SKIP_GLOBAL_REINIT0?:
+
+ LBCO &CH_MASK, PRUx_DMEM, BISSC_CHANNEL_CONFIG_OFFSET, 1
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ LDI CH_MASK, BISSC_CONFIG_CH0 ;change the channel mask it self, so individual PRU work as channel agnostic, single channel single PRU firmware.
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ LDI CH_MASK, BISSC_CONFIG_CH1
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ LDI CH_MASK, BISSC_CONFIG_CH2
+ .endif
+ ;Measure the Processing delay upon initialization
+ LDI SCRATCH1.b0, 0 ;clear the re measure flag for processing delay before proc measurement
+ SBCO &SCRATCH1, PRUx_DMEM, BISSC_RE_MEASURE_PROC_DELAY, 1
+ M_MEASURE_MAX_PROC_TIME
+
+ ;update the status to notify application
+ LDI STATUS_REG1, 1
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ SBCO &STATUS_REG1, PRUx_DMEM, BISSC_STATUS_CH0_CONFIG_OFFSET, 1
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ SBCO &STATUS_REG1, PRUx_DMEM, BISSC_STATUS_CH1_CONFIG_OFFSET, 1
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ SBCO &STATUS_REG1, PRUx_DMEM, BISSC_STATUS_CH2_CONFIG_OFFSET, 1
+ .else
+ ;ch0 status offset is the base status offset and only ch0 offset is going to be used in single ch or multi ch single pru
+ SBCO &STATUS_REG1, PRUx_DMEM, BISSC_STATUS_CH0_CONFIG_OFFSET, 1
+ .endif
+BISSC_HANDLE_HOST_TRIGGER:
+ ;If Host Trigger=1, request made by R5F to Firmware, now Firmware do processing and when done set trigger to 0 so that R5F application can act further.
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ LBCO &STATUS_REG1, PRUx_DMEM, BISSC_CYCLE_TRIGGER_CH0_STATUS_OFFSET, 1
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ LBCO &STATUS_REG1, PRUx_DMEM, BISSC_CYCLE_TRIGGER_CH1_STATUS_OFFSET, 1
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ LBCO &STATUS_REG1, PRUx_DMEM, BISSC_CYCLE_TRIGGER_CH2_STATUS_OFFSET, 1
+ .else
+ ;ch0 cycle trigger offset is the base cycle trigger offset and only ch0 offset is going to be used in single ch or multi ch single pru
+ LBCO &STATUS_REG1, PRUx_DMEM, BISSC_CYCLE_TRIGGER_CH0_STATUS_OFFSET, 1
+ .endif
+ LBCO &STATUS_REG2, PRUx_DMEM, BISSC_MEAS_PROC_DELAY_OFFSET, 1
+ LBCO &FIFO_BIT_IDX, PRUx_DMEM, BISSC_FIFO_BIT_IDX_OFFSET, 1
+ QBBC BISSC_SKIP_MEASURE_PROC_DELAY?, STATUS_REG2, 0
+
+ ;Measure the Processing delay upon host trigger
+ LDI SCRATCH1.b0, 0
+ SBCO &SCRATCH1, PRUx_DMEM, BISSC_RE_MEASURE_PROC_DELAY, 1
+ M_MEASURE_MAX_PROC_TIME
+
+BISSC_SKIP_MEASURE_PROC_DELAY?:
+ QBBS BISSC_CTRL_CMD_DONE, BISSC_FLAGS_REG, 0
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ LBCO &SCRATCH, PRUx_DMEM, BISSC_CTRL_CMD_CH0_CONFIG_OFFSET, 4
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ LBCO &SCRATCH, PRUx_DMEM, BISSC_CTRL_CMD_CH1_CONFIG_OFFSET, 4
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ LBCO &SCRATCH, PRUx_DMEM, BISSC_CTRL_CMD_CH2_CONFIG_OFFSET, 4
+ .else
+ ;ch0 ctrl command offset is the base ctrl command offset and only ch0 ctrl command offset is going to be used in single ch or multi ch single pru
+ LBCO &SCRATCH, PRUx_DMEM, BISSC_CTRL_CMD_CH0_CONFIG_OFFSET, 4
+ .endif
+ QBEQ BISSC_CTRL_CMD_SKIP, SCRATCH, 0
+ MOV BISSC_CTRL_CMD, SCRATCH
+ SET BISSC_FLAGS_REG, BISSC_FLAGS_REG, 0
+ ZERO &SCRATCH, 4
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ SBCO &SCRATCH, PRUx_DMEM, BISSC_CTRL_CMD_CH0_CONFIG_OFFSET, 4
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ SBCO &SCRATCH, PRUx_DMEM, BISSC_CTRL_CMD_CH1_CONFIG_OFFSET, 4
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ SBCO &SCRATCH, PRUx_DMEM, BISSC_CTRL_CMD_CH2_CONFIG_OFFSET, 4
+ .else
+ SBCO &SCRATCH, PRUx_DMEM, BISSC_CTRL_CMD_CH0_CONFIG_OFFSET, 4
+ .endif
+ ZERO &BISSC_CTRL_FF, 4
+ LDI BISSC_CTRL_CRC, 0
+ LDI BISSC_CTRL_CYCLE_CNTR, 0
+ LDI BISSC_CTRL_CMD_RES, 0
+ LDI BISSC_CTRL_OTF_CRC, 0
+ LDI BISSC_CMD_BIT_PTR, 31 ; CMD bit pointer will points to MSB always, decremented only when we transmit one bit from hex command
+ QBA BISSC_CTRL_CMD_DONE
+BISSC_CTRL_CMD_SKIP:
+ CLR BISSC_FLAGS_REG, BISSC_FLAGS_REG, 0
+BISSC_CTRL_CMD_DONE:
+ ;wait till host trigger is set to 1.
+ QBEQ BISSC_HANDLE_HOST_TRIGGER, STATUS_REG1, 0
+ ;BiSS-C position data/control communication loop start here
+ ;clock mode in freerunning/stop low/stop high and ch0 is selected
+ QBBC BISSC_IS_CH1?, CH_MASK, 0
+ LDI R30.w2, (BISSC_TX_CLK_MODE_FREERUN_STOPHIGH | BISSC_TX_CH0_SEL)
+ LBCO &SCRATCH2.w2, PRUx_DMEM, BISSC_CH0_PROC_DELAY_OFFSET, 2
+ LDI R30.b0, 0
+BISSC_IS_CH1?:
+ QBBC BISSC_IS_CH2?, CH_MASK, 1
+ LDI R30.w2, (BISSC_TX_CLK_MODE_FREERUN_STOPHIGH | BISSC_TX_CH1_SEL)
+ LBCO &SCRATCH2.w2, PRUx_DMEM, BISSC_CH1_PROC_DELAY_OFFSET, 2
+ LDI R30.b0, 0
+BISSC_IS_CH2?:
+ QBBC BISSC_SKIP_CH_SEL1?, CH_MASK, 2
+ LDI R30.w2, (BISSC_TX_CLK_MODE_FREERUN_STOPHIGH | BISSC_TX_CH2_SEL)
+ LBCO &SCRATCH2.w2, PRUx_DMEM, BISSC_CH2_PROC_DELAY_OFFSET, 2
+ LDI R30.b0, 0
+BISSC_SKIP_CH_SEL1?:
+ ; since ENABLE_RUNTIME_CH is kept enabled with all 3 channels selected for multi channel, last channel would have been selected by now
+ .if $isdefed("ENABLE_MULTI_CHANNEL")
+ LOOP BISSC_SEND_RECEIVE_BISSC_MULTI_CHANNEL, 3
+ SUB R30.b2, R30.b2, 1
+BISSC_SEND_RECEIVE_BISSC_MULTI_CHANNEL:
+ .endif
+ ;clock mode in freerunning/stop low/stop high and ch0 is selected
+ LBCO &FIFO_BIT_IDX, PRUx_DMEM, BISSC_FIFO_BIT_IDX_OFFSET, 1
+ LBCO &SCRATCH2.b1, PRUx_DMEM, BISSC_POS_CRC_LEN_CONFIG_OFFSET, 1
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ LBCO &DAISY_CHAIN, PRUx_DMEM, BISSC_NUM_SLAVE_CH0_CONFIG_OFFSET, 4
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ LBCO &DAISY_CHAIN, PRUx_DMEM, BISSC_NUM_SLAVE_CH1_CONFIG_OFFSET, 4
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ LBCO &DAISY_CHAIN, PRUx_DMEM, BISSC_NUM_SLAVE_CH2_CONFIG_OFFSET, 4
+ .else
+ ;ch0 number of slaves and encoder data lengths is the base daisychain offset and only ch0 offset is going to be used in single ch or multi ch single pru
+ LBCO &DAISY_CHAIN, PRUx_DMEM, BISSC_NUM_SLAVE_CH0_CONFIG_OFFSET, 4
+ .endif
+ ;compute RX frame size from input arguments. ACK length will be taken from processing delay.
+ ADD SCRATCH2.w2, SCRATCH2.w2, DAISY_CHAIN.b1 ;data length of slave 0
+ ADD SCRATCH2.w2, SCRATCH2.w2, SCRATCH2.b1 ;crc length
+ ADD SCRATCH2.w2, SCRATCH2.w2, BISSC_EW_LEN ;E + W
+ ADD SCRATCH2.w2, SCRATCH2.w2, BISSC_SB_CDS_LEN ;SB + CDS
+ QBEQ BISSC_SKIP_DAISY_CHAIN, DAISY_CHAIN.b2, 0
+ ADD SCRATCH2.w2, SCRATCH2.w2, DAISY_CHAIN.b2 ;data length of slave 1
+ ADD SCRATCH2.w2, SCRATCH2.w2, SCRATCH2.b1 ;crc length
+ ADD SCRATCH2.w2, SCRATCH2.w2, BISSC_EW_LEN ;E + W
+ QBEQ BISSC_SKIP_DAISY_CHAIN, DAISY_CHAIN.b3, 0
+ ADD SCRATCH2.w2, SCRATCH2.w2, DAISY_CHAIN.b3 ;data length of slave 2
+ ADD SCRATCH2.w2, SCRATCH2.w2, SCRATCH2.b1 ;crc length
+ ADD SCRATCH2.w2, SCRATCH2.w2, BISSC_EW_LEN ;E + W
+
+BISSC_SKIP_DAISY_CHAIN:
+ LDI SCRATCH2.w0, 0
+ ; store Rx and Tx frame size to ICSS_CFG_PRUx_ED_CHx for all configured channels
+ M_BISSC_CLK_CONFIG CH_MASK, SCRATCH2
+ LDI SCRATCH1, 0 ;clear the syn bits for load share.
+ SBCO &SCRATCH1, PRUx_DMEM, BISSC_LS_EXEC_RTU_STATE, 4
+ LDI R30.b0, 0
+ .if $isdefed("ENABLE_MULTI_CHANNEL")
+ SET R31, BISSC_TX_GLOBAL_GO
+ .else
+ SET R31, BISSC_TX_CHANNEL_GO
+ .endif
+ ;enable Rx for channel 0
+
+ QBBC BISSC_IS_CH1_EN?, CH_MASK, 0
+ SET R30, BISSC_CH0_RX_EN
+BISSC_IS_CH1_EN?:
+ QBBC BISSC_IS_CH2_EN?, CH_MASK, 1
+ SET R30, BISSC_CH1_RX_EN
+BISSC_IS_CH2_EN?:
+ QBBC BISSC_ACK_BIT1?, CH_MASK, 2
+ SET R30, BISSC_CH2_RX_EN
+
+ ;ack bit
+BISSC_ACK_BIT1?:
+ ; wait for valid bit
+ AND SCRATCH1.b0, R31.b3, CH_MASK
+ QBNE BISSC_ACK_BIT1?, SCRATCH1.b0, CH_MASK ; wait for valid
+ MOV SCRATCH1, R31
+ ;Set the valid bit for clearing flag so that next bit can come.
+ QBBC BISSC_IS_CH1_VALID_ACK?, CH_MASK, 0
+ SET R31, R31, BISSC_CH0_RX_VALID_BIT_OFFSET
+BISSC_IS_CH1_VALID_ACK?:
+ QBBC BISSC_IS_CH2_VALID_ACK?, CH_MASK, 1
+ SET R31, R31, BISSC_CH1_RX_VALID_BIT_OFFSET
+BISSC_IS_CH2_VALID_ACK?:
+ QBBC BISSC_SKIP_RX_VALID_ACK?, CH_MASK, 2
+ SET R31, R31, BISSC_CH2_RX_VALID_BIT_OFFSET
+BISSC_SKIP_RX_VALID_ACK?:
+ ;must maintain 3 cycles before checking next valid bit
+ NOP
+ NOP
+ QBBC BISSC_IS_CH1_FIFO_ACK?, CH_MASK, 0
+ QBBC BISSC_ACK_FOUND1?, SCRATCH1.b0, FIFO_BIT_IDX
+BISSC_IS_CH1_FIFO_ACK?:
+ QBBC BISSC_IS_CH2_FIFO_ACK?, CH_MASK, 1
+ QBBC BISSC_ACK_FOUND1?, SCRATCH1.b1, FIFO_BIT_IDX
+BISSC_IS_CH2_FIFO_ACK?:
+ QBBC BISSC_ACK_BIT1?, CH_MASK, 2
+ QBBS BISSC_ACK_BIT1?, SCRATCH1.b2, FIFO_BIT_IDX
+BISSC_ACK_FOUND1?:
+ ;start bit
+BISSC_START_BIT1?:
+ ; wait for valid bit
+ AND SCRATCH1.b0, R31.b3, CH_MASK
+ QBNE BISSC_START_BIT1?, SCRATCH1.b0, CH_MASK ; wait for valid
+ MOV SCRATCH1, R31
+ QBBC BISSC_IS_CH1_VALID_SB?, CH_MASK, 0
+ SET R31, R31, BISSC_CH0_RX_VALID_BIT_OFFSET
+BISSC_IS_CH1_VALID_SB?:
+ QBBC BISSC_IS_CH2_VALID_SB?, CH_MASK, 1
+ SET R31, R31, BISSC_CH1_RX_VALID_BIT_OFFSET
+BISSC_IS_CH2_VALID_SB?:
+ QBBC BISSC_SKIP_RX_VALID_SB?, CH_MASK, 2
+ SET R31, R31, BISSC_CH2_RX_VALID_BIT_OFFSET
+BISSC_SKIP_RX_VALID_SB?:
+ NOP
+ NOP
+ ;must maintain 3 cycles before checking next valid bit
+ QBBC BISSC_IS_CH1_FIFO_SB?, CH_MASK, 0
+ QBBS BISSC_START_BIT_FOUND?, SCRATCH1.b0, FIFO_BIT_IDX
+BISSC_IS_CH1_FIFO_SB?:
+ QBBC BISSC_IS_CH2_FIFO_SB?, CH_MASK, 1
+ QBBS BISSC_START_BIT_FOUND?, SCRATCH1.b1, FIFO_BIT_IDX
+BISSC_IS_CH2_FIFO_SB?:
+ QBBC BISSC_START_BIT1?, CH_MASK, 2
+ QBBC BISSC_START_BIT1?, SCRATCH1.b2, FIFO_BIT_IDX
+BISSC_START_BIT_FOUND?:
+ ; cds bit
+BISSC_CDS_BIT1?:
+ ; wait for valid bit
+ AND SCRATCH1.b0, R31.b3, CH_MASK
+ QBNE BISSC_CDS_BIT1?, SCRATCH1.b0, CH_MASK
+ MOV BISSC_CDS_BACKUP, R31
+ QBBC BISSC_IS_CH1_VALID_CDS?, CH_MASK, 0
+ SET R31, R31, BISSC_CH0_RX_VALID_BIT_OFFSET
+BISSC_IS_CH1_VALID_CDS?:
+ QBBC BISSC_IS_CH2_VALID_CDS?, CH_MASK, 1
+ SET R31, R31, BISSC_CH1_RX_VALID_BIT_OFFSET
+BISSC_IS_CH2_VALID_CDS?:
+ QBBC BISSC_CDS_BIT_DETECTED?, CH_MASK, 2
+ SET R31, R31, BISSC_CH2_RX_VALID_BIT_OFFSET
+BISSC_CDS_BIT_DETECTED?:
+
+ .if $isdefed("ENABLE_MULTI_CHANNEL")
+ ADD RAW_DATA_LEN, DAISY_CHAIN.b1, (BISSC_EW_LEN + BISSC_RX_CRCBITS)
+ .else
+ QBBC BISSC_RCV_CH1?, CH_MASK, 0
+ LDI SCRATCH2.b3, BISSC_POS_DATA_WORD_CH0_OFFSET
+ LDI SCRATCH2.b1, BISSC_POS_CRC_ERR_COUNT_CH0_OFFSET
+ LDI SCRATCH2.b2, BISSC_POS_OTF_CRC_CH0_OFFSET
+ JMP BISSC_SKIP_RCV?
+BISSC_RCV_CH1?:
+ QBBC BISSC_RCV_CH2?, CH_MASK, 1
+ ADD FIFO_BIT_IDX, FIFO_BIT_IDX, 8
+ LDI SCRATCH2.b3, BISSC_POS_DATA_WORD_CH1_OFFSET
+ LDI SCRATCH2.b1, BISSC_POS_CRC_ERR_COUNT_CH1_OFFSET
+ LDI SCRATCH2.b2, BISSC_POS_OTF_CRC_CH1_OFFSET
+ JMP BISSC_SKIP_RCV?
+BISSC_RCV_CH2?:
+ QBBC BISSC_SKIP_RCV?, CH_MASK, 2
+ ADD FIFO_BIT_IDX, FIFO_BIT_IDX, 16
+ LDI SCRATCH2.b3, BISSC_POS_DATA_WORD_CH2_OFFSET
+ LDI SCRATCH2.b1, BISSC_POS_CRC_ERR_COUNT_CH2_OFFSET
+ LDI SCRATCH2.b2, BISSC_POS_OTF_CRC_CH2_OFFSET
+BISSC_SKIP_RCV?:
+ .endif
+BISSC_POSITION_DATA?:
+
+ QBEQ BISSC_END_RECEIVE?, DAISY_CHAIN.b0,0
+ ZERO &RAW_DATA1_0, 24
+ QBEQ BISSC_SLAVE3_DATA?, DAISY_CHAIN.b0, 3 ;check if slave 2 is connected
+ QBEQ BISSC_SLAVE2_DATA?, DAISY_CHAIN.b0, 2 ;check if slave 1 is connected
+ .if !$isdefed("ENABLE_MULTI_CHANNEL")
+ ADD RAW_DATA_LEN, DAISY_CHAIN.b1, (BISSC_EW_LEN + BISSC_RX_CRCBITS)
+ .endif
+ LDI SCRATCH2.b0, BISSC_POS_DATA_RES_SLAVE0_OFFSET
+ QBA BISSC_START_RECEIVE?
+BISSC_SLAVE2_DATA?:
+ .if !$isdefed("ENABLE_MULTI_CHANNEL")
+ ADD RAW_DATA_LEN, DAISY_CHAIN.b2, (BISSC_EW_LEN + BISSC_RX_CRCBITS)
+ .endif
+ LDI SCRATCH2.b0, BISSC_POS_DATA_RES_SLAVE1_OFFSET
+ QBA BISSC_START_RECEIVE?
+BISSC_SLAVE3_DATA?:
+ .if !$isdefed("ENABLE_MULTI_CHANNEL")
+ ADD RAW_DATA_LEN, DAISY_CHAIN.b3, (BISSC_EW_LEN + BISSC_RX_CRCBITS)
+ .endif
+ LDI SCRATCH2.b0, BISSC_POS_DATA_RES_SLAVE2_OFFSET
+BISSC_START_RECEIVE?:
+ .if $isdefed("ENABLE_MULTI_CHANNEL")
+ ;receive pos data for multiple channel at once
+ M_OTF_RECEIVE_MC RAW_DATA1_0, RAW_DATA2_0, RAW_DATA1_1, RAW_DATA2_1, RAW_DATA1_2, RAW_DATA2_2, SCRATCH2.b0
+ .else
+ ;receive pos data for single channel
+ M_OTF_RECEIVE RAW_DATA1_0, RAW_DATA2_0, SCRATCH2.b0
+ .endif
+ SUB DAISY_CHAIN.b0, DAISY_CHAIN.b0, 1
+ QBA BISSC_POSITION_DATA?
+BISSC_END_RECEIVE?:
+ ; Control communication starts from here
+ QBBC BISSC_CTRL_COMMUNICATION_SKIP?, BISSC_FLAGS_REG, 0
+ ADD BISSC_CTRL_CYCLE_CNTR, BISSC_CTRL_CYCLE_CNTR, 1
+ QBLE BISSC_CTRL_START_BIT?, BISSC_CTRL_CYCLE_CNTR, 16
+ QBA BISSC_CTRL_CMD_BIT_SEND_SKIP?
+BISSC_CTRL_START_BIT?:
+ LBCO &FIFO_BIT_IDX, PRUx_DMEM, BISSC_FIFO_BIT_IDX_OFFSET, 1
+ QBNE BISSC_CTRL_CMD_NEXT_BIT?, BISSC_CTRL_CYCLE_CNTR, 16
+ ;enable clock override for setting clock to low during timeout
+ ZERO &SCRATCH1, 4
+ SET SCRATCH1, SCRATCH1, 29
+ M_BISSC_CLK_CONFIG CH_MASK, SCRATCH1
+ QBA BISSC_CTRL_CMD_START_BIT_SENT?
+
+BISSC_CTRL_CMD_NEXT_BIT?:
+ QBBC BISSC_SEND_HIGH?, BISSC_CTRL_CMD, BISSC_CMD_BIT_PTR
+BISSC_SEND_LOW?:
+ ;enable clock override for setting clock to low during timeout
+ ZERO &SCRATCH1, 4
+ SET SCRATCH1, SCRATCH1, 29
+ M_BISSC_CLK_CONFIG CH_MASK, SCRATCH1
+BISSC_SEND_HIGH?:
+ QBNE BISSC_CTRL_NO_WAIT_FOR_SLAVE_START_BIT?, BISSC_CMD_BIT_PTR, 13
+ QBBC BISSC_CTRL_SB_CH1?, CH_MASK, 0
+ QBBS BISSC_CTRL_NO_WAIT_FOR_SLAVE_START_BIT?, BISSC_CDS_BACKUP.b0, FIFO_BIT_IDX
+BISSC_CTRL_SB_CH1?:
+ QBBC BISSC_CTRL_SB_CH2?, CH_MASK, 1
+ QBBS BISSC_CTRL_NO_WAIT_FOR_SLAVE_START_BIT?, BISSC_CDS_BACKUP.b1, FIFO_BIT_IDX
+BISSC_CTRL_SB_CH2?:
+ QBBC BISSC_SKIP_CTRL_SB?, CH_MASK, 2
+ QBBS BISSC_CTRL_NO_WAIT_FOR_SLAVE_START_BIT?, BISSC_CDS_BACKUP.b2, FIFO_BIT_IDX
+BISSC_SKIP_CTRL_SB?:
+ ZERO &SCRATCH1, 4
+ SET SCRATCH1, SCRATCH1, 29
+ M_BISSC_CLK_CONFIG CH_MASK, SCRATCH1
+ QBA BISSC_CTRL_CMD_BIT_SEND_SKIP?
+
+BISSC_CTRL_NO_WAIT_FOR_SLAVE_START_BIT?:
+ SUB BISSC_CMD_BIT_PTR, BISSC_CMD_BIT_PTR, 1
+ QBLE BISSC_CTRL_CMD_DATA_RCV_SKIP? , BISSC_CMD_BIT_PTR, 12
+ QBGT BISSC_READ_CTRL_CRC_BITS? , BISSC_CMD_BIT_PTR, 4
+ LBCO &FIFO_BIT_IDX, PRUx_DMEM, BISSC_FIFO_BIT_IDX_OFFSET, 1
+ .if $isdefed("ENABLE_MULTI_CHANNEL")
+ LDI SCRATCH.b0, BISSC_REG_BACKUP
+ LOOP BISSC_READ_CDS_BITS_PER_CH?, 3
+ LBCO &BISSC_CTRL_FF, PRUx_DMEM, SCRATCH.b0, 8
+ .else
+ QBBS BISSC_SKIP_FIFO_CTRL_DATA?, CH_MASK, 0
+ QBBC BISSC_IS_CH2_FIFO_CTRL_DATA?, CH_MASK, 1
+ ADD FIFO_BIT_IDX, FIFO_BIT_IDX, 8
+ JMP BISSC_SKIP_FIFO_CTRL_DATA?
+BISSC_IS_CH2_FIFO_CTRL_DATA?:
+ ADD FIFO_BIT_IDX, FIFO_BIT_IDX, 16
+BISSC_SKIP_FIFO_CTRL_DATA?:
+ .endif
+ LSL BISSC_CTRL_CMD_RES, BISSC_CTRL_CMD_RES, 1
+ QBBS BISSC_CDS_BIT_SET?, BISSC_CDS_BACKUP, FIFO_BIT_IDX
+ XOR EX.b0, BISSC_CTRL_FF.b3, 0
+ QBA BISSC_CTRL_CMD_OTF_CRC?
+BISSC_CDS_BIT_SET?:
+ XOR EX.b0, BISSC_CTRL_FF.b3, 1
+ SET BISSC_CTRL_CMD_RES, BISSC_CTRL_CMD_RES, 0
+BISSC_CTRL_CMD_OTF_CRC?:
+ MOV BISSC_CTRL_FF.b3, BISSC_CTRL_FF.b2
+ MOV BISSC_CTRL_FF.b2, BISSC_CTRL_FF.b1
+ XOR BISSC_CTRL_FF.b1, BISSC_CTRL_FF.b0, EX.b0
+ MOV BISSC_CTRL_FF.b0, EX.b0
+ .if $isdefed("ENABLE_MULTI_CHANNEL")
+ SBCO &BISSC_CTRL_FF, PRUx_DMEM, SCRATCH.b0, 8
+ ADD SCRATCH.b0, SCRATCH.b0, 8
+ ADD FIFO_BIT_IDX, FIFO_BIT_IDX, 8
+BISSC_READ_CDS_BITS_PER_CH?:
+ .endif
+ QBA BISSC_CTRL_CMD_BIT_SEND_SKIP?
+
+BISSC_READ_CTRL_CRC_BITS?:
+ LBCO &FIFO_BIT_IDX, PRUx_DMEM, BISSC_FIFO_BIT_IDX_OFFSET, 1
+ .if $isdefed("ENABLE_MULTI_CHANNEL")
+ LDI SCRATCH.b0, BISSC_REG_BACKUP
+ LOOP BISSC_READ_CTRL_CRC_BITS_PER_CH?, 3
+ LBCO &BISSC_CTRL_FF, PRUx_DMEM, SCRATCH.b0, 8
+ .else
+ QBBS BISSC_SKIP_FIFO_CTRL_CRC?, CH_MASK, 0
+ QBBC BISSC_IS_CH2_FIFO_CTRL_CRC?, CH_MASK, 1
+ ADD FIFO_BIT_IDX, FIFO_BIT_IDX, 8
+ JMP BISSC_SKIP_FIFO_CTRL_CRC?
+BISSC_IS_CH2_FIFO_CTRL_CRC?:
+ QBBC BISSC_SKIP_FIFO_CTRL_CRC?, CH_MASK, 2
+ ADD FIFO_BIT_IDX, FIFO_BIT_IDX, 16
+BISSC_SKIP_FIFO_CTRL_CRC?:
+ .endif
+ LSL BISSC_CTRL_CRC, BISSC_CTRL_CRC, 1
+ QBBC BISSC_CDS_BIT_CLEAR?, BISSC_CDS_BACKUP, FIFO_BIT_IDX
+ SET BISSC_CTRL_CRC, BISSC_CTRL_CRC, 0
+ QBA BISSC_READ_CDS_CRC_OF_NEXT_CH?
+BISSC_CDS_BIT_CLEAR?:
+ CLR BISSC_CTRL_CRC, BISSC_CTRL_CRC, 0
+BISSC_READ_CDS_CRC_OF_NEXT_CH?:
+ .if $isdefed("ENABLE_MULTI_CHANNEL")
+ SBCO &BISSC_CTRL_FF, PRUx_DMEM, SCRATCH.b0, 8
+ ADD SCRATCH.b0, SCRATCH.b0, 8
+ ADD FIFO_BIT_IDX, FIFO_BIT_IDX, 8
+BISSC_READ_CTRL_CRC_BITS_PER_CH?:
+ .endif
+BISSC_CTRL_CMD_BIT_SEND_SKIP?:
+BISSC_CTRL_CMD_DATA_RCV_SKIP?:
+BISSC_CTRL_CMD_START_BIT_SENT?:
+ QBEQ BISSC_CTRL_CMD_COMPLETED?, BISSC_CMD_BIT_PTR, 0
+ QBA BISSC_CTRL_COMMUNICATION_SKIP?
+BISSC_CTRL_CMD_COMPLETED?:
+ .if $isdefed("ENABLE_MULTI_CHANNEL")
+ LDI BASE_OFFSET, BISSC_CH0_CTRL_BASE_OFFSET
+ LDI SCRATCH.b0, BISSC_REG_BACKUP
+ LOOP BISSC_STORE_CTRL_RES?, 3
+ LBCO &BISSC_CTRL_FF, PRUx_DMEM, SCRATCH.b0, 8
+ .else
+ QBBC BISSC_STORE_CH1_CTRL_RES?, CH_MASK, 0
+ LDI BASE_OFFSET, BISSC_CH0_CTRL_BASE_OFFSET
+ JMP BISSC_SKIP_CH2_CTRL_RES?
+BISSC_STORE_CH1_CTRL_RES?:
+ QBBC BISSC_STORE_CH2_CTRL_RES?, CH_MASK, 1
+ LDI BASE_OFFSET, BISSC_CH1_CTRL_BASE_OFFSET
+ JMP BISSC_SKIP_CH2_CTRL_RES?
+BISSC_STORE_CH2_CTRL_RES?:
+ QBBC BISSC_SKIP_CH2_CTRL_RES?, CH_MASK, 2
+ LDI BASE_OFFSET, BISSC_CH2_CTRL_BASE_OFFSET
+BISSC_SKIP_CH2_CTRL_RES?:
+ .endif
+ LDI BISSC_CTRL_OTF_CRC, 0
+ QBBS BISSC_CTRL_CRC_BIT?, BISSC_CTRL_FF.b0, 0
+ SET BISSC_CTRL_OTF_CRC, BISSC_CTRL_OTF_CRC, 0
+BISSC_CTRL_CRC_BIT?:
+ QBBS BISSC_CTRL_CRC_BIT1?, BISSC_CTRL_FF.b1, 0
+ SET BISSC_CTRL_OTF_CRC, BISSC_CTRL_OTF_CRC, 1
+BISSC_CTRL_CRC_BIT1?:
+ QBBS BISSC_CTRL_CRC_BIT2?, BISSC_CTRL_FF.b2, 0
+ SET BISSC_CTRL_OTF_CRC, BISSC_CTRL_OTF_CRC, 2
+BISSC_CTRL_CRC_BIT2?:
+ QBBS BISSC_CTRL_CRC_END?, BISSC_CTRL_FF.b3, 0
+ SET BISSC_CTRL_OTF_CRC, BISSC_CTRL_OTF_CRC, 3
+BISSC_CTRL_CRC_END?:
+ AND BISSC_CTRL_OTF_CRC, BISSC_CTRL_OTF_CRC, 0xF
+ AND BISSC_CTRL_CRC, BISSC_CTRL_CRC, 0xF
+ ADD SCRATCH3.b0, BASE_OFFSET, BISSC_CTRL_CMD_RESULT_OFFSET
+ SBCO &BISSC_CTRL_CMD_RES, PRUx_DMEM, SCRATCH3.b0, 1
+ ADD SCRATCH3.b0, BASE_OFFSET, BISSC_CTRL_CMD_DATA_CRC_OFFSET
+ SBCO &BISSC_CTRL_CRC, PRUx_DMEM, SCRATCH3.b0, 1
+ ADD SCRATCH3.b0, BASE_OFFSET, BISSC_CTRL_CMD_OTF_CRC_OFFSET
+ SBCO &BISSC_CTRL_OTF_CRC, PRUx_DMEM, SCRATCH3.b0, 1
+
+ QBEQ BISSC_CTRL_CRC_SUCCESS?, BISSC_CTRL_OTF_CRC, BISSC_CTRL_CRC
+ ADD SCRATCH3.b0, BASE_OFFSET, BISSC_CTRL_CMD_CRC_ERROR_COUNT_OFFSET
+ LBCO &SCRATCH1, PRUx_DMEM, SCRATCH3.b0, 4
+ ADD SCRATCH1, SCRATCH1, 1
+ SBCO &SCRATCH1, PRUx_DMEM, SCRATCH3.b0, 4
+BISSC_CTRL_CRC_SUCCESS?:
+ LDI BISSC_CTRL_CRC, 0
+ LDI BISSC_CTRL_OTF_CRC, 0
+ .if $isdefed("ENABLE_MULTI_CHANNEL")
+ ZERO &BISSC_CTRL_FF, 4
+ SBCO &BISSC_CTRL_FF, PRUx_DMEM, SCRATCH.b0, 8
+ ADD SCRATCH.b0, SCRATCH.b0, 8
+ ADD BASE_OFFSET, BASE_OFFSET, 8
+BISSC_STORE_CTRL_RES?:
+ .endif
+
+BISSC_HOST_CMD_END:
+
+ CLR BISSC_FLAGS_REG, BISSC_FLAGS_REG, 0 ;clear the flag which indicate the control communication
+
+ LDI STATUS_REG1, 0
+ ;Clear Host Trigger
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ SBCO &STATUS_REG1, PRUx_DMEM, BISSC_CTRL_CMD_CH0_STATUS_OFFSET, 1
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ SBCO &STATUS_REG1, PRUx_DMEM, BISSC_CTRL_CMD_CH1_STATUS_OFFSET, 1
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ SBCO &STATUS_REG1, PRUx_DMEM, BISSC_CTRL_CMD_CH2_STATUS_OFFSET, 1
+ .else
+ ;ch0 ctrl command offset is the base offset and only ch0 offset is going to be used in single ch or multi ch single pru
+ SBCO &STATUS_REG1, PRUx_DMEM, BISSC_CTRL_CMD_CH0_STATUS_OFFSET, 1
+ .endif
+BISSC_CTRL_COMMUNICATION_SKIP?:
+
+
+ LBCO &SCRATCH2, PRUx_DMEM, BISSC_CONFIG_DELAY_40US_OFFSET, 4 ;wait here for 40(biss_timeout)) useconds
+ LSR SCRATCH2, SCRATCH2, 1
+BISSC_DELAY_LOOP1?:
+ SUB SCRATCH2, SCRATCH2, 1
+ QBNE BISSC_DELAY_LOOP1?, SCRATCH2, 0
+ LBCO &FIFO_BIT_IDX, PRUx_DMEM, BISSC_FIFO_BIT_IDX_OFFSET, 1
+BISSC_RESET_BIT?:
+ ; wait for valid bit
+ AND SCRATCH1.b0, R31.b3, CH_MASK
+ QBNE BISSC_RESET_BIT?, CH_MASK, SCRATCH1.b0
+ MOV SCRATCH1, R31
+ QBBC BISSC_IS_CH1_VALID_RB?, CH_MASK, 0
+ SET R31, R31, BISSC_CH0_RX_VALID_BIT_OFFSET
+BISSC_IS_CH1_VALID_RB?:
+ QBBC BISSC_IS_CH2_VALID_RB?, CH_MASK, 1
+ SET R31, R31,BISSC_CH1_RX_VALID_BIT_OFFSET
+BISSC_IS_CH2_VALID_RB?:
+ QBBC BISSC_SKIP_RX_VALID_RB?, CH_MASK, 2
+ SET R31, R31,BISSC_CH2_RX_VALID_BIT_OFFSET
+BISSC_SKIP_RX_VALID_RB?:
+ ;must maintain 3 cycles before checking next valid bit
+ NOP
+ NOP
+ QBBC BISSC_IS_CH1_FIFO_RB?, CH_MASK, 0
+ QBBS BISSC_SKIP_RESET_BIT?, SCRATCH1.b0, FIFO_BIT_IDX
+BISSC_IS_CH1_FIFO_RB?:
+ QBBC BISSC_IS_CH2_FIFO_RB?, CH_MASK, 1
+ QBBS BISSC_SKIP_RESET_BIT?, SCRATCH1.b1, FIFO_BIT_IDX
+BISSC_IS_CH2_FIFO_RB?:
+ QBBC BISSC_RESET_BIT?, CH_MASK, 2
+ QBBC BISSC_RESET_BIT?, SCRATCH1.b2, FIFO_BIT_IDX
+BISSC_SKIP_RESET_BIT?:
+ ;disable clock override by default
+ ZERO &SCRATCH1, 4
+ M_BISSC_CLK_CONFIG CH_MASK, SCRATCH1
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ M_BISSC_LS_WAIT_FOR_SYNC
+ QBBC BISSC_SKIP_GLOBAL_REINIT?, PRIMARY_CORE, 0
+ NOP
+ NOP
+ SET R31, R31, 19 ;ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low
+ ; rx_en = 0 : Disable RX mode
+ LDI R30.b3, 0
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ M_BISSC_LS_WAIT_FOR_SYNC
+ QBBC BISSC_SKIP_GLOBAL_REINIT?, PRIMARY_CORE, 1
+ NOP
+ NOP
+ SET R31, R31, 19 ;ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low
+ ; rx_en = 0 : Disable RX mode
+ LDI R30.b3, 0
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ M_BISSC_LS_WAIT_FOR_SYNC
+ QBBC BISSC_SKIP_GLOBAL_REINIT?, PRIMARY_CORE, 2
+ NOP
+ NOP
+ SET R31, R31, 19 ;ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low
+ ; rx_en = 0 : Disable RX mode
+ LDI R30.b3, 0
+ .else
+ SET R31, R31, 19 ;ENDAT_TX_GLOBAL_REINIT ; Set TX_EN low
+ ; rx_en = 0 : Disable RX mode
+ LDI R30.b3, 0
+ .endif
+BISSC_SKIP_GLOBAL_REINIT?:
+ LDI STATUS_REG1, 0
+ ;Clear Host Trigger
+ .if $isdefed("ENABLE_MULTI_MAKE_RTU")
+ SBCO &STATUS_REG1, PRUx_DMEM, BISSC_CYCLE_TRIGGER_CH0_STATUS_OFFSET, 1
+ .elseif $isdefed("ENABLE_MULTI_MAKE_PRU")
+ SBCO &STATUS_REG1, PRUx_DMEM, BISSC_CYCLE_TRIGGER_CH1_STATUS_OFFSET, 1
+ .elseif $isdefed("ENABLE_MULTI_MAKE_TXPRU")
+ SBCO &STATUS_REG1, PRUx_DMEM, BISSC_CYCLE_TRIGGER_CH2_STATUS_OFFSET, 1
+ .else
+ ;ch0 cycle trigger offset is the base cycle trigger offset and only ch0 offset is going to be used in single ch or multi ch single pru
+ SBCO &STATUS_REG1, PRUx_DMEM, BISSC_CYCLE_TRIGGER_CH0_STATUS_OFFSET, 1
+ .endif
+ ;Handle next Position request by user.
+ JMP BISSC_HANDLE_HOST_TRIGGER
+ ;never reach here
+ HALT
diff --git a/source/position_sense/bissc/firmware/bissc_master_bin.h b/source/position_sense/bissc/firmware/bissc_master_bin.h
new file mode 100644
index 0000000..6c57f62
--- /dev/null
+++ b/source/position_sense/bissc/firmware/bissc_master_bin.h
@@ -0,0 +1,624 @@
+const uint32_t BiSSFirmware_0[] = {
+0x21000300,
+0x00000208,
+0x00000002,
+0x2effbb80,
+0x83c87880,
+0x91191809,
+0x24001808,
+0x91071837,
+0x1f13ffff,
+0x91031828,
+0x24000019,
+0x81e01819,
+0xc9002805,
+0x2400004c,
+0x24001808,
+0x240108c9,
+0x7900000e,
+0xc9012807,
+0x2400014c,
+0x91191809,
+0x01080909,
+0x24001908,
+0x240110c9,
+0x79000007,
+0xc9022855,
+0x2400024c,
+0x91191809,
+0x01100909,
+0x24001a08,
+0x240118c9,
+0x2400009a,
+0x31070038,
+0x69004c03,
+0x240008de,
+0x2400001e,
+0x69014c03,
+0x240009de,
+0x2400001e,
+0x69024c03,
+0x24000ade,
+0x2400001e,
+0x240100db,
+0x2400009b,
+0x80c9249b,
+0x24010499,
+0x9099041b,
+0xd7051bfe,
+0x2400001e,
+0x1f14ffff,
+0x1e08fefe,
+0x24271098,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d823,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xd609f9f9,
+0x0501dbdb,
+0x91301898,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d81d,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xce09f9f9,
+0x0501dbdb,
+0x00d89a9a,
+0x2eff8199,
+0x81c43899,
+0xc808ff00,
+0x1e08ffff,
+0x0501dbdb,
+0x10000000,
+0x10000000,
+0x6f00dbfb,
+0x1f13ffff,
+0x2400007e,
+0x91e8389b,
+0x0501fbfb,
+0x6f00fbff,
+0x10000000,
+0x0b039a9a,
+0x7900000d,
+0x2eff8199,
+0x81c43899,
+0x1f13ffff,
+0x2400007e,
+0x2a000000,
+0x1f13ffff,
+0x2400007e,
+0x2400009a,
+0x91e83898,
+0x0501f8f8,
+0x6f00f8ff,
+0x7f0000ba,
+0x51004c04,
+0x51014c05,
+0x8122189a,
+0x21006d00,
+0x811e189a,
+0x21001100,
+0x8120189a,
+0x21001800,
+0x24000039,
+0x810b1839,
+0x24000157,
+0x81041857,
+0x91081857,
+0x910b1877,
+0x91191809,
+0xc9007766,
+0x24000019,
+0x81e01819,
+0xc9002805,
+0x2400004c,
+0x24001808,
+0x240108c9,
+0x7900000e,
+0xc9012807,
+0x2400014c,
+0x91191809,
+0x01080909,
+0x24001908,
+0x240110c9,
+0x79000007,
+0xc9022855,
+0x2400024c,
+0x91191809,
+0x01100909,
+0x24001a08,
+0x240118c9,
+0x2400009a,
+0x31070038,
+0x69004c03,
+0x240008de,
+0x2400001e,
+0x69014c03,
+0x240009de,
+0x2400001e,
+0x69024c03,
+0x24000ade,
+0x2400001e,
+0x240100db,
+0x2400009b,
+0x80c9249b,
+0x24010499,
+0x9099041b,
+0xd7051bfe,
+0x2400001e,
+0x1f14ffff,
+0x1e08fefe,
+0x24271098,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d823,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xd609f9f9,
+0x0501dbdb,
+0x91301898,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d81d,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xce09f9f9,
+0x0501dbdb,
+0x00d89a9a,
+0x2eff8199,
+0x81c43899,
+0xc808ff00,
+0x1e08ffff,
+0x0501dbdb,
+0x10000000,
+0x10000000,
+0x6f00dbfb,
+0x1f13ffff,
+0x2400007e,
+0x91e8389b,
+0x0501fbfb,
+0x6f00fbff,
+0x10000000,
+0x0b039a9a,
+0x7900000d,
+0x2eff8199,
+0x81c43899,
+0x1f13ffff,
+0x2400007e,
+0x2a000000,
+0x1f13ffff,
+0x2400007e,
+0x2400009a,
+0x91e83898,
+0x0501f8f8,
+0x6f00f8ff,
+0x7f0000ba,
+0x51004c04,
+0x51014c05,
+0x8122189a,
+0x2100d800,
+0x811e189a,
+0x21007c00,
+0x8120189a,
+0x21008300,
+0x24000039,
+0x810b1839,
+0xd100f40f,
+0x91243898,
+0x5100f80c,
+0x10f8f8f5,
+0x1f00f4f4,
+0x2eff8198,
+0x81243898,
+0x2eff818a,
+0x2400002b,
+0x2400002c,
+0x2400004b,
+0x2400006b,
+0x24001f0c,
+0x79000002,
+0x1d00f4f4,
+0x57005788,
+0xc9002804,
+0x240008de,
+0x911e18da,
+0x2400001e,
+0xc9012804,
+0x240009de,
+0x912018da,
+0x2400001e,
+0xc9022804,
+0x24000ade,
+0x912218da,
+0x2400001e,
+0x91191809,
+0x9100183a,
+0x910c3896,
+0x0036dada,
+0x003adada,
+0x0102dada,
+0x0102dada,
+0x51005608,
+0x0056dada,
+0x003adada,
+0x0102dada,
+0x51007604,
+0x0076dada,
+0x003adada,
+0x0102dada,
+0x2400009a,
+0xc9002803,
+0x240108c9,
+0x80c9249a,
+0xc9012803,
+0x240110c9,
+0x80c9249a,
+0xc9022803,
+0x240118c9,
+0x80c9249a,
+0x240000f9,
+0x81c43899,
+0x2400001e,
+0x1f12ffff,
+0xc9002802,
+0x1f18fefe,
+0xc9012802,
+0x1f19fefe,
+0xc9022802,
+0x1f1afefe,
+0x10287f19,
+0x6e2819ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xc8091905,
+0xc9012802,
+0xc8093903,
+0xcf0228f1,
+0xd60959f0,
+0x10287f19,
+0x6e2819ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xd0091905,
+0xc9012802,
+0xd0093903,
+0xcf0228f1,
+0xce0959f0,
+0x10287f19,
+0x6e2819ff,
+0x10fffff3,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0xc9002805,
+0x2400007a,
+0x2400183a,
+0x2400245a,
+0x21015400,
+0xc9012806,
+0x01080909,
+0x2400087a,
+0x24001c3a,
+0x2400255a,
+0x21015400,
+0xc9022805,
+0x01100909,
+0x2400107a,
+0x2400203a,
+0x2400265a,
+0x5100167e,
+0x2eff8b8d,
+0x51031608,
+0x51021604,
+0x010836c8,
+0x2400341a,
+0x79000006,
+0x010856c8,
+0x24005c1a,
+0x79000003,
+0x010876c8,
+0x2400841a,
+0x2eff8281,
+0x0506c87b,
+0x71207b2f,
+0x311f0010,
+0x0901eded,
+0x10287f18,
+0x6e2818ff,
+0xd009ff03,
+0x10222207,
+0x21016c00,
+0x16002207,
+0x1301eded,
+0x1018187f,
+0x10020222,
+0x10616102,
+0x10414161,
+0x10212141,
+0x14070121,
+0x10070701,
+0x0526c87b,
+0x307b0010,
+0x0901eeee,
+0x10287f18,
+0x6e2818ff,
+0xd009ff03,
+0x10222207,
+0x21017d00,
+0x16002207,
+0x1301eeee,
+0x1018187f,
+0x10020222,
+0x10616102,
+0x10414161,
+0x10212141,
+0x14070121,
+0x10070701,
+0x24000007,
+0x2400067b,
+0x307b000a,
+0x0901eeee,
+0x09010707,
+0x10287f18,
+0x6e2818ff,
+0xd009ff02,
+0x79000003,
+0x1301eeee,
+0x13010707,
+0x1018187f,
+0x2101ba00,
+0x307b0010,
+0x0901eded,
+0x10287f18,
+0x6e2818ff,
+0xd009ff03,
+0x10222207,
+0x21019a00,
+0x16002207,
+0x1301eded,
+0x1018187f,
+0x10020222,
+0x10616102,
+0x10414161,
+0x10212141,
+0x14070121,
+0x10070701,
+0x24000007,
+0x0d207b7b,
+0x19067b7b,
+0x307b000a,
+0x0901eded,
+0x09010707,
+0x10287f18,
+0x6e2818ff,
+0xd009ff02,
+0x79000003,
+0x1301eded,
+0x13010707,
+0x1018187f,
+0x51067b0c,
+0x0d067b7b,
+0x307b000a,
+0x0901eeee,
+0x09010707,
+0x10287f18,
+0x6e2818ff,
+0xd009ff02,
+0x79000003,
+0x1301eeee,
+0x13010707,
+0x1018187f,
+0x007a1a6c,
+0x806c788d,
+0x003a1a6c,
+0x2400007b,
+0xd1000102,
+0x1f007b7b,
+0xd1002102,
+0x1f017b7b,
+0xd1004102,
+0x1f027b7b,
+0xd1006102,
+0x1f037b7b,
+0xd1000202,
+0x1f047b7b,
+0xd1002202,
+0x1f057b7b,
+0x50077b04,
+0x906c3898,
+0x0101f8f8,
+0x806c3898,
+0x005a1a6c,
+0x806c187b,
+0x05011616,
+0x7f000083,
+0xc900f476,
+0x01012c2c,
+0x59102c02,
+0x7900004e,
+0x91191809,
+0x69102c0d,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x79000040,
+0xc80cf50c,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x690d0c13,
+0xc9002802,
+0xd0091311,
+0xc9012802,
+0xd009330f,
+0xc9022802,
+0xd009530d,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x79000021,
+0x05010c0c,
+0x590c0c1f,
+0x61040c12,
+0x91191809,
+0xd1002805,
+0xc9012803,
+0x01080909,
+0x21020c00,
+0x01100909,
+0x09014b4b,
+0xd009f303,
+0x15006a07,
+0x79000003,
+0x15016a07,
+0x1f004b4b,
+0x104a4a6a,
+0x102a2a4a,
+0x14070a2a,
+0x1007070a,
+0x7900000d,
+0x91191809,
+0xd1002806,
+0xc9012803,
+0x01080909,
+0x21021e00,
+0xc9022802,
+0x01100909,
+0x09012b2b,
+0xc809f303,
+0x1f002b2b,
+0x79000002,
+0x1d002b2b,
+0x51000c02,
+0x79000024,
+0xc9002803,
+0x2400ac29,
+0x21022d00,
+0xc9012803,
+0x2400b429,
+0x21022d00,
+0xc9022802,
+0x2400bc29,
+0x2400006b,
+0xd1000a02,
+0x1f006b6b,
+0xd1002a02,
+0x1f016b6b,
+0xd1004a02,
+0x1f026b6b,
+0xd1006a02,
+0x1f036b6b,
+0x110f6b6b,
+0x110f2b2b,
+0x0104291b,
+0x801b184b,
+0x0105291b,
+0x801b182b,
+0x0106291b,
+0x801b186b,
+0x502b6b05,
+0x0100291b,
+0x901b3899,
+0x0101f9f9,
+0x801b3899,
+0x2400002b,
+0x2400006b,
+0x1d00f4f4,
+0x24000057,
+0x811a1857,
+0x91e4389a,
+0x0b01fafa,
+0x0501fafa,
+0x6f00faff,
+0x91191809,
+0x10287f19,
+0x6e1928ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xd0091905,
+0xc9012802,
+0xd0093903,
+0xcf0228f1,
+0xce0959f0,
+0x2eff8199,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x1f13ffff,
+0x2400007e,
+0x24000057,
+0x81081857,
+0x21007100,
+0x2a000000};
+
diff --git a/source/position_sense/bissc/firmware/bissc_master_hexpru.cmd b/source/position_sense/bissc/firmware/bissc_master_hexpru.cmd
new file mode 100644
index 0000000..1eb8d70
--- /dev/null
+++ b/source/position_sense/bissc/firmware/bissc_master_hexpru.cmd
@@ -0,0 +1,3 @@
+-b
+-map=bissc_master_hex.map
+SECTIONS {.text}
diff --git a/source/position_sense/bissc/firmware/bissc_master_multi_PRU_bin.h b/source/position_sense/bissc/firmware/bissc_master_multi_PRU_bin.h
new file mode 100644
index 0000000..a1b9373
--- /dev/null
+++ b/source/position_sense/bissc/firmware/bissc_master_multi_PRU_bin.h
@@ -0,0 +1,727 @@
+const uint32_t BiSSFirmwareMultiMakePRU_0[] = {
+0x21000300,
+0x00000208,
+0x00000002,
+0x24000217,
+0x81c51817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0x2effbb80,
+0x83c87880,
+0x91191809,
+0x24001808,
+0x91071837,
+0x2eff8019,
+0x81c51819,
+0xc9013702,
+0x1f13ffff,
+0x91031828,
+0x24000228,
+0x24000019,
+0x81e01819,
+0xc9002805,
+0x2400004c,
+0x24001808,
+0x240108c9,
+0x7900000e,
+0xc9012807,
+0x2400014c,
+0x91191809,
+0x01080909,
+0x24001908,
+0x240110c9,
+0x79000007,
+0xc902287b,
+0x2400024c,
+0x91191809,
+0x01100909,
+0x24001a08,
+0x240118c9,
+0x2400009a,
+0x31070054,
+0x24000217,
+0x81c51817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0x69004c03,
+0x240008de,
+0x2400001e,
+0x69014c03,
+0x240009de,
+0x2400001e,
+0x69024c03,
+0x24000ade,
+0x2400001e,
+0x240100db,
+0x2400009b,
+0x80c9249b,
+0xc9013708,
+0x24010499,
+0x9099041b,
+0xd7061bfd,
+0x2400001b,
+0x81e0181b,
+0x2400001e,
+0x1f14ffff,
+0x1e08fefe,
+0x24271098,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d832,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xd609f9f9,
+0x0501dbdb,
+0x91301898,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d837,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xce09f9f9,
+0x0501dbdb,
+0x00d89a9a,
+0x2eff8199,
+0x81c43899,
+0xc808ff00,
+0x1e08ffff,
+0x0501dbdb,
+0x10000000,
+0x10000000,
+0x6f00dbfb,
+0x91c5181b,
+0x6f001bff,
+0x24000217,
+0x81c51817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9013703,
+0x1f13ffff,
+0x2400007e,
+0x91e0187a,
+0x57017ab0,
+0x91e8389b,
+0x0501fbfb,
+0x6f00fbff,
+0x10000000,
+0x0b039a9a,
+0x79000017,
+0x2eff8199,
+0x81c43899,
+0x24000217,
+0x81c51817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9013703,
+0x1f13ffff,
+0x2400007e,
+0x2a000000,
+0x91e83898,
+0x0501f8f8,
+0x6f00f8ff,
+0x2400017a,
+0x81e0187a,
+0x7f0000d4,
+0x51004c04,
+0x51014c05,
+0x8122189a,
+0x2100a100,
+0x811e189a,
+0x21001f00,
+0x8120189a,
+0x21002600,
+0x24000039,
+0x810b1839,
+0x24000157,
+0x81051857,
+0x91091857,
+0x910b1877,
+0x91191809,
+0xc900778c,
+0x24000019,
+0x81e01819,
+0xc9002805,
+0x2400004c,
+0x24001808,
+0x240108c9,
+0x7900000e,
+0xc9012807,
+0x2400014c,
+0x91191809,
+0x01080909,
+0x24001908,
+0x240110c9,
+0x79000007,
+0xc902287b,
+0x2400024c,
+0x91191809,
+0x01100909,
+0x24001a08,
+0x240118c9,
+0x2400009a,
+0x31070054,
+0x24000217,
+0x81c51817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0x69004c03,
+0x240008de,
+0x2400001e,
+0x69014c03,
+0x240009de,
+0x2400001e,
+0x69024c03,
+0x24000ade,
+0x2400001e,
+0x240100db,
+0x2400009b,
+0x80c9249b,
+0xc9013708,
+0x24010499,
+0x9099041b,
+0xd7061bfd,
+0x2400001b,
+0x81e0181b,
+0x2400001e,
+0x1f14ffff,
+0x1e08fefe,
+0x24271098,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d832,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xd609f9f9,
+0x0501dbdb,
+0x91301898,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d837,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xce09f9f9,
+0x0501dbdb,
+0x00d89a9a,
+0x2eff8199,
+0x81c43899,
+0xc808ff00,
+0x1e08ffff,
+0x0501dbdb,
+0x10000000,
+0x10000000,
+0x6f00dbfb,
+0x91c5181b,
+0x6f001bff,
+0x24000217,
+0x81c51817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9013703,
+0x1f13ffff,
+0x2400007e,
+0x91e0187a,
+0x57017ab0,
+0x91e8389b,
+0x0501fbfb,
+0x6f00fbff,
+0x10000000,
+0x0b039a9a,
+0x79000017,
+0x2eff8199,
+0x81c43899,
+0x24000217,
+0x81c51817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9013703,
+0x1f13ffff,
+0x2400007e,
+0x2a000000,
+0x91e83898,
+0x0501f8f8,
+0x6f00f8ff,
+0x2400017a,
+0x81e0187a,
+0x7f0000d4,
+0x51004c04,
+0x51014c05,
+0x8122189a,
+0x21013200,
+0x811e189a,
+0x2100b000,
+0x8120189a,
+0x2100b700,
+0x24000039,
+0x810b1839,
+0xd100f40f,
+0x91283898,
+0x5100f80c,
+0x10f8f8f5,
+0x1f00f4f4,
+0x2eff8198,
+0x81283898,
+0x2eff818a,
+0x2400002b,
+0x2400002c,
+0x2400004b,
+0x2400006b,
+0x24001f0c,
+0x79000002,
+0x1d00f4f4,
+0x57005762,
+0xc9002804,
+0x240008de,
+0x911e18da,
+0x2400001e,
+0xc9012804,
+0x240009de,
+0x912018da,
+0x2400001e,
+0xc9022804,
+0x24000ade,
+0x912218da,
+0x2400001e,
+0x91191809,
+0x9100183a,
+0x91103896,
+0x0036dada,
+0x003adada,
+0x0102dada,
+0x0102dada,
+0x51005608,
+0x0056dada,
+0x003adada,
+0x0102dada,
+0x51007604,
+0x0076dada,
+0x003adada,
+0x0102dada,
+0x2400009a,
+0xc9002803,
+0x240108c9,
+0x80c9249a,
+0xc9012803,
+0x240110c9,
+0x80c9249a,
+0xc9022803,
+0x240118c9,
+0x80c9249a,
+0x240000f9,
+0x81c43899,
+0x2400001e,
+0x1f12ffff,
+0xc9002802,
+0x1f18fefe,
+0xc9012802,
+0x1f19fefe,
+0xc9022802,
+0x1f1afefe,
+0x10287f19,
+0x6e2819ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xc8091905,
+0xc9012802,
+0xc8093903,
+0xcf0228f1,
+0xd60959f0,
+0x10287f19,
+0x6e2819ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xd0091905,
+0xc9012802,
+0xd0093903,
+0xcf0228f1,
+0xce0959f0,
+0x10287f19,
+0x6e2819ff,
+0x10fffff3,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0xc9002805,
+0x2400007a,
+0x2400183a,
+0x2400245a,
+0x2101ae00,
+0xc9012806,
+0x01080909,
+0x2400087a,
+0x24001c3a,
+0x2400255a,
+0x2101ae00,
+0xc9022805,
+0x01100909,
+0x2400107a,
+0x2400203a,
+0x2400265a,
+0x5100167e,
+0x2eff8b8d,
+0x51031608,
+0x51021604,
+0x010836c8,
+0x2400341a,
+0x79000006,
+0x010856c8,
+0x24005c1a,
+0x79000003,
+0x010876c8,
+0x2400841a,
+0x2eff8281,
+0x0506c87b,
+0x71207b2f,
+0x311f0010,
+0x0901eded,
+0x10287f18,
+0x6e2818ff,
+0xd009ff03,
+0x10222207,
+0x2101c600,
+0x16002207,
+0x1301eded,
+0x1018187f,
+0x10020222,
+0x10616102,
+0x10414161,
+0x10212141,
+0x14070121,
+0x10070701,
+0x0526c87b,
+0x307b0010,
+0x0901eeee,
+0x10287f18,
+0x6e2818ff,
+0xd009ff03,
+0x10222207,
+0x2101d700,
+0x16002207,
+0x1301eeee,
+0x1018187f,
+0x10020222,
+0x10616102,
+0x10414161,
+0x10212141,
+0x14070121,
+0x10070701,
+0x24000007,
+0x2400067b,
+0x307b000a,
+0x0901eeee,
+0x09010707,
+0x10287f18,
+0x6e2818ff,
+0xd009ff02,
+0x79000003,
+0x1301eeee,
+0x13010707,
+0x1018187f,
+0x21021400,
+0x307b0010,
+0x0901eded,
+0x10287f18,
+0x6e2818ff,
+0xd009ff03,
+0x10222207,
+0x2101f400,
+0x16002207,
+0x1301eded,
+0x1018187f,
+0x10020222,
+0x10616102,
+0x10414161,
+0x10212141,
+0x14070121,
+0x10070701,
+0x24000007,
+0x0d207b7b,
+0x19067b7b,
+0x307b000a,
+0x0901eded,
+0x09010707,
+0x10287f18,
+0x6e2818ff,
+0xd009ff02,
+0x79000003,
+0x1301eded,
+0x13010707,
+0x1018187f,
+0x51067b0c,
+0x0d067b7b,
+0x307b000a,
+0x0901eeee,
+0x09010707,
+0x10287f18,
+0x6e2818ff,
+0xd009ff02,
+0x79000003,
+0x1301eeee,
+0x13010707,
+0x1018187f,
+0x007a1a6c,
+0x806c788d,
+0x003a1a6c,
+0x2400007b,
+0xd1000102,
+0x1f007b7b,
+0xd1002102,
+0x1f017b7b,
+0xd1004102,
+0x1f027b7b,
+0xd1006102,
+0x1f037b7b,
+0xd1000202,
+0x1f047b7b,
+0xd1002202,
+0x1f057b7b,
+0x50077b04,
+0x906c3898,
+0x0101f8f8,
+0x806c3898,
+0x005a1a6c,
+0x806c187b,
+0x05011616,
+0x7f000083,
+0xc900f476,
+0x01012c2c,
+0x59102c02,
+0x7900004e,
+0x91191809,
+0x69102c0d,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x79000040,
+0xc80cf50c,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x690d0c13,
+0xc9002802,
+0xd0091311,
+0xc9012802,
+0xd009330f,
+0xc9022802,
+0xd009530d,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x79000021,
+0x05010c0c,
+0x590c0c1f,
+0x61040c12,
+0x91191809,
+0xd1002805,
+0xc9012803,
+0x01080909,
+0x21026600,
+0x01100909,
+0x09014b4b,
+0xd009f303,
+0x15006a07,
+0x79000003,
+0x15016a07,
+0x1f004b4b,
+0x104a4a6a,
+0x102a2a4a,
+0x14070a2a,
+0x1007070a,
+0x7900000d,
+0x91191809,
+0xd1002806,
+0xc9012803,
+0x01080909,
+0x21027800,
+0xc9022802,
+0x01100909,
+0x09012b2b,
+0xc809f303,
+0x1f002b2b,
+0x79000002,
+0x1d002b2b,
+0x51000c02,
+0x79000024,
+0xc9002803,
+0x2400ac29,
+0x21028700,
+0xc9012803,
+0x2400b429,
+0x21028700,
+0xc9022802,
+0x2400bc29,
+0x2400006b,
+0xd1000a02,
+0x1f006b6b,
+0xd1002a02,
+0x1f016b6b,
+0xd1004a02,
+0x1f026b6b,
+0xd1006a02,
+0x1f036b6b,
+0x110f6b6b,
+0x110f2b2b,
+0x0104291b,
+0x801b184b,
+0x0105291b,
+0x801b182b,
+0x0106291b,
+0x801b186b,
+0x502b6b05,
+0x0100291b,
+0x901b3899,
+0x0101f9f9,
+0x801b3899,
+0x2400002b,
+0x2400006b,
+0x1d00f4f4,
+0x24000057,
+0x811b1857,
+0x91e4389a,
+0x0b01fafa,
+0x0501fafa,
+0x6f00faff,
+0x91191809,
+0x10287f19,
+0x6e1928ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xd0091905,
+0xc9012802,
+0xd0093903,
+0xcf0228f1,
+0xce0959f0,
+0x2eff8199,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x24000217,
+0x81c51817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9013705,
+0x10000000,
+0x10000000,
+0x1f13ffff,
+0x2400007e,
+0x24000057,
+0x81091857,
+0x2100a500,
+0x2a000000};
+
diff --git a/source/position_sense/bissc/firmware/bissc_master_multi_RTU_bin.h b/source/position_sense/bissc/firmware/bissc_master_multi_RTU_bin.h
new file mode 100644
index 0000000..59f0dbc
--- /dev/null
+++ b/source/position_sense/bissc/firmware/bissc_master_multi_RTU_bin.h
@@ -0,0 +1,727 @@
+const uint32_t BiSSFirmwareMultiMakeRTU_0[] = {
+0x21000300,
+0x00000208,
+0x00000002,
+0x24000117,
+0x81c41817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0x2effbb80,
+0x83c87880,
+0x91191809,
+0x24001808,
+0x91071837,
+0x2eff8019,
+0x81c41819,
+0xc9003702,
+0x1f13ffff,
+0x91031828,
+0x24000128,
+0x24000019,
+0x81e01819,
+0xc9002805,
+0x2400004c,
+0x24001808,
+0x240108c9,
+0x7900000e,
+0xc9012807,
+0x2400014c,
+0x91191809,
+0x01080909,
+0x24001908,
+0x240110c9,
+0x79000007,
+0xc902287b,
+0x2400024c,
+0x91191809,
+0x01100909,
+0x24001a08,
+0x240118c9,
+0x2400009a,
+0x31070054,
+0x24000117,
+0x81c41817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0x69004c03,
+0x240008de,
+0x2400001e,
+0x69014c03,
+0x240009de,
+0x2400001e,
+0x69024c03,
+0x24000ade,
+0x2400001e,
+0x240100db,
+0x2400009b,
+0x80c9249b,
+0xc9003708,
+0x24010499,
+0x9099041b,
+0xd7051bfd,
+0x2400001b,
+0x81e0181b,
+0x2400001e,
+0x1f14ffff,
+0x1e08fefe,
+0x24271098,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d832,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xd609f9f9,
+0x0501dbdb,
+0x91301898,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d837,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xce09f9f9,
+0x0501dbdb,
+0x00d89a9a,
+0x2eff8199,
+0x81c43899,
+0xc808ff00,
+0x1e08ffff,
+0x0501dbdb,
+0x10000000,
+0x10000000,
+0x6f00dbfb,
+0x91c4181b,
+0x6f001bff,
+0x24000117,
+0x81c41817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9003703,
+0x1f13ffff,
+0x2400007e,
+0x91e0187a,
+0x57017ab0,
+0x91e8389b,
+0x0501fbfb,
+0x6f00fbff,
+0x10000000,
+0x0b039a9a,
+0x79000017,
+0x2eff8199,
+0x81c43899,
+0x24000117,
+0x81c41817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9003703,
+0x1f13ffff,
+0x2400007e,
+0x2a000000,
+0x91e83898,
+0x0501f8f8,
+0x6f00f8ff,
+0x2400017a,
+0x81e0187a,
+0x7f0000d4,
+0x51004c04,
+0x51014c05,
+0x8122189a,
+0x2100a100,
+0x811e189a,
+0x21001f00,
+0x8120189a,
+0x21002600,
+0x24000039,
+0x810b1839,
+0x24000157,
+0x81041857,
+0x91081857,
+0x910b1877,
+0x91191809,
+0xc900778c,
+0x24000019,
+0x81e01819,
+0xc9002805,
+0x2400004c,
+0x24001808,
+0x240108c9,
+0x7900000e,
+0xc9012807,
+0x2400014c,
+0x91191809,
+0x01080909,
+0x24001908,
+0x240110c9,
+0x79000007,
+0xc902287b,
+0x2400024c,
+0x91191809,
+0x01100909,
+0x24001a08,
+0x240118c9,
+0x2400009a,
+0x31070054,
+0x24000117,
+0x81c41817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0x69004c03,
+0x240008de,
+0x2400001e,
+0x69014c03,
+0x240009de,
+0x2400001e,
+0x69024c03,
+0x24000ade,
+0x2400001e,
+0x240100db,
+0x2400009b,
+0x80c9249b,
+0xc9003708,
+0x24010499,
+0x9099041b,
+0xd7051bfd,
+0x2400001b,
+0x81e0181b,
+0x2400001e,
+0x1f14ffff,
+0x1e08fefe,
+0x24271098,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d832,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xd609f9f9,
+0x0501dbdb,
+0x91301898,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d837,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xce09f9f9,
+0x0501dbdb,
+0x00d89a9a,
+0x2eff8199,
+0x81c43899,
+0xc808ff00,
+0x1e08ffff,
+0x0501dbdb,
+0x10000000,
+0x10000000,
+0x6f00dbfb,
+0x91c4181b,
+0x6f001bff,
+0x24000117,
+0x81c41817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9003703,
+0x1f13ffff,
+0x2400007e,
+0x91e0187a,
+0x57017ab0,
+0x91e8389b,
+0x0501fbfb,
+0x6f00fbff,
+0x10000000,
+0x0b039a9a,
+0x79000017,
+0x2eff8199,
+0x81c43899,
+0x24000117,
+0x81c41817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9003703,
+0x1f13ffff,
+0x2400007e,
+0x2a000000,
+0x91e83898,
+0x0501f8f8,
+0x6f00f8ff,
+0x2400017a,
+0x81e0187a,
+0x7f0000d4,
+0x51004c04,
+0x51014c05,
+0x8122189a,
+0x21013200,
+0x811e189a,
+0x2100b000,
+0x8120189a,
+0x2100b700,
+0x24000039,
+0x810b1839,
+0xd100f40f,
+0x91243898,
+0x5100f80c,
+0x10f8f8f5,
+0x1f00f4f4,
+0x2eff8198,
+0x81243898,
+0x2eff818a,
+0x2400002b,
+0x2400002c,
+0x2400004b,
+0x2400006b,
+0x24001f0c,
+0x79000002,
+0x1d00f4f4,
+0x57005762,
+0xc9002804,
+0x240008de,
+0x911e18da,
+0x2400001e,
+0xc9012804,
+0x240009de,
+0x912018da,
+0x2400001e,
+0xc9022804,
+0x24000ade,
+0x912218da,
+0x2400001e,
+0x91191809,
+0x9100183a,
+0x910c3896,
+0x0036dada,
+0x003adada,
+0x0102dada,
+0x0102dada,
+0x51005608,
+0x0056dada,
+0x003adada,
+0x0102dada,
+0x51007604,
+0x0076dada,
+0x003adada,
+0x0102dada,
+0x2400009a,
+0xc9002803,
+0x240108c9,
+0x80c9249a,
+0xc9012803,
+0x240110c9,
+0x80c9249a,
+0xc9022803,
+0x240118c9,
+0x80c9249a,
+0x240000f9,
+0x81c43899,
+0x2400001e,
+0x1f12ffff,
+0xc9002802,
+0x1f18fefe,
+0xc9012802,
+0x1f19fefe,
+0xc9022802,
+0x1f1afefe,
+0x10287f19,
+0x6e2819ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xc8091905,
+0xc9012802,
+0xc8093903,
+0xcf0228f1,
+0xd60959f0,
+0x10287f19,
+0x6e2819ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xd0091905,
+0xc9012802,
+0xd0093903,
+0xcf0228f1,
+0xce0959f0,
+0x10287f19,
+0x6e2819ff,
+0x10fffff3,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0xc9002805,
+0x2400007a,
+0x2400183a,
+0x2400245a,
+0x2101ae00,
+0xc9012806,
+0x01080909,
+0x2400087a,
+0x24001c3a,
+0x2400255a,
+0x2101ae00,
+0xc9022805,
+0x01100909,
+0x2400107a,
+0x2400203a,
+0x2400265a,
+0x5100167e,
+0x2eff8b8d,
+0x51031608,
+0x51021604,
+0x010836c8,
+0x2400341a,
+0x79000006,
+0x010856c8,
+0x24005c1a,
+0x79000003,
+0x010876c8,
+0x2400841a,
+0x2eff8281,
+0x0506c87b,
+0x71207b2f,
+0x311f0010,
+0x0901eded,
+0x10287f18,
+0x6e2818ff,
+0xd009ff03,
+0x10222207,
+0x2101c600,
+0x16002207,
+0x1301eded,
+0x1018187f,
+0x10020222,
+0x10616102,
+0x10414161,
+0x10212141,
+0x14070121,
+0x10070701,
+0x0526c87b,
+0x307b0010,
+0x0901eeee,
+0x10287f18,
+0x6e2818ff,
+0xd009ff03,
+0x10222207,
+0x2101d700,
+0x16002207,
+0x1301eeee,
+0x1018187f,
+0x10020222,
+0x10616102,
+0x10414161,
+0x10212141,
+0x14070121,
+0x10070701,
+0x24000007,
+0x2400067b,
+0x307b000a,
+0x0901eeee,
+0x09010707,
+0x10287f18,
+0x6e2818ff,
+0xd009ff02,
+0x79000003,
+0x1301eeee,
+0x13010707,
+0x1018187f,
+0x21021400,
+0x307b0010,
+0x0901eded,
+0x10287f18,
+0x6e2818ff,
+0xd009ff03,
+0x10222207,
+0x2101f400,
+0x16002207,
+0x1301eded,
+0x1018187f,
+0x10020222,
+0x10616102,
+0x10414161,
+0x10212141,
+0x14070121,
+0x10070701,
+0x24000007,
+0x0d207b7b,
+0x19067b7b,
+0x307b000a,
+0x0901eded,
+0x09010707,
+0x10287f18,
+0x6e2818ff,
+0xd009ff02,
+0x79000003,
+0x1301eded,
+0x13010707,
+0x1018187f,
+0x51067b0c,
+0x0d067b7b,
+0x307b000a,
+0x0901eeee,
+0x09010707,
+0x10287f18,
+0x6e2818ff,
+0xd009ff02,
+0x79000003,
+0x1301eeee,
+0x13010707,
+0x1018187f,
+0x007a1a6c,
+0x806c788d,
+0x003a1a6c,
+0x2400007b,
+0xd1000102,
+0x1f007b7b,
+0xd1002102,
+0x1f017b7b,
+0xd1004102,
+0x1f027b7b,
+0xd1006102,
+0x1f037b7b,
+0xd1000202,
+0x1f047b7b,
+0xd1002202,
+0x1f057b7b,
+0x50077b04,
+0x906c3898,
+0x0101f8f8,
+0x806c3898,
+0x005a1a6c,
+0x806c187b,
+0x05011616,
+0x7f000083,
+0xc900f476,
+0x01012c2c,
+0x59102c02,
+0x7900004e,
+0x91191809,
+0x69102c0d,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x79000040,
+0xc80cf50c,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x690d0c13,
+0xc9002802,
+0xd0091311,
+0xc9012802,
+0xd009330f,
+0xc9022802,
+0xd009530d,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x79000021,
+0x05010c0c,
+0x590c0c1f,
+0x61040c12,
+0x91191809,
+0xd1002805,
+0xc9012803,
+0x01080909,
+0x21026600,
+0x01100909,
+0x09014b4b,
+0xd009f303,
+0x15006a07,
+0x79000003,
+0x15016a07,
+0x1f004b4b,
+0x104a4a6a,
+0x102a2a4a,
+0x14070a2a,
+0x1007070a,
+0x7900000d,
+0x91191809,
+0xd1002806,
+0xc9012803,
+0x01080909,
+0x21027800,
+0xc9022802,
+0x01100909,
+0x09012b2b,
+0xc809f303,
+0x1f002b2b,
+0x79000002,
+0x1d002b2b,
+0x51000c02,
+0x79000024,
+0xc9002803,
+0x2400ac29,
+0x21028700,
+0xc9012803,
+0x2400b429,
+0x21028700,
+0xc9022802,
+0x2400bc29,
+0x2400006b,
+0xd1000a02,
+0x1f006b6b,
+0xd1002a02,
+0x1f016b6b,
+0xd1004a02,
+0x1f026b6b,
+0xd1006a02,
+0x1f036b6b,
+0x110f6b6b,
+0x110f2b2b,
+0x0104291b,
+0x801b184b,
+0x0105291b,
+0x801b182b,
+0x0106291b,
+0x801b186b,
+0x502b6b05,
+0x0100291b,
+0x901b3899,
+0x0101f9f9,
+0x801b3899,
+0x2400002b,
+0x2400006b,
+0x1d00f4f4,
+0x24000057,
+0x811a1857,
+0x91e4389a,
+0x0b01fafa,
+0x0501fafa,
+0x6f00faff,
+0x91191809,
+0x10287f19,
+0x6e1928ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xd0091905,
+0xc9012802,
+0xd0093903,
+0xcf0228f1,
+0xce0959f0,
+0x2eff8199,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x24000117,
+0x81c41817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9003705,
+0x10000000,
+0x10000000,
+0x1f13ffff,
+0x2400007e,
+0x24000057,
+0x81081857,
+0x2100a500,
+0x2a000000};
+
diff --git a/source/position_sense/bissc/firmware/bissc_master_multi_TXPRU_bin.h b/source/position_sense/bissc/firmware/bissc_master_multi_TXPRU_bin.h
new file mode 100644
index 0000000..1ed450f
--- /dev/null
+++ b/source/position_sense/bissc/firmware/bissc_master_multi_TXPRU_bin.h
@@ -0,0 +1,727 @@
+const uint32_t BiSSFirmwareMultiMakeTXPRU_0[] = {
+0x21000300,
+0x00000208,
+0x00000002,
+0x24000417,
+0x81c61817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0x2effbb80,
+0x83c87880,
+0x91191809,
+0x24001808,
+0x91071837,
+0x2eff8019,
+0x81c61819,
+0xc9023702,
+0x1f13ffff,
+0x91031828,
+0x24000428,
+0x24000019,
+0x81e01819,
+0xc9002805,
+0x2400004c,
+0x24001808,
+0x240108c9,
+0x7900000e,
+0xc9012807,
+0x2400014c,
+0x91191809,
+0x01080909,
+0x24001908,
+0x240110c9,
+0x79000007,
+0xc902287b,
+0x2400024c,
+0x91191809,
+0x01100909,
+0x24001a08,
+0x240118c9,
+0x2400009a,
+0x31070054,
+0x24000417,
+0x81c61817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0x69004c03,
+0x240008de,
+0x2400001e,
+0x69014c03,
+0x240009de,
+0x2400001e,
+0x69024c03,
+0x24000ade,
+0x2400001e,
+0x240100db,
+0x2400009b,
+0x80c9249b,
+0xc9023708,
+0x24010499,
+0x9099041b,
+0xd7071bfd,
+0x2400001b,
+0x81e0181b,
+0x2400001e,
+0x1f14ffff,
+0x1e08fefe,
+0x24271098,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d832,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xd609f9f9,
+0x0501dbdb,
+0x91301898,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d837,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xce09f9f9,
+0x0501dbdb,
+0x00d89a9a,
+0x2eff8199,
+0x81c43899,
+0xc808ff00,
+0x1e08ffff,
+0x0501dbdb,
+0x10000000,
+0x10000000,
+0x6f00dbfb,
+0x91c6181b,
+0x6f001bff,
+0x24000417,
+0x81c61817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9023703,
+0x1f13ffff,
+0x2400007e,
+0x91e0187a,
+0x57017ab0,
+0x91e8389b,
+0x0501fbfb,
+0x6f00fbff,
+0x10000000,
+0x0b039a9a,
+0x79000017,
+0x2eff8199,
+0x81c43899,
+0x24000417,
+0x81c61817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9023703,
+0x1f13ffff,
+0x2400007e,
+0x2a000000,
+0x91e83898,
+0x0501f8f8,
+0x6f00f8ff,
+0x2400017a,
+0x81e0187a,
+0x7f0000d4,
+0x51004c04,
+0x51014c05,
+0x8122189a,
+0x2100a100,
+0x811e189a,
+0x21001f00,
+0x8120189a,
+0x21002600,
+0x24000039,
+0x810b1839,
+0x24000157,
+0x81061857,
+0x910a1857,
+0x910b1877,
+0x91191809,
+0xc900778c,
+0x24000019,
+0x81e01819,
+0xc9002805,
+0x2400004c,
+0x24001808,
+0x240108c9,
+0x7900000e,
+0xc9012807,
+0x2400014c,
+0x91191809,
+0x01080909,
+0x24001908,
+0x240110c9,
+0x79000007,
+0xc902287b,
+0x2400024c,
+0x91191809,
+0x01100909,
+0x24001a08,
+0x240118c9,
+0x2400009a,
+0x31070054,
+0x24000417,
+0x81c61817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0x69004c03,
+0x240008de,
+0x2400001e,
+0x69014c03,
+0x240009de,
+0x2400001e,
+0x69024c03,
+0x24000ade,
+0x2400001e,
+0x240100db,
+0x2400009b,
+0x80c9249b,
+0xc9023708,
+0x24010499,
+0x9099041b,
+0xd7071bfd,
+0x2400001b,
+0x81e0181b,
+0x2400001e,
+0x1f14ffff,
+0x1e08fefe,
+0x24271098,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d832,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xd609f9f9,
+0x0501dbdb,
+0x91301898,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d837,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xce09f9f9,
+0x0501dbdb,
+0x00d89a9a,
+0x2eff8199,
+0x81c43899,
+0xc808ff00,
+0x1e08ffff,
+0x0501dbdb,
+0x10000000,
+0x10000000,
+0x6f00dbfb,
+0x91c6181b,
+0x6f001bff,
+0x24000417,
+0x81c61817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9023703,
+0x1f13ffff,
+0x2400007e,
+0x91e0187a,
+0x57017ab0,
+0x91e8389b,
+0x0501fbfb,
+0x6f00fbff,
+0x10000000,
+0x0b039a9a,
+0x79000017,
+0x2eff8199,
+0x81c43899,
+0x24000417,
+0x81c61817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9023703,
+0x1f13ffff,
+0x2400007e,
+0x2a000000,
+0x91e83898,
+0x0501f8f8,
+0x6f00f8ff,
+0x2400017a,
+0x81e0187a,
+0x7f0000d4,
+0x51004c04,
+0x51014c05,
+0x8122189a,
+0x21013200,
+0x811e189a,
+0x2100b000,
+0x8120189a,
+0x2100b700,
+0x24000039,
+0x810b1839,
+0xd100f40f,
+0x912c3898,
+0x5100f80c,
+0x10f8f8f5,
+0x1f00f4f4,
+0x2eff8198,
+0x812c3898,
+0x2eff818a,
+0x2400002b,
+0x2400002c,
+0x2400004b,
+0x2400006b,
+0x24001f0c,
+0x79000002,
+0x1d00f4f4,
+0x57005762,
+0xc9002804,
+0x240008de,
+0x911e18da,
+0x2400001e,
+0xc9012804,
+0x240009de,
+0x912018da,
+0x2400001e,
+0xc9022804,
+0x24000ade,
+0x912218da,
+0x2400001e,
+0x91191809,
+0x9100183a,
+0x91143896,
+0x0036dada,
+0x003adada,
+0x0102dada,
+0x0102dada,
+0x51005608,
+0x0056dada,
+0x003adada,
+0x0102dada,
+0x51007604,
+0x0076dada,
+0x003adada,
+0x0102dada,
+0x2400009a,
+0xc9002803,
+0x240108c9,
+0x80c9249a,
+0xc9012803,
+0x240110c9,
+0x80c9249a,
+0xc9022803,
+0x240118c9,
+0x80c9249a,
+0x240000f9,
+0x81c43899,
+0x2400001e,
+0x1f12ffff,
+0xc9002802,
+0x1f18fefe,
+0xc9012802,
+0x1f19fefe,
+0xc9022802,
+0x1f1afefe,
+0x10287f19,
+0x6e2819ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xc8091905,
+0xc9012802,
+0xc8093903,
+0xcf0228f1,
+0xd60959f0,
+0x10287f19,
+0x6e2819ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xd0091905,
+0xc9012802,
+0xd0093903,
+0xcf0228f1,
+0xce0959f0,
+0x10287f19,
+0x6e2819ff,
+0x10fffff3,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0xc9002805,
+0x2400007a,
+0x2400183a,
+0x2400245a,
+0x2101ae00,
+0xc9012806,
+0x01080909,
+0x2400087a,
+0x24001c3a,
+0x2400255a,
+0x2101ae00,
+0xc9022805,
+0x01100909,
+0x2400107a,
+0x2400203a,
+0x2400265a,
+0x5100167e,
+0x2eff8b8d,
+0x51031608,
+0x51021604,
+0x010836c8,
+0x2400341a,
+0x79000006,
+0x010856c8,
+0x24005c1a,
+0x79000003,
+0x010876c8,
+0x2400841a,
+0x2eff8281,
+0x0506c87b,
+0x71207b2f,
+0x311f0010,
+0x0901eded,
+0x10287f18,
+0x6e2818ff,
+0xd009ff03,
+0x10222207,
+0x2101c600,
+0x16002207,
+0x1301eded,
+0x1018187f,
+0x10020222,
+0x10616102,
+0x10414161,
+0x10212141,
+0x14070121,
+0x10070701,
+0x0526c87b,
+0x307b0010,
+0x0901eeee,
+0x10287f18,
+0x6e2818ff,
+0xd009ff03,
+0x10222207,
+0x2101d700,
+0x16002207,
+0x1301eeee,
+0x1018187f,
+0x10020222,
+0x10616102,
+0x10414161,
+0x10212141,
+0x14070121,
+0x10070701,
+0x24000007,
+0x2400067b,
+0x307b000a,
+0x0901eeee,
+0x09010707,
+0x10287f18,
+0x6e2818ff,
+0xd009ff02,
+0x79000003,
+0x1301eeee,
+0x13010707,
+0x1018187f,
+0x21021400,
+0x307b0010,
+0x0901eded,
+0x10287f18,
+0x6e2818ff,
+0xd009ff03,
+0x10222207,
+0x2101f400,
+0x16002207,
+0x1301eded,
+0x1018187f,
+0x10020222,
+0x10616102,
+0x10414161,
+0x10212141,
+0x14070121,
+0x10070701,
+0x24000007,
+0x0d207b7b,
+0x19067b7b,
+0x307b000a,
+0x0901eded,
+0x09010707,
+0x10287f18,
+0x6e2818ff,
+0xd009ff02,
+0x79000003,
+0x1301eded,
+0x13010707,
+0x1018187f,
+0x51067b0c,
+0x0d067b7b,
+0x307b000a,
+0x0901eeee,
+0x09010707,
+0x10287f18,
+0x6e2818ff,
+0xd009ff02,
+0x79000003,
+0x1301eeee,
+0x13010707,
+0x1018187f,
+0x007a1a6c,
+0x806c788d,
+0x003a1a6c,
+0x2400007b,
+0xd1000102,
+0x1f007b7b,
+0xd1002102,
+0x1f017b7b,
+0xd1004102,
+0x1f027b7b,
+0xd1006102,
+0x1f037b7b,
+0xd1000202,
+0x1f047b7b,
+0xd1002202,
+0x1f057b7b,
+0x50077b04,
+0x906c3898,
+0x0101f8f8,
+0x806c3898,
+0x005a1a6c,
+0x806c187b,
+0x05011616,
+0x7f000083,
+0xc900f476,
+0x01012c2c,
+0x59102c02,
+0x7900004e,
+0x91191809,
+0x69102c0d,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x79000040,
+0xc80cf50c,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x690d0c13,
+0xc9002802,
+0xd0091311,
+0xc9012802,
+0xd009330f,
+0xc9022802,
+0xd009530d,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x79000021,
+0x05010c0c,
+0x590c0c1f,
+0x61040c12,
+0x91191809,
+0xd1002805,
+0xc9012803,
+0x01080909,
+0x21026600,
+0x01100909,
+0x09014b4b,
+0xd009f303,
+0x15006a07,
+0x79000003,
+0x15016a07,
+0x1f004b4b,
+0x104a4a6a,
+0x102a2a4a,
+0x14070a2a,
+0x1007070a,
+0x7900000d,
+0x91191809,
+0xd1002806,
+0xc9012803,
+0x01080909,
+0x21027800,
+0xc9022802,
+0x01100909,
+0x09012b2b,
+0xc809f303,
+0x1f002b2b,
+0x79000002,
+0x1d002b2b,
+0x51000c02,
+0x79000024,
+0xc9002803,
+0x2400ac29,
+0x21028700,
+0xc9012803,
+0x2400b429,
+0x21028700,
+0xc9022802,
+0x2400bc29,
+0x2400006b,
+0xd1000a02,
+0x1f006b6b,
+0xd1002a02,
+0x1f016b6b,
+0xd1004a02,
+0x1f026b6b,
+0xd1006a02,
+0x1f036b6b,
+0x110f6b6b,
+0x110f2b2b,
+0x0104291b,
+0x801b184b,
+0x0105291b,
+0x801b182b,
+0x0106291b,
+0x801b186b,
+0x502b6b05,
+0x0100291b,
+0x901b3899,
+0x0101f9f9,
+0x801b3899,
+0x2400002b,
+0x2400006b,
+0x1d00f4f4,
+0x24000057,
+0x811c1857,
+0x91e4389a,
+0x0b01fafa,
+0x0501fafa,
+0x6f00faff,
+0x91191809,
+0x10287f19,
+0x6e1928ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xd0091905,
+0xc9012802,
+0xd0093903,
+0xcf0228f1,
+0xce0959f0,
+0x2eff8199,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x24000417,
+0x81c61817,
+0x91031819,
+0x91c41817,
+0x10171739,
+0x91c51817,
+0x12173939,
+0x91c61817,
+0x12173939,
+0x6e1939fa,
+0xc9023705,
+0x10000000,
+0x10000000,
+0x1f13ffff,
+0x2400007e,
+0x24000057,
+0x810a1857,
+0x2100a500,
+0x2a000000};
+
diff --git a/source/position_sense/bissc/firmware/bissc_master_multi_bin.h b/source/position_sense/bissc/firmware/bissc_master_multi_bin.h
new file mode 100644
index 0000000..afe2cb1
--- /dev/null
+++ b/source/position_sense/bissc/firmware/bissc_master_multi_bin.h
@@ -0,0 +1,691 @@
+const uint32_t BiSSFirmwareMulti_0[] = {
+0x21000300,
+0x00000208,
+0x00000002,
+0x2effbb80,
+0x83c87880,
+0x91191809,
+0x24001808,
+0x91071837,
+0x1f13ffff,
+0x91031828,
+0x24000019,
+0x81e01819,
+0xc9002805,
+0x2400004c,
+0x24001808,
+0x240108c9,
+0x7900000e,
+0xc9012807,
+0x2400014c,
+0x91191809,
+0x01080909,
+0x24001908,
+0x240110c9,
+0x79000007,
+0xc9022855,
+0x2400024c,
+0x91191809,
+0x01100909,
+0x24001a08,
+0x240118c9,
+0x2400009a,
+0x31070038,
+0x69004c03,
+0x240008de,
+0x2400001e,
+0x69014c03,
+0x240009de,
+0x2400001e,
+0x69024c03,
+0x24000ade,
+0x2400001e,
+0x240100db,
+0x2400009b,
+0x80c9249b,
+0x24010499,
+0x9099041b,
+0xd7051bfe,
+0x2400001e,
+0x1f14ffff,
+0x1e08fefe,
+0x24271098,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d823,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xd609f9f9,
+0x0501dbdb,
+0x91301898,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d81d,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xce09f9f9,
+0x0501dbdb,
+0x00d89a9a,
+0x2eff8199,
+0x81c43899,
+0xc808ff00,
+0x1e08ffff,
+0x0501dbdb,
+0x10000000,
+0x10000000,
+0x6f00dbfb,
+0x1f13ffff,
+0x2400007e,
+0x91e8389b,
+0x0501fbfb,
+0x6f00fbff,
+0x10000000,
+0x0b039a9a,
+0x7900000d,
+0x2eff8199,
+0x81c43899,
+0x1f13ffff,
+0x2400007e,
+0x2a000000,
+0x1f13ffff,
+0x2400007e,
+0x2400009a,
+0x91e83898,
+0x0501f8f8,
+0x6f00f8ff,
+0x7f0000ba,
+0x51004c04,
+0x51014c05,
+0x8122189a,
+0x21006d00,
+0x811e189a,
+0x21001100,
+0x8120189a,
+0x21001800,
+0x24000039,
+0x810b1839,
+0x24000157,
+0x81041857,
+0x91081857,
+0x910b1877,
+0x91191809,
+0xc9007766,
+0x24000019,
+0x81e01819,
+0xc9002805,
+0x2400004c,
+0x24001808,
+0x240108c9,
+0x7900000e,
+0xc9012807,
+0x2400014c,
+0x91191809,
+0x01080909,
+0x24001908,
+0x240110c9,
+0x79000007,
+0xc9022855,
+0x2400024c,
+0x91191809,
+0x01100909,
+0x24001a08,
+0x240118c9,
+0x2400009a,
+0x31070038,
+0x69004c03,
+0x240008de,
+0x2400001e,
+0x69014c03,
+0x240009de,
+0x2400001e,
+0x69024c03,
+0x24000ade,
+0x2400001e,
+0x240100db,
+0x2400009b,
+0x80c9249b,
+0x24010499,
+0x9099041b,
+0xd7051bfe,
+0x2400001e,
+0x1f14ffff,
+0x1e08fefe,
+0x24271098,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d823,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xd609f9f9,
+0x0501dbdb,
+0x91301898,
+0x240000d8,
+0xc808ff00,
+0x0101d8d8,
+0x4898d81d,
+0x10fffff9,
+0x1e08ffff,
+0x10000000,
+0x10000000,
+0xce09f9f9,
+0x0501dbdb,
+0x00d89a9a,
+0x2eff8199,
+0x81c43899,
+0xc808ff00,
+0x1e08ffff,
+0x0501dbdb,
+0x10000000,
+0x10000000,
+0x6f00dbfb,
+0x1f13ffff,
+0x2400007e,
+0x91e8389b,
+0x0501fbfb,
+0x6f00fbff,
+0x10000000,
+0x0b039a9a,
+0x7900000d,
+0x2eff8199,
+0x81c43899,
+0x1f13ffff,
+0x2400007e,
+0x2a000000,
+0x1f13ffff,
+0x2400007e,
+0x2400009a,
+0x91e83898,
+0x0501f8f8,
+0x6f00f8ff,
+0x7f0000ba,
+0x51004c04,
+0x51014c05,
+0x8122189a,
+0x2100d800,
+0x811e189a,
+0x21007c00,
+0x8120189a,
+0x21008300,
+0x24000039,
+0x810b1839,
+0xd100f40f,
+0x91243898,
+0x5100f80c,
+0x10f8f8f5,
+0x1f00f4f4,
+0x2eff8198,
+0x81243898,
+0x2eff818a,
+0x2400002b,
+0x2400002c,
+0x2400004b,
+0x2400006b,
+0x24001f0c,
+0x79000002,
+0x1d00f4f4,
+0x57005788,
+0xc9002804,
+0x240008de,
+0x911e18da,
+0x2400001e,
+0xc9012804,
+0x240009de,
+0x912018da,
+0x2400001e,
+0xc9022804,
+0x24000ade,
+0x912218da,
+0x2400001e,
+0x31020002,
+0x05015e5e,
+0x91191809,
+0x9100183a,
+0x910c3896,
+0x0036dada,
+0x003adada,
+0x0102dada,
+0x0102dada,
+0x51005608,
+0x0056dada,
+0x003adada,
+0x0102dada,
+0x51007604,
+0x0076dada,
+0x003adada,
+0x0102dada,
+0x2400009a,
+0xc9002803,
+0x240108c9,
+0x80c9249a,
+0xc9012803,
+0x240110c9,
+0x80c9249a,
+0xc9022803,
+0x240118c9,
+0x80c9249a,
+0x240000f9,
+0x81c43899,
+0x2400001e,
+0x1f14ffff,
+0xc9002802,
+0x1f18fefe,
+0xc9012802,
+0x1f19fefe,
+0xc9022802,
+0x1f1afefe,
+0x10287f19,
+0x6e2819ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xc8091905,
+0xc9012802,
+0xc8093903,
+0xcf0228f1,
+0xd60959f0,
+0x10287f19,
+0x6e2819ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xd0091905,
+0xc9012802,
+0xd0093903,
+0xcf0228f1,
+0xce0959f0,
+0x10287f19,
+0x6e2819ff,
+0x10fffff3,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x010836c8,
+0x510016cd,
+0x2eff8b8d,
+0x51031606,
+0x51021603,
+0x2400341a,
+0x79000004,
+0x24005c1a,
+0x79000002,
+0x2400841a,
+0x2eff8b81,
+0x0506c87b,
+0x71207b50,
+0x311f001c,
+0x0901eded,
+0x0901efef,
+0x0901f1f1,
+0x10287f18,
+0x6e2818ff,
+0xd0091f03,
+0x10060607,
+0x21015e00,
+0x16000607,
+0x1301eded,
+0xd0093f03,
+0x10262627,
+0x21016300,
+0x16002627,
+0x1301efef,
+0xd0095f03,
+0x10464647,
+0x21016800,
+0x16004647,
+0x1301f1f1,
+0x1018187f,
+0x10e5e5e6,
+0x10e4e4e5,
+0x10e3e3e4,
+0x10e2e2e3,
+0x14e7e1e2,
+0x10e7e7e1,
+0x0526c87b,
+0x307b001c,
+0x0901eeee,
+0x0901f0f0,
+0x0901f2f2,
+0x10287f18,
+0x6e2818ff,
+0xd0091f03,
+0x10060607,
+0x21017b00,
+0x16000607,
+0x1301eeee,
+0xd0093f03,
+0x10262627,
+0x21018000,
+0x16002627,
+0x1301f0f0,
+0xd0095f03,
+0x10464647,
+0x21018500,
+0x16004647,
+0x1301f2f2,
+0x1018187f,
+0x10e5e5e6,
+0x10e4e4e5,
+0x10e3e3e4,
+0x10e2e2e3,
+0x14e7e1e2,
+0x10e7e7e1,
+0x240000e7,
+0x31050014,
+0x0901eeee,
+0x0901f0f0,
+0x0901f2f2,
+0x0901e7e7,
+0x10287f18,
+0x6e2818ff,
+0xd0091f02,
+0x21019800,
+0x1301eeee,
+0x13010707,
+0xd0093f02,
+0x21019c00,
+0x1301f0f0,
+0x13012727,
+0xd0095f02,
+0x2101a000,
+0x1301f2f2,
+0x13014747,
+0x1018187f,
+0x2101eb00,
+0x307b001c,
+0x0901eded,
+0x0901efef,
+0x0901f1f1,
+0x10287f18,
+0x6e2818ff,
+0xd0091f03,
+0x10060607,
+0x2101ad00,
+0x16000607,
+0x1301eded,
+0xd0093f03,
+0x10262627,
+0x2101b200,
+0x16002627,
+0x1301efef,
+0xd0095f03,
+0x10464647,
+0x2101b700,
+0x16004647,
+0x1301f1f1,
+0x1018187f,
+0x10e5e5e6,
+0x10e4e4e5,
+0x10e3e3e4,
+0x10e2e2e3,
+0x14e7e1e2,
+0x10e7e7e1,
+0x0d207b7b,
+0x19067b7b,
+0x240000e7,
+0x307b0014,
+0x0901eded,
+0x0901efef,
+0x0901f1f1,
+0x0901e7e7,
+0x10287f18,
+0x6e2818ff,
+0xd0091f02,
+0x2101cc00,
+0x1301eded,
+0x13010707,
+0xd0093f02,
+0x2101d000,
+0x1301efef,
+0x13012727,
+0xd0095f02,
+0x2101d400,
+0x1301f1f1,
+0x13014747,
+0x1018187f,
+0x51067b16,
+0x0d067b7b,
+0x307b0014,
+0x0901eeee,
+0x0901f0f0,
+0x0901f2f2,
+0x0901e7e7,
+0x10287f18,
+0x6e2818ff,
+0xd0091f02,
+0x2101e200,
+0x1301eeee,
+0x13010707,
+0xd0093f02,
+0x2101e600,
+0x1301f0f0,
+0x13012727,
+0xd0095f02,
+0x2101ea00,
+0x1301f2f2,
+0x13014747,
+0x1018187f,
+0x821a788d,
+0x01181a1a,
+0x2eff8198,
+0x31020014,
+0x0908e1e1,
+0x0908e2e2,
+0x0908e3e3,
+0x0908e4e4,
+0x0908e5e5,
+0x0908e6e6,
+0x0908f8f8,
+0xd1006102,
+0x1f001818,
+0xd1006202,
+0x1f011818,
+0xd1006302,
+0x1f021818,
+0xd1006402,
+0x1f031818,
+0xd1006502,
+0x1f041818,
+0xd1006602,
+0x1f051818,
+0x50071804,
+0x901a389b,
+0x0101fbfb,
+0x801a389b,
+0x01041a1a,
+0x50273804,
+0x901a389b,
+0x0101fbfb,
+0x801a389b,
+0x01041a1a,
+0x50475804,
+0x901a389b,
+0x0101fbfb,
+0x801a389b,
+0x01041a1a,
+0x801a3898,
+0x05011616,
+0x7f000034,
+0xc900f477,
+0x01012c2c,
+0x59102c02,
+0x7900004f,
+0x91191809,
+0x69102c0d,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x79000041,
+0xc80cf50c,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x690d0c13,
+0xc9002802,
+0xd0091311,
+0xc9012802,
+0xd009330f,
+0xc9022802,
+0xd009530d,
+0x2eff8199,
+0x1f1df9f9,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x79000022,
+0x05010c0c,
+0x590c0c20,
+0x61040c13,
+0x91191809,
+0x2400c818,
+0x3102000f,
+0x9018788a,
+0x09014b4b,
+0xd009f303,
+0x15006a07,
+0x79000003,
+0x15016a07,
+0x1f004b4b,
+0x104a4a6a,
+0x102a2a4a,
+0x14070a2a,
+0x1007070a,
+0x8018788a,
+0x01081818,
+0x01080909,
+0x7900000d,
+0x91191809,
+0x2400c818,
+0x3102000a,
+0x9018788a,
+0x09012b2b,
+0xc809f303,
+0x1f002b2b,
+0x79000002,
+0x1d002b2b,
+0x8018788a,
+0x01081818,
+0x01080909,
+0x51000c02,
+0x79000024,
+0x2400ac29,
+0x2400c818,
+0x3102001e,
+0x9018788a,
+0x2400006b,
+0xd1000a02,
+0x1f006b6b,
+0xd1002a02,
+0x1f016b6b,
+0xd1004a02,
+0x1f026b6b,
+0xd1006a02,
+0x1f036b6b,
+0x110f6b6b,
+0x110f2b2b,
+0x0104291b,
+0x801b184b,
+0x0105291b,
+0x801b182b,
+0x0106291b,
+0x801b186b,
+0x502b6b05,
+0x0100291b,
+0x901b3899,
+0x0101f9f9,
+0x801b3899,
+0x2400002b,
+0x2400006b,
+0x2eff818a,
+0x8018788a,
+0x01081818,
+0x01082929,
+0x1d00f4f4,
+0x24000057,
+0x811a1857,
+0x91e4389a,
+0x0b01fafa,
+0x0501fafa,
+0x6f00faff,
+0x91191809,
+0x10287f19,
+0x6e1928ff,
+0x10fffff9,
+0xc9002802,
+0x1f18ffff,
+0xc9012802,
+0x1f19ffff,
+0xc9022802,
+0x1f1affff,
+0x10000000,
+0x10000000,
+0xc9002802,
+0xd0091905,
+0xc9012802,
+0xd0093903,
+0xcf0228f1,
+0xce0959f0,
+0x2eff8199,
+0xc9002803,
+0x240108c9,
+0x80c92499,
+0xc9012803,
+0x240110c9,
+0x80c92499,
+0xc9022803,
+0x240118c9,
+0x80c92499,
+0x1f13ffff,
+0x2400007e,
+0x24000057,
+0x81081857,
+0x21007100,
+0x2a000000};
+
diff --git a/source/position_sense/bissc/firmware/bissc_params.h b/source/position_sense/bissc/firmware/bissc_params.h
new file mode 100644
index 0000000..146d43e
--- /dev/null
+++ b/source/position_sense/bissc/firmware/bissc_params.h
@@ -0,0 +1,132 @@
+
+;
+; Copyright (C) 2023 Texas Instruments Incorporated
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions
+; are met:
+;
+; Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+;
+; Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the
+; distribution.
+;
+; Neither the name of Texas Instruments Incorporated nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;************************************************************************************
+;* File: bissc_params.h *
+;* *
+;* Brief: Defining Register usage and setting BissC specific parameters *
+;************************************************************************************
+
+
+ ; register usage
+ ; R1-R6 - flipflops for otf crc.
+ ; R7 - holds received crc for position data and used as ex for otf calculation.
+ ; R8.b0 - valid bit,rx enable, rx valid, R8.b1 - holds channel mask, R8.w2 - stores raw data length (pos_data_length + ew_length + pos_crc_length).
+ ; R9.b0 - holds fifo bit index(middle bit) of oversampled data, R9.b1 - holds base offset for channel in use, R9.w2 - holds CFG0 offset for channel in use.
+ ; R10 - flipflops for control communication otf crc.
+ ; R11.b1 - holds 4-bit control communication crc, R11.b2 - holds cds data, R11.b3 - holds ctrl otf crc.
+ ; R12.b0 - control command bit pointer, R12.b1 - control cycle counter.
+ ; R12.b2 - holds the channel number for channel in use, R12.b3 - holds slave offset for encoder connected in daisy chain.
+ ; R13-R14 - holds raw data for channel 0, R15-R16 - holds raw data for channel 1, R17-R18 - holds raw data for channel 2.
+ ; R19 - holds cds backup for one biss-c cycle.
+ ; R20 - Used as flag register.
+ ; R21 - holds hex equivalent control command.
+ ; R22 - holds daisy chain configurations.
+ ; R23.b0 - used for execution status for each PRU in load share. R23.b1 - holds primary core mask.
+ ; R23.w2 -it is used as status register.
+ ; R24-R27 - scratch.
+ ; R29 - holds call and return (branch) address.
+
+ ; unused Register: R11.b0, R28
+
+ .asg R1, FF0
+ .asg R2, FF1
+ .asg R3, FF2
+ .asg R4, FF3
+ .asg R5, FF4
+ .asg R6, FF5
+ .asg R7, EX
+ .asg R7, BISSC_RCV_CRC
+ .asg R8.b0, VALID_BIT_IDX
+ .asg R8.b0, BISSC_RX_EN
+ .asg R8.b0, BISSC_RX_VALID
+ .asg R8.b1, CH_MASK
+ .asg R8.w2, RAW_DATA_LEN ;length(used for data loop) including ew and crc
+ .asg R9.b0, FIFO_BIT_IDX
+ .asg R9.b1, BASE_OFFSET
+ .asg R9.w2, BISSC_ICSSG_CHx_CFG0
+ .asg R10, BISSC_CTRL_FF
+ .asg R11.b1, BISSC_CTRL_CRC
+ .asg R11.b2, BISSC_CTRL_CMD_RES
+ .asg R11.b3, BISSC_CTRL_OTF_CRC
+ .asg R12.b0, BISSC_CMD_BIT_PTR
+ .asg R12.b1, BISSC_CTRL_CYCLE_CNTR
+ .asg R12.b2, BISSC_ENABLE_CHx_IN_USE
+ .asg R12.b3, SLAVE_OFFSET
+ .asg R13, RAW_DATA1_0 ;Includes Position data, ew and CRC
+ .asg R14, RAW_DATA2_0
+ .asg R15, RAW_DATA1_1 ;Includes Position data, ew and CRC
+ .asg R16, RAW_DATA2_1
+ .asg R17, RAW_DATA1_2 ;Includes Position data, ew and CRC
+ .asg R18, RAW_DATA2_2
+ .asg R19, BISSC_CDS_BACKUP
+ .asg R20, BISSC_FLAGS_REG
+ .asg R21, BISSC_CTRL_CMD
+ .asg R22, DAISY_CHAIN
+ .asg R23.b0, LS_SYNC_STATE
+ .asg R23.b1, PRIMARY_CORE
+ .asg R23.b2, STATUS_REG1
+ .asg R23.b3, STATUS_REG2
+ .asg R24, SCRATCH
+ .asg R25, SCRATCH1
+ .asg R26, SCRATCH2
+ .asg R27, SCRATCH3
+ .asg R29, LINK_REG
+
+
+BISSC_RX_CRCBITS .set 6
+
+; Time units below in nano sec
+
+BISSC_MAX_TBiSS_Timeout .set 40000 ;max biss timeout
+BISSC_MIN_TBiSS_Timeout .set 12500 ;min biss timeout
+BISSC_TLineDelay .set 40000 ;max Line delay
+
+BISSC_BUSY_Tbust_s .set 40000 ;max processing time for single cycle data
+BISSC_BUSY_Tbust_r .set 20000000 ;max processing time for register access
+
+BISSC_CONFIG_CH0 .set 0x1
+BISSC_CONFIG_CH1 .set (0x1 << 1)
+BISSC_CONFIG_CH2 .set (0x1 << 2)
+
+BISSC_SB_CDS_LEN .set 2
+BISSC_EW_LEN .set 2
+
+BISSC_CH0_RX_VALID_BIT_OFFSET .set 24
+BISSC_CH1_RX_VALID_BIT_OFFSET .set 25
+BISSC_CH2_RX_VALID_BIT_OFFSET .set 26
+
+
+BISSC_CH0_VALID_BIT_IDX .set 24
+BISSC_CH1_VALID_BIT_IDX .set 25
+BISSC_CH2_VALID_BIT_IDX .set 26
+
diff --git a/source/position_sense/bissc/firmware/firmware_version.h b/source/position_sense/bissc/firmware/firmware_version.h
new file mode 100644
index 0000000..7127295
--- /dev/null
+++ b/source/position_sense/bissc/firmware/firmware_version.h
@@ -0,0 +1,74 @@
+
+;
+; Copyright (C) 2023 Texas Instruments Incorporated
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions
+; are met:
+;
+; Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+;
+; Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the
+; distribution.
+;
+; Neither the name of Texas Instruments Incorporated nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;************************************************************************************
+;* File: fimware_version.h *
+;* *
+;* Brief: Defining firmware specific parameters *
+;************************************************************************************
+
+
+ .if !$isdefed("__firmware_version_h")
+__firmware_version_h .set 1
+
+; ICSS_FIRMWARE_RELEASE_1:
+; bit 31..16 reserved
+; bit15..8 device number
+FIRMWARE_DEVICE_AM335x .set 0 ; AM335x
+FIRMWARE_DEVICE_AM437x .set 1 ; AM437x
+FIRMWARE_DEVICE_AM64x .set 2 ; AM64x
+; bit7..0 protocol type
+FIRMWARE_PROTOCOL_TYPE_PROFIBUS_SLAVE .set 0x00
+FIRMWARE_PROTOCOL_TYPE_ETHERCAT_SLAVE .set 0x01
+FIRMWARE_PROTOCOL_TYPE_PROFINET_DEVICE .set 0x02
+FIRMWARE_PROTOCOL_TYPE_SERCOS_SLAVE .set 0x03
+FIRMWARE_PROTOCOL_TYPE_OPENMAC_SLAVE .set 0x04
+FIRMWARE_PROTOCOL_TYPE_ETHERNET .set 0x05
+FIRMWARE_PROTOCOL_TYPE_ENETIP_SLAVE .set 0x06
+FIRMWARE_PROTOCOL_TYPE_ENDAT_MASTER .set 0x07
+FIRMWARE_PROTOCOL_TYPE_BISSC_MASTER .set 0x08
+
+; ICSS_FIRMWARE_RELEASE_2:
+; bit31 release or internal version
+FIRMWARE_VERSION_RELEASE .set 0
+FIRMWARE_VERSION_INTERNAL .set 1
+; bit30..24 version number
+FIRMWARE_VERSION_REVISION .set 0x00
+; bit23..16 major number
+FIRMWARE_VERSION_MAJOR .set 0x00
+; bit15..0 minor number
+FIRMWARE_VERSION_MINOR .set 0x0002
+
+ICSS_FIRMWARE_RELEASE_1 .set ((FIRMWARE_DEVICE_AM64x << 8) | (FIRMWARE_PROTOCOL_TYPE_BISSC_MASTER << 0))
+ICSS_FIRMWARE_RELEASE_2 .set ((FIRMWARE_VERSION_RELEASE << 31) | (FIRMWARE_VERSION_REVISION << 24) | (FIRMWARE_VERSION_MAJOR << 16) | (FIRMWARE_VERSION_MINOR << 0))
+
+ .endif
diff --git a/source/position_sense/bissc/firmware/makefile b/source/position_sense/bissc/firmware/makefile
new file mode 100644
index 0000000..f82ee05
--- /dev/null
+++ b/source/position_sense/bissc/firmware/makefile
@@ -0,0 +1,130 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+SHELL = cmd.exe
+CCS_PATH?=C:/ti/ccs1200/ccs/ccs_base/pru/include
+CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3
+
+#Set the default mode
+CHANNELS ?= SINGLE
+
+ifeq ($(CHANNELS),MULTI)
+MULTI_CHANNEL=ENABLE_MULTI_CHANNEL
+endif
+
+ifeq ($(CHANNELS),SINGLE)
+MULTI_CHANNEL=0
+endif
+
+GEN_OPTS__FLAG :=
+GEN_CMDS__FLAG :=
+
+ORDERED_OBJS += \
+"bissc_main.obj" \
+"bissc_diagnostic.cmd" \
+$(GEN_CMDS__FLAG) \
+-llibc.a \
+
+-include ../makefile.init
+
+RM := DEL /F
+RMDIR := RMDIR /S/Q
+
+SUBDIRS := \
+. \
+
+# Add inputs and outputs from these tool invocations to the build variables
+CMD_SRCS += \
+bissc_diagnostic.cmd
+
+ASM_SRCS += \
+$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/source/position_sense/bissc/firmware/bissc_main.asm
+
+OBJS += \
+./bissc_main.obj
+
+ASM_DEPS += \
+./bissc_main.d
+
+OBJS__QUOTED += \
+"bissc_main.obj"
+
+ASM_DEPS__QUOTED += \
+"bissc_main.d"
+
+ASM_SRCS__QUOTED += \
+"$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/source/position_sense/bissc/firmware/bissc_main.asm"
+
+# Each subdirectory must supply rules for building sources it contributes
+bissc_main.obj: $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/source/position_sense/bissc/firmware/bissc_main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES)
+ @echo 'Building file: "$<"'
+ @echo 'Invoking: PRU Compiler'
+ "$(CG_TOOL_ROOT)/bin/clpru" --include_path="$(CCS_PATH)" --include_path="$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/source/position_sense/bissc/firmware" --include_path="$(CG_TOOL_ROOT)/include" --define=PRU1 --define=$(MULTI_CHANNEL) --define=icssg1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(///
+ */
+const filedirs = {
+ common: [
+ "..", /* core_os_combo base */
+ "../..", /* Example base */
+ "../../../..",
+ ],
+};
+
+const includes = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware",
+ ],
+};
+
+const defines_rtu = {
+ common: [
+ "ENABLE_MULTI_MAKE_RTU",
+
+ ],
+
+};
+const defines_pru = {
+ common: [
+
+ "ENABLE_MULTI_MAKE_PRU",
+
+ ],
+
+};
+const defines_txpru = {
+ common: [
+ "ENABLE_MULTI_MAKE_TXPRU",
+ ],
+
+};
+
+
+
+const readmeDoxygenPageTag = "BISSC_DESIGN";
+
+const cflags = {
+ common: [
+ "-v4"
+ ],
+};
+
+const lflags = {
+ common: [
+ "--entry_point=BISSC_INIT",
+ "--disable_auto_rts",
+ ],
+};
+
+
+const buildOptionCombos = [
+ { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"},
+ { device: device, cpu: "icssg0-rtupru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"},
+ { device: device, cpu: "icssg0-txpru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"},
+];
+
+let postBuildStepsPru1 = [
+ "$(CG_TOOL_ROOT)/bin/hexpru --diag_wrap=off --array --array:name_prefix=BiSSFirmwareMultiMakePRU -o bissc_master_multi_PRU_bin.h bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; mv bissc_master_multi_PRU_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/bissc_master_multi_PRU_bin.h;"
+
+];
+let postBuildStepsRtupru1 = [
+ "$(CG_TOOL_ROOT)/bin/hexpru --diag_wrap=off --array --array:name_prefix=BiSSFirmwareMultiMakeRTU -o bissc_master_multi_RTU_bin.h bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-rtupru1_fw_ti-pru-cgt.out; mv bissc_master_multi_RTU_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/bissc_master_multi_RTU_bin.h;"
+
+];
+let postBuildStepsTxpru1 = [
+ "$(CG_TOOL_ROOT)/bin/hexpru --diag_wrap=off --array --array:name_prefix=BiSSFirmwareMultiMakeTXPRU -o bissc_master_multi_TXPRU_bin.h bissc_peripheral_interface_multi_ch_load_share_am243x-evm_icssg0-txpru1_fw_ti-pru-cgt.out; mv bissc_master_multi_TXPRU_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/bissc_master_multi_TXPRU_bin.h;"
+
+];
+
+function getComponentProperty() {
+ let property = {};
+
+ property.dirPath = path.resolve(__dirname, "..");
+ property.type = "executable";
+ property.makefile = "pru";
+ property.name = "bissc_peripheral_interface_multi_ch_load_share";
+ property.isInternal = false;
+ property.description = "Bissc Multi channel Interface for Different Make Encoders"
+ property.buildOptionCombos = buildOptionCombos;
+ property.pru_main_file = "main";
+ property.pru_linker_file = "linker";
+ property.isSkipTopLevelBuild = true;
+ property.skipUpdatingTirex = true;
+ return property;
+}
+
+function getComponentBuildProperty(buildOption) {
+ let build_property = {};
+
+ build_property.files = files;
+ build_property.filedirs = filedirs;
+ build_property.includes = includes;
+ if(buildOption.cpu.match("icssg0-pru1"))
+ {
+ build_property.defines = defines_pru;
+ build_property.postBuildSteps = postBuildStepsPru1;
+ }
+ if(buildOption.cpu.match("icssg0-rtupru1"))
+ {
+ build_property.defines = defines_rtu;
+ build_property.postBuildSteps = postBuildStepsRtupru1;
+ }
+ if(buildOption.cpu.match("icssg0-txpru1"))
+ {
+ build_property.defines = defines_txpru;
+ build_property.postBuildSteps = postBuildStepsTxpru1;
+ }
+
+ build_property.cflags = cflags;
+ build_property.lflags = lflags;
+ build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
+ build_property.projecspecFileAction = "copy";
+ build_property.skipMakefileCcsBootimageGen = true;
+ return build_property;
+}
+
+module.exports = {
+ getComponentProperty,
+ getComponentBuildProperty,
+};
diff --git a/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec
new file mode 100644
index 0000000..2403f84
--- /dev/null
+++ b/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec
@@ -0,0 +1,75 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile
new file mode 100644
index 0000000..b2a0a14
--- /dev/null
+++ b/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile
@@ -0,0 +1,117 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Required input arguments:
+# MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} sdk_dir_path
+# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path
+# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path
+
+SHELL = cmd.exe
+CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include
+CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3
+SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg
+
+GEN_OPTS__FLAG :=
+GEN_CMDS__FLAG :=
+
+ORDERED_OBJS += \
+"./main.obj" \
+"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd" \
+$(GEN_CMDS__FLAG) \
+-llibc.a \
+
+-include ../makefile.init
+
+RM := DEL /F
+RMDIR := RMDIR /S/Q
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+. \
+
+# Add inputs and outputs from these tool invocations to the build variables
+CMD_SRCS += \
+${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd \
+
+ASM_SRCS += \
+${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/main.asm
+
+OBJS += \
+./main.obj
+
+ASM_DEPS += \
+./main.d
+
+OBJS__QUOTED += \
+"main.obj"
+
+ASM_DEPS__QUOTED += \
+"main.d"
+
+ASM_SRCS__QUOTED += \
+"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/main.asm"
+
+# Each subdirectory must supply rules for building sources it contributes
+main.obj: ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES)
+ @echo 'Building file: "$<"'
+ @echo 'Invoking: PRU Compiler'
+ "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM243X --define=ENABLE_MULTI_MAKE_PRU --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt/makefile b/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt/makefile
new file mode 100644
index 0000000..3f0c01b
--- /dev/null
+++ b/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt/makefile
@@ -0,0 +1,117 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Required input arguments:
+# MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} sdk_dir_path
+# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path
+# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path
+
+SHELL = cmd.exe
+CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include
+CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3
+SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg
+
+GEN_OPTS__FLAG :=
+GEN_CMDS__FLAG :=
+
+ORDERED_OBJS += \
+"./main.obj" \
+"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt/linker.cmd" \
+$(GEN_CMDS__FLAG) \
+-llibc.a \
+
+-include ../makefile.init
+
+RM := DEL /F
+RMDIR := RMDIR /S/Q
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+. \
+
+# Add inputs and outputs from these tool invocations to the build variables
+CMD_SRCS += \
+${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-rtupru1_fw/ti-pru-cgt/linker.cmd \
+
+ASM_SRCS += \
+${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/main.asm
+
+OBJS += \
+./main.obj
+
+ASM_DEPS += \
+./main.d
+
+OBJS__QUOTED += \
+"main.obj"
+
+ASM_DEPS__QUOTED += \
+"main.d"
+
+ASM_SRCS__QUOTED += \
+"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/main.asm"
+
+# Each subdirectory must supply rules for building sources it contributes
+main.obj: ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES)
+ @echo 'Building file: "$<"'
+ @echo 'Invoking: PRU Compiler'
+ "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM243X --define=ENABLE_MULTI_MAKE_RTU --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt/makefile b/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt/makefile
new file mode 100644
index 0000000..a04df44
--- /dev/null
+++ b/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt/makefile
@@ -0,0 +1,117 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Required input arguments:
+# MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} sdk_dir_path
+# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path
+# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path
+
+SHELL = cmd.exe
+CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include
+CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3
+SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg
+
+GEN_OPTS__FLAG :=
+GEN_CMDS__FLAG :=
+
+ORDERED_OBJS += \
+"./main.obj" \
+"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt/linker.cmd" \
+$(GEN_CMDS__FLAG) \
+-llibc.a \
+
+-include ../makefile.init
+
+RM := DEL /F
+RMDIR := RMDIR /S/Q
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+. \
+
+# Add inputs and outputs from these tool invocations to the build variables
+CMD_SRCS += \
+${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/am243x-evm/icssg0-txpru1_fw/ti-pru-cgt/linker.cmd \
+
+ASM_SRCS += \
+${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/main.asm
+
+OBJS += \
+./main.obj
+
+ASM_DEPS += \
+./main.d
+
+OBJS__QUOTED += \
+"main.obj"
+
+ASM_DEPS__QUOTED += \
+"main.d"
+
+ASM_SRCS__QUOTED += \
+"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/main.asm"
+
+# Each subdirectory must supply rules for building sources it contributes
+main.obj: ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_load_share/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES)
+ @echo 'Building file: "$<"'
+ @echo 'Invoking: PRU Compiler'
+ "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DTX_PRU1 -DSLICE1 -DPRU1 -DSLICE1 -v4 --define=SOC_AM243X --define=ENABLE_MULTI_MAKE_TXPRU --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(///
+ */
+const filedirs = {
+ common: [
+ "..", /* core_os_combo base */
+ "../..", /* Example base */
+ "../../../..",
+
+ ],
+};
+
+const includes = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware",
+ ],
+};
+
+const defines = {
+ common: [
+ "ENABLE_MULTI_CHANNEL",
+ ],
+};
+
+
+
+const readmeDoxygenPageTag = "BISSC_DESIGN";
+
+const cflags = {
+ common: [
+ "-v4"
+ ],
+};
+
+const lflags = {
+ common: [
+ "--entry_point=BISSC_INIT",
+ "--disable_auto_rts",
+ ],
+};
+
+
+const buildOptionCombos = [
+ { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"},
+];
+
+let postBuildSteps = [
+ "$(CG_TOOL_ROOT)/bin/hexpru --diag_wrap=off --array --array:name_prefix=BiSSFirmwareMulti -o bissc_master_multi_bin.h bissc_peripheral_interface_multi_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; mv bissc_master_multi_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/bissc_master_multi_bin.h;"
+
+];
+function getComponentProperty() {
+ let property = {};
+
+ property.dirPath = path.resolve(__dirname, "..");
+ property.type = "executable";
+ property.makefile = "pru";
+ property.name = "bissc_peripheral_interface_multi_ch";
+ property.isInternal = false;
+ property.description = "BiSSC Multi Channel Interface for Same make encoders"
+ property.buildOptionCombos = buildOptionCombos;
+ property.pru_main_file = "main";
+ property.pru_linker_file = "linker";
+ property.isSkipTopLevelBuild = true;
+ property.skipUpdatingTirex = true;
+ property.postBuildSteps = postBuildSteps;
+ return property;
+}
+
+function getComponentBuildProperty(buildOption) {
+ let build_property = {};
+
+ build_property.files = files;
+ build_property.filedirs = filedirs;
+ build_property.includes = includes;
+ build_property.defines = defines;
+ build_property.cflags = cflags;
+ build_property.lflags = lflags;
+ build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
+ build_property.projecspecFileAction = "copy";
+ build_property.skipMakefileCcsBootimageGen = true;
+
+ return build_property;
+}
+
+module.exports = {
+ getComponentProperty,
+ getComponentBuildProperty,
+};
diff --git a/source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec
new file mode 100644
index 0000000..4606a66
--- /dev/null
+++ b/source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec
@@ -0,0 +1,75 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile
new file mode 100644
index 0000000..75a67b0
--- /dev/null
+++ b/source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile
@@ -0,0 +1,117 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Required input arguments:
+# MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} sdk_dir_path
+# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path
+# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path
+
+SHELL = cmd.exe
+CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include
+CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3
+SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg
+
+GEN_OPTS__FLAG :=
+GEN_CMDS__FLAG :=
+
+ORDERED_OBJS += \
+"./main.obj" \
+"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd" \
+$(GEN_CMDS__FLAG) \
+-llibc.a \
+
+-include ../makefile.init
+
+RM := DEL /F
+RMDIR := RMDIR /S/Q
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+. \
+
+# Add inputs and outputs from these tool invocations to the build variables
+CMD_SRCS += \
+${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_single_pru/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd \
+
+ASM_SRCS += \
+${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_single_pru/main.asm
+
+OBJS += \
+./main.obj
+
+ASM_DEPS += \
+./main.d
+
+OBJS__QUOTED += \
+"main.obj"
+
+ASM_DEPS__QUOTED += \
+"main.d"
+
+ASM_SRCS__QUOTED += \
+"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_single_pru/main.asm"
+
+# Each subdirectory must supply rules for building sources it contributes
+main.obj: ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/multi_channel_single_pru/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES)
+ @echo 'Building file: "$<"'
+ @echo 'Invoking: PRU Compiler'
+ "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM243X --define=ENABLE_MULTI_CHANNEL --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(///
+ */
+const filedirs = {
+ common: [
+ "..", /* core_os_combo base */
+ "../../..", /* Example base */
+ "../../../..",
+ ],
+};
+
+const includes = {
+ common: [
+ "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware",
+ ],
+};
+
+const defines = {
+ common: [
+
+ ],
+};
+/*const lnkfiles = {
+ common: [
+ "linker.cmd",
+ ]
+};*/
+
+
+const readmeDoxygenPageTag = "BISSC_DESIGN";
+
+const cflags = {
+ common: [
+ "-v4"
+ ],
+};
+
+const lflags = {
+ common: [
+ "--entry_point=BISSC_INIT",
+ "--disable_auto_rts",
+ ],
+};
+
+
+const buildOptionCombos = [
+ { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"},
+];
+
+let postBuildSteps = [
+ "$(CG_TOOL_ROOT)/bin/hexpru --diag_wrap=off --array --array:name_prefix=BiSSFirmware -o bissc_master_bin.h bissc_peripheral_interface_single_ch_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out; mv bissc_master_bin.h ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/bissc_master_bin.h;"
+
+];
+function getComponentProperty() {
+ let property = {};
+
+ property.dirPath = path.resolve(__dirname, "..");
+ property.type = "executable";
+ property.makefile = "pru";
+ property.name = "bissc_peripheral_interface_single_ch";
+ property.isInternal = false;
+ property.description = "BiSSC Peripheral Interface"
+ property.buildOptionCombos = buildOptionCombos;
+ property.pru_main_file = "main";
+ property.pru_linker_file = "linker";
+ property.isSkipTopLevelBuild = true;
+ property.skipUpdatingTirex = true;
+ property.postBuildSteps = postBuildSteps;
+ return property;
+}
+
+function getComponentBuildProperty(buildOption) {
+ let build_property = {};
+
+ build_property.files = files;
+ build_property.filedirs = filedirs;
+ build_property.includes = includes;
+ build_property.defines = defines;
+ build_property.cflags = cflags;
+ build_property.lflags = lflags;
+ build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
+ build_property.projecspecFileAction = "copy";
+ build_property.skipMakefileCcsBootimageGen = true;
+
+ return build_property;
+}
+
+module.exports = {
+ getComponentProperty,
+ getComponentBuildProperty,
+};
diff --git a/source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec b/source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec
new file mode 100644
index 0000000..78cb2f9
--- /dev/null
+++ b/source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec
@@ -0,0 +1,74 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile b/source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile
new file mode 100644
index 0000000..1be8006
--- /dev/null
+++ b/source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile
@@ -0,0 +1,117 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Required input arguments:
+# MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} sdk_dir_path
+# CCS_INSTALL_DIR=${CCS_INSTALL_DIR} ccs_dir_path
+# CCS_PROJECT_DEBUG=${CWD} project_debug_dir_path
+
+SHELL = cmd.exe
+CCS_PATH?=$(CCS_INSTALL_DIR)/ccs_base/pru/include
+CG_TOOL_ROOT := C:/ti/ti-cgt-pru_2.3.3
+SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg
+
+GEN_OPTS__FLAG :=
+GEN_CMDS__FLAG :=
+
+ORDERED_OBJS += \
+"./main.obj" \
+"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd" \
+$(GEN_CMDS__FLAG) \
+-llibc.a \
+
+-include ../makefile.init
+
+RM := DEL /F
+RMDIR := RMDIR /S/Q
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+. \
+
+# Add inputs and outputs from these tool invocations to the build variables
+CMD_SRCS += \
+${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/single_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/linker.cmd \
+
+ASM_SRCS += \
+${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/single_channel/main.asm
+
+OBJS += \
+./main.obj
+
+ASM_DEPS += \
+./main.d
+
+OBJS__QUOTED += \
+"main.obj"
+
+ASM_DEPS__QUOTED += \
+"main.d"
+
+ASM_SRCS__QUOTED += \
+"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/single_channel/main.asm"
+
+# Each subdirectory must supply rules for building sources it contributes
+main.obj: ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware/single_channel/main.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES)
+ @echo 'Building file: "$<"'
+ @echo 'Invoking: PRU Compiler'
+ "$(CG_TOOL_ROOT)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 -v4 --define=SOC_AM243X --include_path="$(CCS_PATH)" --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/firmware" --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(
+#include
+#include
+#include
+#include
+#define BISSC_MODE_SINGLE_CHANNEL_SINGLE_PRU (0U)
+#define BISSC_MODE_MULTI_CHANNEL_SINGLE_PRU (1U)
+#define BISSC_MODE_MULTI_CHANNEL_MULTI_PRU (2U)
+
+#define BISSC_NUM_BITS_POSITION_CRC 6
+#define BISSC_NUM_BITS_EW 2
+#define BISSC_NUM_BITS_ADDRESS 8
+
+#define BISSC_MAX_CYCLE_TIMEOUT 5
+#define NUM_ED_CH_MAX 3
+#define NUM_SLAVE_MAX 3
+/* Max processing delay at 1 MHz is 40 us as per spec - values are in valid bits*/
+#define BISSC_MAX_PROC_DELAY_1MHZ 40
+#define BISSC_MAX_PROC_DELAY_2MHZ 80
+#define BISSC_MAX_PROC_DELAY_5MHZ 200
+#define BISSC_MAX_PROC_DELAY_8MHZ 320
+#define BISSC_MAX_PROC_DELAY_10MHZ 400
+
+#define BISSC_RX_SAMPLE_SIZE 7 /* 8x over clock */
+#define BISSC_RX_SAMPLE_SIZE_10MHZ 3 /* 4x over clock */
+#define BISSC_POS_CRC_LEN 6
+#define BISSC_EW_LEN 2
+#define BISSC_CTRL_CMD_CRC_LEN 4
+#define BISSC_POS_DATA_LEN_DEFAULT 12
+
+#define BISSC_INPUT_CLOCK_UART_FREQUENCY 192000000
+#define BISSC_INPUT_CLOCK_OCP_FREQUENCY 200000000
+#define BISSC_INPUT_CLOCK_FREQUENCY_UART BISSC_INPUT_CLOCK_UART_FREQUENCY
+/**
+ * \brief Structure defining EnDat clock configuration for selected frequency
+ *
+ * \details Rx, Tx divisors for selected frequency, oversampling rate, ocp/uart clock source status.
+ *
+ */
+struct bissc_clk_cfg
+{
+ uint16_t rx_div;
+ /**< Rx divisor for selected frequency*/
+ uint16_t tx_div;
+ /**< Tx divisor for selected frequency*/
+ uint16_t rx_div_attr;
+ /**< Rx oversampling rate*/
+ uint16_t is_ocp;
+ /**< status for ocp clock source*/
+};
+/**
+ * \brief Structure defining BiSSC Position data results
+ *
+ * \details position data result(raw data, angle and number of turns), error-warning, 6-bit received crc, 6-bit otf crc.
+ */
+struct bissc_position_info
+{
+ uint64_t position[NUM_SLAVE_MAX];
+ /**< Position data results from each encoder connected in daisy chain*/
+ float angle[NUM_SLAVE_MAX];
+ /**< Single turn result(Angle) for each encoder connected in daisy chain*/
+ uint32_t num_of_turns[NUM_SLAVE_MAX];
+ /**< Multi turn result(No. of rotations) for each encoder connected in daisy chain*/
+ uint8_t ew[NUM_SLAVE_MAX];
+ /**< Error and Warning result for each encoder connected in daisy chain*/
+ uint8_t rcv_crc[NUM_SLAVE_MAX];
+ /**< received 6-bit crc for each encoder connected in daisy chain*/
+ uint8_t otf_crc[NUM_SLAVE_MAX];
+ /**< Calculated otf 6-bit crc for each encoder connected in daisy chain*/
+};
+/**
+ * \brief Structure defining BiSSC Channel specific control communication(ctrl) results
+ *
+ * \details cds results, ctrl 4 bit received crc and ctrl otf crc.
+ *
+ */
+struct bissc_control_info
+{
+ uint8_t cmd_result;
+ /**< Control communication result received from the encoder*/
+ uint8_t cmd_rcv_crc;
+ /**< Control Communication received 4-bit crc*/
+ uint8_t cmd_otf_crc;
+ /**< Control Communication calculated otf crc*/
+};
+/**
+ * \brief Initialize BiSS-C firmware interface address and get the pointer to struct bissc_priv instance
+ *
+ * \details contains ICSS slice, load share, data lengths, channel, safety specific information and a pointer to bissc_pruicss_xchg structure.
+ *
+ */
+struct bissc_priv
+{
+ int32_t pruicss_slicex;
+ /**< PRU ICSS slice number*/
+ int32_t load_share;
+ /**< Load share flag*/
+ int32_t data_len[NUM_ED_CH_MAX][NUM_SLAVE_MAX];
+ /**< Resolution of each encoder connected in daisy chain config to each channel*/
+ int32_t single_turn_len[NUM_ED_CH_MAX][NUM_SLAVE_MAX];
+ /**< Single turn resolution of each encoder connected in daisy chain config to each channel*/
+ int32_t multi_turn_len[NUM_ED_CH_MAX][NUM_SLAVE_MAX];
+ /**< Multi turn resolution of each encoder connected in daisy chain config to each channel*/
+ int32_t channel[NUM_ED_CH_MAX];
+ /**< Array of all configured channel*/
+ struct bissc_pruicss_xchg *pruicss_xchg;
+ /**< Structure defining BiSSC interface*/
+ int32_t has_safety;
+ /**< status for safety support*/
+ void *pruicss_cfg;
+ /**< PRU-ICSS cfg registers base offset*/
+ int64_t raw_data;
+ /**< Raw data received from encoder*/
+ struct bissc_position_info enc_pos_data[NUM_ED_CH_MAX];
+ /**< Structure containing encoders position data results for each channel*/
+ struct bissc_control_info enc_ctrl_data[NUM_ED_CH_MAX];
+ /**< Structure containing encoders control communication results for each PRU*/
+ int32_t pd_crc_err_cnt[NUM_ED_CH_MAX][NUM_SLAVE_MAX];
+ /**< position data crc error count for each encoder connected in daisy chain to each channel*/
+ int32_t ctrl_crc_err_cnt[NUM_ED_CH_MAX];
+ /**< control communication crc error count for each encoder connected to each PRU in load share*/
+ int32_t num_slaves[NUM_ED_CH_MAX];
+ /**< Number of slaves connected in daisy chain to each PRU in load share*/
+ int32_t totalchannels;
+ /**< Total number of channels configured*/
+};
+
+
+#include "bissc_api.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/source/position_sense/bissc/include/bissc_interface.h b/source/position_sense/bissc/include/bissc_interface.h
new file mode 100644
index 0000000..9539a89
--- /dev/null
+++ b/source/position_sense/bissc/include/bissc_interface.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef BISSC_INTERFACE_H_
+#define BISSC_INTERFACE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros */
+/* ========================================================================== */
+
+
+/* ========================================================================== */
+/* Structures */
+/* ========================================================================== */
+/**
+ * \brief Structure defining BiSSC Raw data received from encoder.
+ *
+ */
+struct raw_data{
+ volatile uint32_t pos_data_word0;
+ /**< Initial (<=32) position bits received */
+ volatile uint32_t pos_data_word1;
+ /**< position bits received after the initial 32 bits (if applicable) */
+};
+/**
+ * \brief Structure defining BiSSC Position data lengths of conected encoder.
+ *
+ * \details number of slaves connected in daisy chain, and their position data lengths(resolution).
+ */
+struct enc_len{
+ volatile uint8_t num_slaves;
+ /**< Number of Encoders connected */
+ volatile uint8_t data_len[3];
+ /**< Data length of individual encoder connected in daisy chain*/
+};
+/**
+ * \brief Structure defining BiSSC Position data results.
+ *
+ * \details raw data, position data crc error count, 6-bit otf crc.
+ */
+struct pos_data_res{
+ struct raw_data raw_data[3];
+ /**< Structure defining BiSSC Raw data received from encoder*/
+ volatile uint32_t pd_crc_err_cnt[3];
+ /**< Position data CRC error count */
+ volatile uint8_t pos_data_otf_crc[3];
+ /**< position data otf crc bits*/
+};
+/**
+ * \brief Structure defining BiSSC Channel specific control communication(ctrl) results
+ *
+ * \details ctrl crc error count,cds results, ctrl 4 bit received crc and ctrl otf crc.
+ *
+ */
+struct ctrl_res
+{
+ volatile uint32_t ctrl_crc_err_cnt;
+ /**< control communication CRC error count */
+ volatile uint8_t ctrl_cds_res;
+ /**< control communication result*/
+ volatile uint8_t ctrl_rcvd_crc;
+ /**< control communication crc received*/
+ volatile uint8_t ctrl_otf_crc;
+ /**< control communication otf crc computed*/
+};
+/**
+ * \brief Structure defining BiSSC interface
+ *
+ * \details Firmware config, command and channel interface
+ *
+ */
+struct bissc_pruicss_xchg
+{
+ volatile uint8_t pos_crc_len;
+ /**< Position data CRC length */
+ volatile uint8_t rx_clk_freq;
+ /**< Clock frequency */
+ volatile uint8_t ctrl_cmd_crc_len;
+ /**< Control command CRC length */
+ volatile uint8_t channel;
+ /**< Channel configuration */
+
+ volatile uint8_t status[3];
+ /**< Firmware initialization status */
+ volatile uint8_t primary_core_mask;
+ /**< Primary core mask incase of load share */
+ volatile uint8_t cycle_trigger[3];
+ /**< BiSSC cycle complete status */
+ volatile uint8_t measure_proc_delay;
+ /**< measure processing delay - do this for every config change */
+
+ struct enc_len enc_len[3];
+ /**< position data lengths(resolution) of BiSSC encoders connected */
+
+ volatile uint8_t valid_bit_idx;
+ /**< channel Bit Index */
+ volatile uint8_t fifo_bit_idx;
+ /**< Fifo Bit Index(middle bit) */
+ volatile uint8_t ctrl_cmd_status[3];
+ /**< control communication status */
+
+ volatile uint16_t proc_delay[3];
+ /**< automatically estimated processing delay */
+
+
+ volatile uint32_t ctrl_cmd[3];
+ /**< Hex equivalent Control command */
+
+ volatile uint32_t max_proc_delay;
+ /**< maximum processing delay for selected frequency */
+
+ struct pos_data_res pos_data_res[3];
+ /**< Channel specific position data results*/
+
+ struct ctrl_res ctrl_res[3];
+ /**< Channel specific control communication results*/
+
+ volatile uint8_t execution_state[3];
+ /**< Execution state for different channels in load share */
+
+ volatile uint64_t register_backup[3];
+ /**< Backup registers for ch0 - ch2 */
+
+ volatile uint8_t bissc_re_measure_proc_delay;
+
+ volatile uint32_t delay_40us;
+ /**< BiSS-C Timeout delay */
+
+ volatile uint32_t delay_100ms;
+ /**< BiSS-C max interframe delay */
+
+ volatile uint64_t icssg_clk;
+ /**< ICSSG core clock frequency */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/source/position_sense/bissc/makefile.am243x.r5f.ti-arm-clang b/source/position_sense/bissc/makefile.am243x.r5f.ti-arm-clang
new file mode 100644
index 0000000..9d8d6da
--- /dev/null
+++ b/source/position_sense/bissc/makefile.am243x.r5f.ti-arm-clang
@@ -0,0 +1,119 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+
+CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
+
+CC=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmclang
+AR=$(CGT_TI_ARM_CLANG_PATH)/bin/tiarmar
+
+PROFILE?=release
+ConfigName:=$(PROFILE)
+
+LIBNAME:=motorcontrol_bissc.am243x.r5f.ti-arm-clang.$(PROFILE).lib
+
+FILES_common := \
+ bissc_drv.c \
+
+FILES_PATH_common = \
+ ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/driver \
+
+INCLUDES_common := \
+ -I${CG_TOOL_ROOT}/include/c \
+ -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source \
+ -I${MOTOR_CONTROL_SDK_PATH}/source \
+ -I${MOTOR_CONTROL_SDK_PATH}/source/position_sense/bissc/include \
+
+DEFINES_common := \
+ -DSOC_AM243X \
+
+CFLAGS_common := \
+ -mcpu=cortex-r5 \
+ -mfloat-abi=hard \
+ -mfpu=vfpv3-d16 \
+ -mthumb \
+ -Wall \
+ -Werror \
+ -g \
+ -Wno-gnu-variable-sized-type-not-at-end \
+ -Wno-unused-function \
+
+CFLAGS_cpp_common := \
+ -Wno-c99-designator \
+ -Wno-extern-c-compat \
+ -Wno-c++11-narrowing \
+ -Wno-reorder-init-list \
+ -Wno-deprecated-register \
+ -Wno-writable-strings \
+ -Wno-enum-compare \
+ -Wno-reserved-user-defined-literal \
+ -Wno-unused-const-variable \
+ -x c++ \
+
+CFLAGS_debug := \
+ -D_DEBUG_=1 \
+
+CFLAGS_release := \
+ -Os \
+
+ARFLAGS_common := \
+ rc \
+
+FILES := $(FILES_common) $(FILES_$(PROFILE))
+ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
+FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
+CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+ASMFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+ifeq ($(CPLUSPLUS_BUILD), yes)
+CFLAGS += $(CFLAGS_cpp_common)
+endif
+DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
+INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
+ARFLAGS := $(ARFLAGS_common) $(ARFLAGS_$(PROFILE))
+
+LIBDIR := lib
+OBJDIR := obj/am243x/ti-arm-clang/$(PROFILE)/r5f/motorcontrol_bissc/
+OBJS := $(FILES:%.c=%.obj)
+OBJS += $(ASMFILES:%.S=%.obj)
+DEPS := $(FILES:%.c=%.d)
+
+vpath %.obj $(OBJDIR)
+vpath %.c $(FILES_PATH)
+vpath %.S $(FILES_PATH)
+
+$(OBJDIR)/%.obj %.obj: %.c
+ @echo Compiling: $(LIBNAME): $<
+ $(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.S
+ @echo Compiling: $(LIBNAME): $<
+ $(CC) -c $(ASMFLAGS) -o $(OBJDIR)/$@ $<
+
+all: $(LIBDIR)/$(LIBNAME)
+
+$(LIBDIR)/$(LIBNAME): $(OBJS) | $(LIBDIR)
+ @echo .
+ @echo Archiving: $(LIBNAME) to $@ ...
+ $(AR) $(ARFLAGS) $@ $(addprefix $(OBJDIR), $(OBJS))
+ @echo Archiving: $(LIBNAME) Done !!!
+ @echo .
+
+clean:
+ @echo Cleaning: $(LIBNAME) ...
+ $(RMDIR) $(OBJDIR)
+ $(RM) $(LIBDIR)/$(LIBNAME)
+
+scrub:
+ @echo Scrubing: $(LIBNAME) ...
+ -$(RMDIR) obj/
+ -$(RMDIR) lib/
+
+$(OBJS): | $(OBJDIR)
+
+$(LIBDIR) $(OBJDIR):
+ $(MKDIR) $@
+
+-include $(addprefix $(OBJDIR)/, $(DEPS))
|