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am64x/am243x: HDSL: Multi-channel Sync Mode bugs

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- Multiple setups fix
 - Multiple encoders fix

Fixes: PINDSW-6893

Signed-off-by: Rajul Bhambay <r-bhambay@ti.com>
This commit is contained in:
Rajul Bhambay 2023-09-13 16:07:23 +05:30
commit 0d9a5d95eb
40 changed files with 439 additions and 3466 deletions
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32
.metadata/.tirex/am243x.content.tirex.json
View File

@ -230,38 +230,6 @@
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Hdsl Diagnostic Ddr Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "hdsl_diagnostic_ddr",
"location": "../../examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM243x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"position_sense",
"hdsl_diagnostic_with_traces",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [

32
.metadata/.tirex/am64x.content.tirex.json
View File

@ -164,38 +164,6 @@
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [
"example"
],
"resourceSubClass": [
"example.general"
],
"description": "A Hdsl Diagnostic Ddr Example. CPU is R5FSS0-0 running FREERTOS.",
"name": "hdsl_diagnostic_ddr",
"location": "../../examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
"devtools": [
"AM64x_GP_EVM"
],
"kernel": [
"freertos"
],
"compiler": [
"ticlang"
],
"subCategories": [
"position_sense",
"hdsl_diagnostic_with_traces",
"r5fss0-0_freertos"
],
"mainCategories": [
[
"Examples",
"Development Tools"
]
]
},
{
"resourceType": "project.ccs",
"resourceClass": [

1
.project/device/project_am243x.js
View File

@ -19,7 +19,6 @@ const example_file_list = [
"examples/position_sense/endat_diagnostic/multi_channel_single_pru/.project/project.js",
"examples/position_sense/hdsl_diagnostic/multi_channel/.project/project.js",
"examples/position_sense/hdsl_diagnostic/single_channel/.project/project.js",
"examples/position_sense/hdsl_diagnostic_with_traces/.project/project.js",
"examples/position_sense/tamagawa_diagnostic/multi_channel/.project/project.js",
"examples/position_sense/tamagawa_diagnostic/single_channel/.project/project.js",
"examples/current_sense/icss_sdfm/.project/project.js",

1
.project/device/project_am64x.js
View File

@ -19,7 +19,6 @@ const example_file_list = [
"examples/position_sense/endat_diagnostic/multi_channel_single_pru/.project/project.js",
"examples/position_sense/hdsl_diagnostic/multi_channel/.project/project.js",
"examples/position_sense/hdsl_diagnostic/single_channel/.project/project.js",
"examples/position_sense/hdsl_diagnostic_with_traces/.project/project.js",
"examples/position_sense/tamagawa_diagnostic/multi_channel/.project/project.js",
"examples/position_sense/tamagawa_diagnostic/single_channel/.project/project.js",
"examples/current_sense/icss_sdfm/.project/project.js",

606
examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c
View File

@ -46,6 +46,7 @@
#include <kernel/dpl/ClockP.h>
#include <drivers/pruicss.h>
#include <drivers/udma.h>
#include "ti_drivers_config.h"
#include "ti_drivers_open_close.h"
@ -69,6 +70,11 @@
#include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h>
#include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h>
#include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h>
#if (CONFIG_HDSL0_CHANNEL0 + CONFIG_HDSL0_CHANNEL1 > 1)
#define HDSL_MULTI_CHANNEL
#endif
/* Divide factor for normal clock (default value for 300 MHz=31) */
#define DIV_FACTOR_NORMAL 31
/* Divide factor for oversampled clock (default value for 300 MHz=3) */
@ -100,40 +106,231 @@
#define ENCODER_RSSI_REG_ADDRESS (0x7C)
#define ENCODER_PING_REG_ADDRESS (0x7F)
extern PRUICSS_Config gPruicssConfig[2];
struct hdslvariables *hdslvariables;
#ifndef HDSL_MULTI_CHANNEL
/* Memory Trace is triggered for each H-Frame. SYS_EVENT_21 is triggered for each
H-Frame from PRU. SYS_EVENT_21 is mapped to PRU_ICSSG0_PR1_HOST_INTR_PEND_3 of R5F
in INTC Mapping. */
/*Event number for SYS_EVENT_21 (pr1_pru_mst_intr<5>_int_req) */
#define HDSL_MEMORY_TRACE_ICSS_INTC_EVENT_NUM (21U)
/* R5F Interrupt number for Memory Traces */
#define HDSL_MEMORY_TRACE_R5F_IRQ_NUM (CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_3)
#endif
HwiP_Object gPRUHwiObject;
/** \brief Global Structure pointer holding PRUSS1 memory Map. */
PRUICSS_Handle gPruIcss0Handle;
HDSL_Handle gHdslHandleCh0;
HDSL_Handle gHdslHandleCh1;
HDSL_Handle gHdslHandleCh2;
PRUICSS_Handle gPruIcss0Handle;
PRUICSS_IntcInitData gPruss0_intc_initdata = PRU_ICSS0_INTC_INITDATA;
PRUICSS_Handle gPruIcss1Handle;
PRUICSS_IntcInitData gPruss1_intc_initdata = PRU_ICSS1_INTC_INITDATA;
static char gUart_buffer[256];
static void *gPru_cfg;
void *gPru_dramx;
void *gPru_dramx_0;
void *gPru_dramx_1;
int get_pos=1;
int32_t get_pos=1;
uint32_t gMulti_turn, gRes;
uint64_t gMask;
uint8_t gPc_data;
uint8_t gPc_addrh, gPc_addrl, gPc_offh, gPc_offl, gPc_buf0, gPc_buf1, gPc_buf2, gPc_buf3, gPc_buf4, gPc_buf5, gPc_buf6, gPc_buf7;
#ifdef HDSL_AM64xE1_TRANSCEIVER
static TCA6424_Config gTCA6424_Config;
#endif
#ifndef HDSL_MULTI_CHANNEL
Udma_ChHandle chHandle;
/* To store user input to start memory copy*/
volatile uint8_t start_copy;
/* To store user input number of count of memory copy*/
uint16_t trace_count;
/* To save log h-frame count during memory copy*/
uint32_t h_frame_count_arr[NUM_RESOURCES];
/* Location for copying HDSL Interface structure */
HDSL_Interface gHdslInterfaceTrace[NUM_RESOURCES] __attribute__((aligned(128), section(".hdslInterface_mem")));
HwiP_Object gPRUHwiObject;
/* UDMA TRPD Memory */
uint8_t gUdmaTestTrpdMem[UDMA_TEST_TRPD_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
#endif
#ifndef HDSL_MULTI_CHANNEL
void App_udmaEventCb(Udma_EventHandle eventHandle, uint32_t eventType, void *appData);
static void App_udmaTrpdInit(Udma_ChHandle chHandle,
uint8_t *trpdMem,
const void *destBuf,
const void *srcBuf,
uint32_t length);
static void App_udmaTrpdInit(Udma_ChHandle chHandle,
uint8_t *trpdMem,
const void *destBuf,
const void *srcBuf,
uint32_t length)
{
CSL_UdmapTR15 *pTr;
uint32_t cqRingNum = Udma_chGetCqRingNum(chHandle);
static uint32_t initDone = 0;
if(initDone == 0)
{
/* Make TRPD with TR15 TR type */
UdmaUtils_makeTrpdTr15(trpdMem, 1U, cqRingNum);
/* Setup TR */
pTr = UdmaUtils_getTrpdTr15Pointer(trpdMem, 0U);
pTr->flags = CSL_FMK(UDMAP_TR_FLAGS_TYPE, CSL_UDMAP_TR_FLAGS_TYPE_4D_BLOCK_MOVE_REPACKING_INDIRECTION);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_STATIC, 0U);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOL, CSL_UDMAP_TR_FLAGS_EOL_MATCH_SOL_EOL);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EVENT_SIZE, CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0_TYPE, CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1_TYPE, CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_CMD_ID, 0x25U); /* This will come back in TR response */
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_SA_INDIRECT, 0U);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_DA_INDIRECT, 0U);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOP, 1U);
pTr->icnt0 = length;
pTr->icnt1 = 1U;
pTr->icnt2 = 1U;
pTr->icnt3 = 1U;
pTr->dim1 = pTr->icnt0;
pTr->dim2 = (pTr->icnt0 * pTr->icnt1);
pTr->dim3 = (pTr->icnt0 * pTr->icnt1 * pTr->icnt2);
pTr->addr = (uint64_t) Udma_defaultVirtToPhyFxn(srcBuf, 0U, NULL);
pTr->fmtflags = 0x00000000U; /* Linear addressing, 1 byte per elem */
pTr->dicnt0 = length;
pTr->dicnt1 = 1U;
pTr->dicnt2 = 1U;
pTr->dicnt3 = 1U;
pTr->ddim1 = pTr->dicnt0;
pTr->ddim2 = (pTr->dicnt0 * pTr->dicnt1);
pTr->ddim3 = (pTr->dicnt0 * pTr->dicnt1 * pTr->dicnt2);
pTr->daddr = (uint64_t) Udma_defaultVirtToPhyFxn(destBuf, 0U, NULL);
/* Perform cache writeback */
CacheP_wb(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD);
initDone = 1;
}
else
{
pTr = UdmaUtils_getTrpdTr15Pointer(trpdMem, 0U);
pTr->daddr = (uint64_t) Udma_defaultVirtToPhyFxn(destBuf, 0U, NULL);
/* Perform cache writeback */
CacheP_wb(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD);
}
return;
}
void udma_copy(uint8_t *srcBuf, uint8_t *destBuf, uint32_t length)
{
int32_t retVal = UDMA_SOK;
uint64_t pDesc;
uint32_t trRespStatus;
uint8_t *trpdMem = &gUdmaTestTrpdMem[0U];
uint64_t trpdMemPhy = (uint64_t) Udma_defaultVirtToPhyFxn(trpdMem, 0U, NULL);
/* Init TR packet descriptor */
App_udmaTrpdInit(chHandle, trpdMem, destBuf, srcBuf, length);
/* Submit TRPD to channel */
retVal = Udma_ringQueueRaw(Udma_chGetFqRingHandle(chHandle), trpdMemPhy);
DebugP_assert(UDMA_SOK == retVal);
/* Wait for return descriptor in completion ring - this marks transfer completion */
while(1)
{
retVal = Udma_ringDequeueRaw(Udma_chGetCqRingHandle(chHandle), &pDesc);
if(UDMA_SOK == retVal)
{
/* Check TR response status */
CacheP_inv(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD);
trRespStatus = UdmaUtils_getTrpdTr15Response(trpdMem, 1U, 0U);
DebugP_assert(CSL_UDMAP_TR_RESPONSE_STATUS_COMPLETE == trRespStatus);
break;
}
}
/* Validate data in destination memory */
CacheP_inv(destBuf, length, CacheP_TYPE_ALLD);
}
static void HDSL_IsrFxn()
{
static uint64_t h_frames_count = 0;
static uint32_t temp = 0;
uint8_t *srcBuf;
uint8_t *destBuf;
uint32_t length;
srcBuf = (uint8_t*)HDSL_get_src_loc(gHdslHandleCh0);
length = HDSL_get_length(gHdslHandleCh0);
PRUICSS_clearEvent(gPruIcss0Handle, HDSL_MEMORY_TRACE_ICSS_INTC_EVENT_NUM);
/* No of h-frames count */
h_frames_count++;
if((start_copy == 1) && (temp < trace_count))
{
/* Init buffers and TR packet descriptor */
destBuf = (uint8_t*)&gHdslInterfaceTrace[temp];
/* start UDMA copying data from src to dest */
udma_copy(srcBuf,destBuf,length);
h_frame_count_arr[temp] = h_frames_count;
temp++;
}
else
{
start_copy = 0;
temp = 0;
}
}
void traces_into_memory(HDSL_Handle hdslHandle)
{
int32_t i= 0;
uint32_t length;
length = HDSL_get_length(hdslHandle);
DebugP_log("\r\n sizeof(hdslInterface)_count = %u", length);
DebugP_log("\r\n Start address of memory trace location = %x", &gHdslInterfaceTrace[0]);
DebugP_log("\r\n End address of memory trace location = %x", &gHdslInterfaceTrace[NUM_RESOURCES-1]);
DebugP_log("\r\n No of HDSL-Interface-Register-Structure to copy = %u", trace_count);
start_copy = 1;
while(start_copy)
{
ClockP_sleep(1);
}
for(i=0; i< trace_count; i++)
{
DebugP_log("\r\n %u h_frame_count = %u ",i, h_frame_count_arr[i]);
}
}
#endif
void sync_calculation(HDSL_Handle hdslHandle)
{
uint8_t ES;
@ -244,7 +441,8 @@ void sync_calculation(HDSL_Handle hdslHandle)
}
void process_request(HDSL_Handle hdslHandle,int menu){
void process_request(HDSL_Handle hdslHandle,int32_t menu)
{
uint64_t ret_status=0;
uint64_t val0, val1, val2;
uint8_t ureg, ureg1;
@ -358,6 +556,11 @@ void process_request(HDSL_Handle hdslHandle,int menu){
DebugP_log("\r\n RSSI: %u", ret_status);
}
break;
#ifndef HDSL_MULTI_CHANNEL
case MENU_HDSL_REG_INTO_MEMORY:
traces_into_memory(hdslHandle);
break;
#endif
case MENU_PC_SHORT_MSG_WRITE:
TC_write_pc_short_msg(hdslHandle);
break;
@ -385,6 +588,7 @@ void process_request(HDSL_Handle hdslHandle,int menu){
break;
}
}
void hdsl_pruss_init(void)
{
PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh0->icssCore);
@ -414,6 +618,7 @@ void hdsl_pruss_init(void)
/* enable cycle counter */
HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE), CTR_EN);
}
void hdsl_pruss_init_300m(void)
{
PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh0->icssCore);
@ -517,10 +722,23 @@ void hdsl_pruss_load_run_fw_300m(HDSL_Handle hdslHandle)
void hdsl_init(void)
{
uint8_t ES;
uint32_t period;
uint8_t ES;
uint32_t period;
#ifndef HDSL_MULTI_CHANNEL
HwiP_Params hwiPrms;
uint32_t intrNum = HDSL_MEMORY_TRACE_R5F_IRQ_NUM;
#endif
hdsl_pruss_init();
#ifndef HDSL_MULTI_CHANNEL
/* Register PRU interrupt */
HwiP_Params_init(&hwiPrms);
hwiPrms.intNum = intrNum;
hwiPrms.callback = (void*)&HDSL_IsrFxn;
HwiP_construct(&gPRUHwiObject, &hwiPrms);
#endif
HDSL_iep_init(gHdslHandleCh0);
ClockP_usleep(5000);
if(CONFIG_HDSL0_MODE==0)
@ -549,10 +767,23 @@ void hdsl_init(void)
}
void hdsl_init_300m(void)
{
uint8_t ES;
uint32_t period;
uint8_t ES;
uint32_t period;
#ifndef HDSL_MULTI_CHANNEL
HwiP_Params hwiPrms;
uint32_t intrNum = HDSL_MEMORY_TRACE_R5F_IRQ_NUM;
#endif
hdsl_pruss_init_300m();
#ifndef HDSL_MULTI_CHANNEL
/* Register PRU interrupt */
HwiP_Params_init(&hwiPrms);
hwiPrms.intNum = intrNum;
hwiPrms.callback = (void*)&HDSL_IsrFxn;
HwiP_construct(&gPRUHwiObject, &hwiPrms);
#endif
HDSL_iep_init(gHdslHandleCh0);
ClockP_usleep(5000);
if(CONFIG_HDSL0_MODE==0)
@ -679,11 +910,19 @@ static void display_menu(void)
DebugP_log("\r\n | %2d : RSSI |", MENU_RSSI);
DebugP_log("\r\n | %2d : Parameter Channel Short Message Write |", MENU_PC_SHORT_MSG_WRITE);
DebugP_log("\r\n | %2d : Parameter Channel Short Message Read |", MENU_PC_SHORT_MSG_READ);
DebugP_log("\r\n | %2d : Access on RID 0h, direct read access with length 8 |", MENU_DIRECT_READ_RID0_LENGTH8);
DebugP_log("\r\n | %2d : Access on RID 81h, direct read access with length 8 |", MENU_DIRECT_READ_RID81_LENGTH8);
DebugP_log("\r\n | %2d : Access on RID 81h, direct read access with length 2 |", MENU_DIRECT_READ_RID81_LENGTH2);
DebugP_log("\r\n | %2d : Access on RID 0h, indirect write, length 8, with offset 0 |", MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0);
DebugP_log("\r\n | %2d : Access on RID 0h; indirect write, length 8, without offset value |", MENU_INDIRECT_WRITE_RID0_LENGTH8);
DebugP_log("\r\n | %2d : Parameter Channel Long Message Read |", MENU_DIRECT_READ_RID0_LENGTH8);
DebugP_log("\r\n | Access on RID 0h, direct read access with length 8 |");
DebugP_log("\r\n | %2d : Parameter Channel Long Message Read |", MENU_DIRECT_READ_RID81_LENGTH8);
DebugP_log("\r\n | Access on RID 81h, direct read access with length 8 |");
DebugP_log("\r\n | %2d : Parameter Channel Long Message Read |", MENU_DIRECT_READ_RID81_LENGTH2);
DebugP_log("\r\n | Access on RID 81h, direct read access with length 2 |");
DebugP_log("\r\n | %2d : Parameter Channel Long Message Write |", MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0);
DebugP_log("\r\n | Access on RID 0h, indirect write, length 8, with offset 0 |");
DebugP_log("\r\n | %2d : Parameter Channel Long Message Write |", MENU_INDIRECT_WRITE_RID0_LENGTH8);
DebugP_log("\r\n | Access on RID 0h; indirect write, length 8, without offset value |");
#ifndef HDSL_MULTI_CHANNEL
DebugP_log("\r\n | %2d : HDSL registers into Memory |", MENU_HDSL_REG_INTO_MEMORY);
#endif
DebugP_log("\r\n |------------------------------------------------------------------------------|\n");
DebugP_log("\r\n Enter value: ");
}
@ -929,114 +1168,34 @@ void indirect_write_rid0_length8(HDSL_Handle hdslHandle)
static int get_menu(void)
{
unsigned int cmd;
uint32_t cmd;
if(DebugP_scanf("%d\n", &cmd) < 0 || cmd >= MENU_LIMIT)
#ifndef HDSL_MULTI_CHANNEL
if(DebugP_scanf("%d\n", &cmd) < 0 || (cmd >= MENU_LIMIT))
#else
if(DebugP_scanf("%d\n", &cmd) < 0 || (cmd >= MENU_LIMIT) || (cmd == MENU_HDSL_REG_INTO_MEMORY))
#endif
{
DebugP_log("\r\n WARNING: invalid option, Safe position selected");
cmd = MENU_SAFE_POSITION;
DebugP_log( "\r\n Enter 0 :Fast Position \r\n Enter 1: Safe Position 1 \r\n Enter 2: Safe Position 2 \r");
if((DebugP_scanf("%d", &get_pos) < 0) || get_pos > 2)
{
DebugP_log("\r\n WARNING: invalid position value");
}
}
if (cmd == MENU_PC_LONG_MSG_WRITE)
#ifndef HDSL_MULTI_CHANNEL
if (cmd == MENU_HDSL_REG_INTO_MEMORY)
{
DebugP_log("\r\n Enter addgRess High (hex value): ");
if(DebugP_scanf("%x\n", &gPc_addrh) < 0 || gPc_addrh > 0x3f)
{
DebugP_log("\r\n WARNING: invalid addgRess High");
return MENU_INVALID;
}
DebugP_log("\r\n Enter addgRess Low (hex value): ");
if(DebugP_scanf("%x\n", &gPc_addrl) < 0 || gPc_addrl > 0x3f)
{
DebugP_log("\r\n WARNING: invalid addgRess Low");
return MENU_INVALID;
}
DebugP_log("\r\n Enter parameter channel offset high (hex value): ");
if(DebugP_scanf("%x\n", &gPc_offh) < 0 || gPc_offh > 0x3f)
{
DebugP_log("\r\n WARNING: invalid parameter channel offset high");
return MENU_INVALID;
}
DebugP_log("\r\n Enter parameter channel offset low (hex value): ");
if(DebugP_scanf("%x\n", &gPc_offl) < 0 || gPc_offl > 0x3f)
{
DebugP_log("\r\n WARNING: invalid parameter channel offset low");
return MENU_INVALID;
}
DebugP_log("\r\n Enter buffer 0 data (hex value): ");
if (DebugP_scanf("%x\n", &gPc_buf0) < 0 || gPc_buf0 > 0xff)
{
DebugP_log("\r\n WARNING: invalid buffer 0 data");
return MENU_INVALID;
}
DebugP_log("\r\n Enter buffer 1 data (hex value): ");
if (DebugP_scanf("%x\n", &gPc_buf1) < 0 || gPc_buf1 > 0xff)
{
DebugP_log("\r\n WARNING: invalid buffer 1 data");
return MENU_INVALID;
}
DebugP_log("\r\n Enter buffer 2 data (hex value): ");
if (DebugP_scanf("%x\n", &gPc_buf2) < 0 || gPc_buf2 > 0xff)
{
DebugP_log("\r\n WARNING: invalid buffer 2 data");
return MENU_INVALID;
}
DebugP_log("\r\n Enter buffer 3 data (hex value): ");
if (DebugP_scanf("%x\n", &gPc_buf3) < 0 || gPc_buf3 > 0xff)
{
DebugP_log("\r\n WARNING: invalid buffer 3 data");
return MENU_INVALID;
}
DebugP_log("\r\n Enter buffer 4 data (hex value): ");
if (DebugP_scanf("%x\n", &gPc_buf4) < 0 || gPc_buf4 > 0xff)
{
DebugP_log("\r\n WARNING: invalid buffer 4 data");
return MENU_INVALID;
}
DebugP_log("\r\n Enter buffer 5 data (hex value): ");
if (DebugP_scanf("%x\n", &gPc_buf5) < 0 || gPc_buf5 > 0xff)
{
DebugP_log("\r\n WARNING: invalid buffer 5 data");
return MENU_INVALID;
}
DebugP_log("\r\n Enter buffer 6 data (hex value): ");
if (DebugP_scanf("%x\n", &gPc_buf6) < 0 || gPc_buf6 > 0xff)
{
DebugP_log("\r\n WARNING: invalid buffer 6 data");
return MENU_INVALID;
}
DebugP_log("\r\n Enter buffer 7 data (hex value): ");
if (DebugP_scanf("%x\n", &gPc_buf7) < 0 || gPc_buf7 > 0xff)
{
DebugP_log("\r\n WARNING: invalid buffer 7 data");
return MENU_INVALID;
}
DebugP_log("\r\n| How many traces you want to copy : ");
if(DebugP_scanf("%u\n", &trace_count) < 0 || trace_count >= NUM_RESOURCES)
{
DebugP_log("\r\n| WARNING: invalid data\n|\n|\n");
return MENU_INVALID;
}
}
#endif
return cmd;
}
#ifdef HDSL_AM64xE1_TRANSCEIVER
static void hdsl_i2c_io_expander(void *args)
{
@ -1083,12 +1242,25 @@ static void hdsl_i2c_io_expander(void *args)
void hdsl_diagnostic_main(void *arg)
{
uint32_t val, acc_bits, pos_bits;
uint8_t ureg;
uint32_t val, acc_bits, pos_bits;
uint8_t ureg;
#ifndef HDSL_MULTI_CHANNEL
int32_t retVal = UDMA_SOK;
#endif
/* Open drivers to open the UART driver for console */
Drivers_open();
Board_driversOpen();
#ifndef HDSL_MULTI_CHANNEL
/* UDMA initialization */
chHandle = gConfigUdma0BlkCopyChHandle[0]; /* Has to be done after driver open */
/* Channel enable */
retVal = Udma_chEnable(chHandle);
DebugP_assert(UDMA_SOK == retVal);
#endif
/*C16 pin High for Enabling ch0 in booster pack */
#if (CONFIG_HDSL0_BOOSTER_PACK)
GPIO_setDirMode(ENC1_EN_BASE_ADDR, ENC1_EN_PIN, ENC1_EN_DIR);
@ -1126,112 +1298,110 @@ void hdsl_diagnostic_main(void *arg)
/*need some extra time for SYNC mode since frames are longer*/
#if (CONFIG_HDSL0_CHANNEL0==1)
//Channel 0 starts here:
ClockP_usleep(1000);
for (ureg = HDSL_get_master_qm(gHdslHandleCh0), val = 0; !(ureg & 0x80); ureg = HDSL_get_master_qm(gHdslHandleCh0), val++, ClockP_usleep(10))
{
if (val > 100)
{ /* wait 1ms to detect, increase if reqd. */
DebugP_log( "\r\nHiperface DSL encoder not detected on gHdslHandleCh0 \n\n");
ClockP_usleep(5000);
}
}
while(1)
{
ureg = HDSL_get_master_qm(gHdslHandleCh0);
DebugP_log( "\r\n");
DebugP_log( "\r|------------------------------------------------------------------------------|\n");
DebugP_log( "\r| Hiperface DSL diagnostic |\n");
DebugP_log( "\r|------------------------------------------------------------------------------|\n");
DebugP_log( "\r|========Channel 0: |\n");
DebugP_log( "\r|\n");
DebugP_log( "\r| Quality monitoring value: %u\n", ureg & 0xF);
if((ureg & 0x80) != 0)
break;
ureg = HDSL_get_edges(gHdslHandleCh0);
DebugP_log( "\r| Edges: 0x%x\n", ureg);
DebugP_log( "\r\n Hiperface DSL encoder not detected\n");
ClockP_usleep(10000);
}
ureg = HDSL_get_delay(gHdslHandleCh0);
DebugP_log("\r\n | Cable delay: %u |", ureg & 0xF);
DebugP_log("\r\n | RSSI: %u |", (ureg & 0xF0) >> 4);
val =HDSL_get_enc_id(gHdslHandleCh0, 0) | (HDSL_get_enc_id(gHdslHandleCh0, 1) << 8) |
(HDSL_get_enc_id(gHdslHandleCh0, 2) << 16);
acc_bits = val & 0xF;
acc_bits += 8;
pos_bits = (val & 0x3F0) >> 4;
pos_bits += acc_bits;
DebugP_log("\r\n | Encoder ID: 0x%x", val);
DebugP_log( "(");
DebugP_log( "Acceleration bits: %u ,", acc_bits);
DebugP_log( "Position bits: %u,", pos_bits);
DebugP_log( "%s", val & 0x400 ? " Bipolar position" : " Unipolar position");
DebugP_log(")|");
DebugP_log("\r\n |-------------------------------------------------------------------------------|");
DebugP_log("\r\n Enter single turn bits: ");
if((DebugP_scanf("%d\n", &gHdslHandleCh0->res) < 0) || gHdslHandleCh0->res > pos_bits)
{
DebugP_log( "\r| WARNING: invalid single turn bits, assuming single turn encoder\n");
gHdslHandleCh0->res = pos_bits;
}
gHdslHandleCh0->multi_turn = pos_bits - gHdslHandleCh0->res;
gHdslHandleCh0->mask = pow(2, gHdslHandleCh0->res) - 1;
if (gHdslHandleCh0->multi_turn)
{
DebugP_log( "\r| Multi turn bits: %u\n", gHdslHandleCh0->multi_turn);
}
DebugP_log( "\r\n");
DebugP_log( "\r |-------------------------------------------------------------------------------|\n");
DebugP_log( "\r | Hiperface DSL Diagnostic : Channel 0 |\n");
DebugP_log( "\r |-------------------------------------------------------------------------------|\n");
DebugP_log( "\r | |\n");
DebugP_log( "\r | Quality monitoring value: %u |\n", ureg & 0xF);
ureg = HDSL_get_edges(gHdslHandleCh0);
DebugP_log( "\r | Edges: 0x%x |", ureg);
ureg = HDSL_get_delay(gHdslHandleCh0);
DebugP_log("\r\n | Cable delay: %u |", ureg & 0xF);
DebugP_log("\r\n | RSSI: %u |", (ureg & 0xF0) >> 4);
val =HDSL_get_enc_id(gHdslHandleCh0, 0) | (HDSL_get_enc_id(gHdslHandleCh0, 1) << 8) |
(HDSL_get_enc_id(gHdslHandleCh0, 2) << 16);
acc_bits = val & 0xF;
acc_bits += 8;
pos_bits = (val & 0x3F0) >> 4;
pos_bits += acc_bits;
DebugP_log("\r\n | Encoder ID: 0x%x", val);
DebugP_log( "(");
DebugP_log( "Acceleration bits: %u ,", acc_bits);
DebugP_log( "Position bits: %u,", pos_bits);
DebugP_log( "%s", val & 0x400 ? " Bipolar position" : " Unipolar position");
DebugP_log(")|");
DebugP_log("\r\n |-------------------------------------------------------------------------------|");
DebugP_log("\r\n Enter single turn bits: ");
if((DebugP_scanf("%d\n", &gHdslHandleCh0->res) < 0) || gHdslHandleCh0->res > pos_bits)
{
DebugP_log( "\r| WARNING: invalid single turn bits, assuming single turn encoder\n");
gHdslHandleCh0->res = pos_bits;
}
gHdslHandleCh0->multi_turn = pos_bits - gHdslHandleCh0->res;
gHdslHandleCh0->mask = pow(2, gHdslHandleCh0->res) - 1;
if (gHdslHandleCh0->multi_turn)
{
DebugP_log( "\r\n Multi turn bits: %u\n", gHdslHandleCh0->multi_turn);
}
#endif
#if (CONFIG_HDSL0_CHANNEL1==1)
//Channel 1 starts here:
ClockP_usleep(1000);
for (ureg = HDSL_get_master_qm(gHdslHandleCh1), val = 0; !(ureg & 0x80); ureg = HDSL_get_master_qm(gHdslHandleCh1), val++, ClockP_usleep(10))
{
if (val > 100)
{ /* wait 1ms to detect, increase if reqd. */
DebugP_log( "\r\nHiperface DSL encoder not detected on gHdslHandleCh1 \n\n");
ClockP_usleep(5000);
}
}
DebugP_log( "\r\n");
DebugP_log( "\r|------------------------------------------------------------------------------|\n");
DebugP_log( "\r| Hiperface DSL diagnostic |\n");
DebugP_log( "\r|------------------------------------------------------------------------------|\n");
DebugP_log( "\r|========Channel 1: |\n");
DebugP_log( "\r|\n");
DebugP_log( "\r| Quality monitoring value: %u\n", ureg & 0xF);
ureg = HDSL_get_edges(gHdslHandleCh1);
DebugP_log( "\r| Edges: 0x%x\n", ureg);
ureg = HDSL_get_delay(gHdslHandleCh1);
DebugP_log("\r\n | Cable delay: %u |", ureg & 0xF);
DebugP_log("\r\n | RSSI: %u |", (ureg & 0xF0) >> 4);
val =HDSL_get_enc_id(gHdslHandleCh1, 0) | (HDSL_get_enc_id(gHdslHandleCh1, 1) << 8) |
(HDSL_get_enc_id(gHdslHandleCh1, 2) << 16);
acc_bits = val & 0xF;
acc_bits += 8;
pos_bits = (val & 0x3F0) >> 4;
pos_bits += acc_bits;
DebugP_log("\r\n | Encoder ID: 0x%x", val);
DebugP_log( "(");
DebugP_log( "Acceleration bits: %u ,", acc_bits);
DebugP_log( "Position bits: %u,", pos_bits);
DebugP_log( "%s", val & 0x400 ? " Bipolar position" : " Unipolar position");
DebugP_log(")|");
DebugP_log("\r\n |-------------------------------------------------------------------------------|");
DebugP_log("\r\n Enter single turn bits: ");
if((DebugP_scanf("%d\n", &gHdslHandleCh1->res) < 0) || gHdslHandleCh1->res > pos_bits)
{
DebugP_log( "\r| WARNING: invalid single turn bits, assuming single turn encoder\n");
gHdslHandleCh1->res = pos_bits;
}
gHdslHandleCh1->multi_turn = pos_bits - gHdslHandleCh1->res;
gHdslHandleCh1->mask = pow(2, gHdslHandleCh1->res) - 1;
if (gHdslHandleCh1->multi_turn)
{
DebugP_log( "\r| Multi turn bits: %u\n", gHdslHandleCh1->multi_turn);
}
#endif
//Channel 1 starts here:
while(1)
{
int menu;
ureg = HDSL_get_master_qm(gHdslHandleCh1);
if((ureg & 0x80) != 0)
break;
DebugP_log( "\r\n Hiperface DSL encoder not detected\n");
ClockP_usleep(10000);
}
DebugP_log( "\r\n");
DebugP_log( "\r |-------------------------------------------------------------------------------|\n");
DebugP_log( "\r | Hiperface DSL Diagnostic : Channel 1 |\n");
DebugP_log( "\r |-------------------------------------------------------------------------------|\n");
DebugP_log( "\r | |\n");
DebugP_log( "\r | Quality monitoring value: %u |\n", ureg & 0xF);
ureg = HDSL_get_edges(gHdslHandleCh1);
DebugP_log( "\r | Edges: 0x%x |", ureg);
ureg = HDSL_get_delay(gHdslHandleCh1);
DebugP_log("\r\n | Cable delay: %u |", ureg & 0xF);
DebugP_log("\r\n | RSSI: %u |", (ureg & 0xF0) >> 4);
val =HDSL_get_enc_id(gHdslHandleCh1, 0) | (HDSL_get_enc_id(gHdslHandleCh1, 1) << 8) |
(HDSL_get_enc_id(gHdslHandleCh1, 2) << 16);
acc_bits = val & 0xF;
acc_bits += 8;
pos_bits = (val & 0x3F0) >> 4;
pos_bits += acc_bits;
DebugP_log("\r\n | Encoder ID: 0x%x", val);
DebugP_log( "(");
DebugP_log( "Acceleration bits: %u ,", acc_bits);
DebugP_log( "Position bits: %u,", pos_bits);
DebugP_log( "%s", val & 0x400 ? " Bipolar position" : " Unipolar position");
DebugP_log(")|");
DebugP_log("\r\n |-------------------------------------------------------------------------------|");
DebugP_log("\r\n Enter single turn bits: ");
if((DebugP_scanf("%d\n", &gHdslHandleCh1->res) < 0) || gHdslHandleCh1->res > pos_bits)
{
DebugP_log( "\r| WARNING: invalid single turn bits, assuming single turn encoder\n");
gHdslHandleCh1->res = pos_bits;
}
gHdslHandleCh1->multi_turn = pos_bits - gHdslHandleCh1->res;
gHdslHandleCh1->mask = pow(2, gHdslHandleCh1->res) - 1;
if (gHdslHandleCh1->multi_turn)
{
DebugP_log( "\r\n Multi turn bits: %u\n", gHdslHandleCh1->multi_turn);
}
#endif
while(1)
{
int32_t menu;
display_menu();
menu = get_menu();
if (CONFIG_HDSL0_CHANNEL0==1)

16
examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.h
View File

@ -61,19 +61,21 @@ static void HDSL_IsrFxn(void);
void TC_read_pc_short_msg();
void TC_write_pc_short_msg();
//void _copy_reg_into_ddr();
#ifndef HDSL_MULTI_CHANNEL
/*
* @brief It will test copy of traces into memory
* \n Here user will decide how many copies of HDSL_Interface_Register
* \n will be copied into memory
*/
void traces_into_memory();
#endif
void direct_read_rid0_length8();
void direct_read_rid81_length8();
void direct_read_rid81_length2();
void indirect_write_rid0_length8();
void indirect_write_rid0_length8_offset0();
/**
* @name HDSL_sync_calculation
* @brief Measurement of syn period
*/
int HDSL_sync_calculation(void);
#ifdef __cplusplus
}
#endif

2
examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -105,8 +105,6 @@ SECTIONS
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
.hdslInterface_ddr_mem (NOLOAD) > DDR
}
/*

2
examples/position_sense/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -105,8 +105,6 @@ SECTIONS
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
.hdslInterface_ddr_mem (NOLOAD) > DDR
}
/*

11
examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/example.syscfg
View File

@ -1,8 +1,8 @@
/**
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
* @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01"
* @versions {"tool":"1.14.0+2667"}
* @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK@09.00.00"
* @versions {"tool":"1.17.0+3128"}
*/
/**
@ -14,6 +14,8 @@ const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false);
const i2c1 = i2c.addInstance();
const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
const pruicss1 = pruicss.addInstance();
const udma = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1 = udma.addInstance();
const debug_log = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71 = mpu_armv7.addInstance();
@ -40,6 +42,11 @@ pruicss1.$name = "CONFIG_PRU_ICSS1";
pruicss1.instance = "ICSSG1";
pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
udma1.$name = "CONFIG_UDMA0";
udma1.udmaBlkCopyChannel.create(1);
udma1.udmaBlkCopyChannel[0].$name = "CONFIG_UDMA_BLKCOPY_CH0";
udma1.udmaBlkCopyChannel[0].transferCallbackFxn = "App_udmaEventCb";
debug_log.enableUartLog = true;
debug_log.enableCssLog = false;
debug_log.uartLog.$name = "CONFIG_UART0";

2
examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -106,7 +106,7 @@ SECTIONS
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
.hdslInterface_ddr_mem (NOLOAD) > DDR
.hdslInterface_mem (NOLOAD) > DDR
}
/*

32
examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/example.syscfg
View File

@ -1,8 +1,8 @@
/**
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
* @cliArgs --device "AM243x_ALX_beta" --package "ALX" --part "ALX" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01"
* @versions {"tool":"1.14.0+2667"}
* @cliArgs --device "AM243x_ALX_beta" --package "ALX" --part "ALX" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK@09.00.00"
* @versions {"tool":"1.17.0+3128"}
*/
/**
@ -15,6 +15,8 @@ const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false);
const i2c1 = i2c.addInstance();
const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
const pruicss1 = pruicss.addInstance();
const udma = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1 = udma.addInstance();
const debug_log = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71 = mpu_armv7.addInstance();
@ -31,7 +33,7 @@ const hdsl1 = hdsl.addInstance();
gpio1.$name = "CONFIG_GPIO0";
gpio1.pinDir = "OUTPUT";
gpio1.GPIO.gpioPin.rx = false;
gpio1.GPIO.gpioPin.$assign = "ball.R20";
gpio1.GPIO.gpioPin.$assign = "GPMC0_AD1";
i2c1.$name = "CONFIG_I2C0";
i2c1.I2C.$assign = "I2C1";
@ -40,6 +42,11 @@ pruicss1.$name = "CONFIG_PRU_ICSS1";
pruicss1.instance = "ICSSG1";
pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO1";
udma1.$name = "CONFIG_UDMA0";
udma1.udmaBlkCopyChannel.create(1);
udma1.udmaBlkCopyChannel[0].$name = "CONFIG_UDMA_BLKCOPY_CH0";
udma1.udmaBlkCopyChannel[0].transferCallbackFxn = "App_udmaEventCb";
debug_log.enableUartLog = true;
debug_log.enableCssLog = false;
debug_log.uartLog.$name = "CONFIG_UART_CONSOLE";
@ -72,6 +79,7 @@ mpu_armv75.accessPermissions = "Supervisor RD, User RD";
hdsl1.$name = "CONFIG_HDSL0";
hdsl1.Booster_Pack = true;
hdsl1.coreClk = 300000000;
hdsl1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1";
hdsl1.PRU_ICSSG0_PRU.GPO5.$used = false;
hdsl1.PRU_ICSSG0_PRU.GPO4.$used = false;
@ -86,7 +94,7 @@ hdsl1.ENC1_EN = gpio2;
gpio2.$name = "ENC1_EN";
gpio2.GPIO.$assign = "GPIO1";
gpio2.GPIO.gpioPin.rx = false;
gpio2.GPIO.gpioPin.$assign = "ball.C16";
gpio2.GPIO.gpioPin.$assign = "MMC1_SDWP";
const pruicss2 = pruicss.addInstance({}, false);
pruicss2.$name = "CONFIG_PRU_ICSS0";
@ -99,11 +107,11 @@ pruicss2.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
* re-solve from scratch.
*/
gpio1.GPIO.$suggestSolution = "GPIO0";
i2c1.I2C.SCL.$suggestSolution = "ball.A17";
i2c1.I2C.SDA.$suggestSolution = "ball.B18";
debug_log.uartLog.UART.RXD.$suggestSolution = "ball.B10";
debug_log.uartLog.UART.TXD.$suggestSolution = "ball.B11";
hdsl1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "ball.M2";
hdsl1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "ball.J2";
hdsl1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "ball.L5";
hdsl1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "ball.T4";
i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL";
i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA";
debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD";
debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD";
hdsl1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2";
hdsl1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1";
hdsl1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0";
hdsl1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13";

2
examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -106,7 +106,7 @@ SECTIONS
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
.hdslInterface_ddr_mem (NOLOAD) > DDR
.hdslInterface_mem (NOLOAD) > DDR
}
/*

11
examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/example.syscfg
View File

@ -1,8 +1,8 @@
/**
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
* @cliArgs --device "AM64x_beta" --package "ALV" --part "Default" --context "r5fss0-0" --product "MCU_PLUS_SDK@07.03.01"
* @versions {"tool":"1.14.0+2667"}
* @cliArgs --device "AM64x" --package "ALV" --part "Default" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK@09.00.00"
* @versions {"tool":"1.17.0+3128"}
*/
/**
@ -14,6 +14,8 @@ const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false);
const i2c1 = i2c.addInstance();
const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
const pruicss1 = pruicss.addInstance();
const udma = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1 = udma.addInstance();
const debug_log = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71 = mpu_armv7.addInstance();
@ -40,6 +42,11 @@ pruicss1.$name = "CONFIG_PRU_ICSS1";
pruicss1.instance = "ICSSG1";
pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
udma1.$name = "CONFIG_UDMA0";
udma1.udmaBlkCopyChannel.create(1);
udma1.udmaBlkCopyChannel[0].$name = "CONFIG_UDMA_BLKCOPY_CH0";
udma1.udmaBlkCopyChannel[0].transferCallbackFxn = "App_udmaEventCb";
debug_log.enableUartLog = true;
debug_log.enableCssLog = false;
debug_log.uartLog.$name = "CONFIG_UART0";

2
examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd
View File

@ -106,7 +106,7 @@ SECTIONS
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
.hdslInterface_ddr_mem (NOLOAD) > DDR
.hdslInterface_mem (NOLOAD) > DDR
}
/*

14
examples/position_sense/hdsl_diagnostic_with_traces/.project/project.js
View File

@ -1,14 +0,0 @@
function getComponentProperty(device)
{
return require(`./project_${device}`).getComponentProperty();
};
function getComponentBuildProperty(buildOption)
{
return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption);
};
module.exports = {
getComponentProperty,
getComponentBuildProperty,
};

120
examples/position_sense/hdsl_diagnostic_with_traces/.project/project_am243x.js
View File

@ -1,120 +0,0 @@
let path = require('path');
let device = "am243x";
const files = {
common: [
"hdsl_diagnostic_ddr.c",
"main.c",
],
};
/* Relative to where the makefile will be generated
* Typically at <example_folder>/<BOARD>/<core_os_combo>/<compiler>
*/
const filedirs = {
common: [
"..", /* core_os_combo base */
"../../..", /* Example base */
],
};
const libdirs_freertos = {
common: [
"${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib",
"${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib",
"${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib",
"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/lib",
],
};
const includes_freertos_r5f = {
common: [
"${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include",
"${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F",
"${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f",
],
};
const libs_freertos_r5f = {
common: [
"freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
"drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
"board.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
"motorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib",
],
};
const lnkfiles = {
common: [
"linker.cmd",
]
};
const projectspec_files = {
common: [
"../../../hdsl_diagnostic_ddr.h",
]
}
const syscfgfile = "../example.syscfg";
const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_HDSL";
const templates_freertos_r5f =
[
{
input: ".project/templates/am243x/freertos/main_freertos.c.xdt",
output: "../main.c",
options: {
entryFunction: "hdsl_diagnostic_main",
},
}
];
const buildOptionCombos = [
{ device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-evm", os: "freertos"},
];
function getComponentProperty() {
let property = {};
property.dirPath = path.resolve(__dirname, "..");
property.type = "executable";
property.name = "hdsl_diagnostic_ddr";
property.isInternal = false;
property.buildOptionCombos = buildOptionCombos;
property.isSkipTopLevelBuild = false;
return property;
}
function getComponentBuildProperty(buildOption) {
let build_property = {};
build_property.files = files;
build_property.filedirs = filedirs;
build_property.lnkfiles = lnkfiles;
build_property.syscfgfile = syscfgfile;
build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
build_property.projectspec_files = projectspec_files;
if(buildOption.cpu.match(/r5f*/)) {
if(buildOption.os.match(/freertos*/) )
{
build_property.includes = includes_freertos_r5f;
build_property.libdirs = libdirs_freertos;
build_property.libs = libs_freertos_r5f;
build_property.templates = templates_freertos_r5f;
}
}
return build_property;
}
module.exports = {
getComponentProperty,
getComponentBuildProperty,
};

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@ -1,118 +0,0 @@
let path = require('path');
let device = "am64x";
const files = {
common: [
"hdsl_diagnostic_ddr.c",
"main.c",
],
};
/* Relative to where the makefile will be generated
* Typically at <example_folder>/<BOARD>/<core_os_combo>/<compiler>
*/
const filedirs = {
common: [
"..", /* core_os_combo base */
"../../..", /* Example base */
],
};
const libdirs_freertos = {
common: [
"${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib",
"${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib",
"${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib",
"${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/lib",
],
};
const includes_freertos_r5f = {
common: [
"${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include",
"${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F",
"${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am64x/r5f",
],
};
const libs_freertos_r5f = {
common: [
"freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
"drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
"board.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
"motorcontrol_hdsl.am64x.r5f.ti-arm-clang.${ConfigName}.lib",
],
};
const lnkfiles = {
common: [
"linker.cmd",
]
};
const projectspec_files = {
common: [
"../../../hdsl_diagnostic_ddr.h",
]
}
const syscfgfile = "../example.syscfg";
const readmeDoxygenPageTag = "EXAMPLE_MOTORCONTROL_HDSL";
const templates_freertos_r5f =
[
{
input: ".project/templates/am64x/freertos/main_freertos.c.xdt",
output: "../main.c",
options: {
entryFunction: "hdsl_diagnostic_main",
},
}
];
const buildOptionCombos = [
{ device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am64x-evm", os: "freertos"},
];
function getComponentProperty() {
let property = {};
property.dirPath = path.resolve(__dirname, "..");
property.type = "executable";
property.name = "hdsl_diagnostic_ddr";
property.isInternal = false;
property.buildOptionCombos = buildOptionCombos;
property.isSkipTopLevelBuild = false;
return property;
}
function getComponentBuildProperty(buildOption) {
let build_property = {};
build_property.files = files;
build_property.filedirs = filedirs;
build_property.lnkfiles = lnkfiles;
build_property.syscfgfile = syscfgfile;
build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
build_property.projectspec_files = projectspec_files;
if(buildOption.cpu.match(/r5f*/)) {
if(buildOption.os.match(/freertos*/) )
{
build_property.includes = includes_freertos_r5f;
build_property.libdirs = libdirs_freertos;
build_property.libs = libs_freertos_r5f;
build_property.templates = templates_freertos_r5f;
}
}
return build_property;
}
module.exports = {
getComponentProperty,
getComponentBuildProperty,
};

126
examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/example.syscfg
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@ -1,126 +0,0 @@
/**
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
* @cliArgs --device "AM243x_ALV_beta" --package "ALV" --part "ALV" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK@09.00.00"
* @versions {"tool":"1.17.0+3128"}
*/
/**
* Import the modules used in this configuration.
*/
const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false);
const gpio1 = gpio.addInstance();
const gpio2 = gpio.addInstance();
const gpio3 = gpio.addInstance();
const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false);
const i2c1 = i2c.addInstance();
const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
const pruicss1 = pruicss.addInstance();
const udma = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1 = udma.addInstance();
const debug_log = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71 = mpu_armv7.addInstance();
const mpu_armv72 = mpu_armv7.addInstance();
const mpu_armv73 = mpu_armv7.addInstance();
const mpu_armv74 = mpu_armv7.addInstance();
const mpu_armv75 = mpu_armv7.addInstance();
const mpu_armv76 = mpu_armv7.addInstance();
const hdsl = scripting.addModule("/position_sense/hdsl", {}, false);
const hdsl1 = hdsl.addInstance();
/**
* Write custom configuration values to the imported modules.
*/
gpio1.$name = "CONFIG_GPIO0";
gpio1.pinDir = "OUTPUT";
gpio1.GPIO.gpioPin.rx = false;
gpio1.GPIO.gpioPin.$assign = "GPMC0_CSn1";
gpio2.$name = "CONFIG_GPIO_COPY";
gpio2.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO17";
gpio3.$name = "CONFIG_GPIO_TEST_COPY";
gpio3.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO18";
i2c1.$name = "CONFIG_I2C0";
i2c1.I2C.$assign = "I2C1";
pruicss1.$name = "CONFIG_PRU_ICSS1";
pruicss1.instance = "ICSSG1";
pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
udma1.$name = "CONFIG_UDMA0";
udma1.udmaBlkCopyChannel.create(1);
udma1.udmaBlkCopyChannel[0].$name = "CONFIG_UDMA_BLKCOPY_CH0";
udma1.udmaBlkCopyChannel[0].intrEnable = true;
udma1.udmaBlkCopyChannel[0].transferCallbackFxn = "App_udmaEventCb";
debug_log.enableUartLog = true;
debug_log.enableCssLog = false;
debug_log.uartLog.$name = "CONFIG_UART0";
debug_log.uartLog.UART.$assign = "USART0";
mpu_armv71.$name = "CONFIG_MPU_REGION0";
mpu_armv71.size = 31;
mpu_armv71.attributes = "Device";
mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute = false;
mpu_armv72.$name = "CONFIG_MPU_REGION1";
mpu_armv72.size = 15;
mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv73.$name = "CONFIG_MPU_REGION2";
mpu_armv73.baseAddr = 0x41010000;
mpu_armv73.size = 15;
mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv74.$name = "CONFIG_MPU_REGION3";
mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv74.baseAddr = 0x70000000;
mpu_armv74.size = 21;
mpu_armv75.$name = "CONFIG_MPU_REGION4";
mpu_armv75.baseAddr = 0x60000000;
mpu_armv75.size = 28;
mpu_armv75.accessPermissions = "Supervisor RD, User RD";
mpu_armv76.$name = "CONFIG_MPU_REGION5";
mpu_armv76.baseAddr = 0x80000000;
mpu_armv76.size = 31;
hdsl1.$name = "CONFIG_HDSL0";
hdsl1.coreClk = 300000000;
hdsl1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1";
const pruicss2 = pruicss.addInstance({}, false);
pruicss2.$name = "CONFIG_PRU_ICSS0";
pruicss2.instance = scripting.forceWrite("ICSSG0");
hdsl1.pru = pruicss2;
pruicss2.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO2";
/**
* Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
* version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to
* re-solve from scratch.
*/
gpio1.GPIO.$suggestSolution = "GPIO0";
gpio2.GPIO.$suggestSolution = "GPIO0";
gpio3.GPIO.$suggestSolution = "GPIO0";
i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL";
i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA";
debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD";
debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD";
hdsl1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2";
hdsl1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1";
hdsl1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0";
hdsl1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13";
hdsl1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5";
hdsl1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4";
hdsl1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3";
hdsl1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14";
hdsl1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8";
hdsl1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12";
hdsl1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6";
hdsl1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11";

84
examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/main.c
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@ -1,84 +0,0 @@
/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include <kernel/dpl/DebugP.h>
#include "ti_drivers_config.h"
#include "ti_board_config.h"
#include "FreeRTOS.h"
#include "task.h"
#define MAIN_TASK_PRI (configMAX_PRIORITIES-1)
#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE))
StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
StaticTask_t gMainTaskObj;
TaskHandle_t gMainTask;
void hdsl_diagnostic_main(void *args);
void freertos_main(void *args)
{
hdsl_diagnostic_main(NULL);
vTaskDelete(NULL);
}
int main(void)
{
/* init SOC specific modules */
System_init();
Board_init();
/* This task is created at highest priority, it should create more tasks and then delete itself */
gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */
"freertos_main", /* Text name for the task. This is to facilitate debugging only. */
MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
NULL, /* We are not using the task parameter. */
MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
gMainTaskStack, /* pointer to stack base */
&gMainTaskObj ); /* pointer to statically allocated task object memory */
configASSERT(gMainTask != NULL);
/* Start the scheduler to start the tasks executing. */
vTaskStartScheduler();
/* The following line should never be reached because vTaskStartScheduler()
will only return if there was not enough FreeRTOS heap memory available to
create the Idle and (if configured) Timer tasks. Heap management, and
techniques for trapping heap exhaustion, are described in the book text. */
DebugP_assertNoLog(0);
return 0;
}

115
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@ -1,115 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectSpec>
<applicability>
<when>
<context
deviceFamily="ARM"
deviceId="Cortex R.AM2434_ALV"
/>
</when>
</applicability>
<project
title="Hdsl Diagnostic Ddr"
name = "hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang"
products="sysconfig;com.ti.MOTOR_CONTROL_SDK_AMXXX;"
configurations="
Debug,
Release,
"
connection="TIXDS110_Connection.xml"
toolChain="TICLANG"
cgtVersion="2.1.3"
device="Cortex R.AM2434_ALV"
deviceCore="MAIN_PULSAR_Cortex_R5_0_0"
ignoreDefaultDeviceSettings="true"
ignoreDefaultCCSSettings="true"
endianness="little"
outputFormat="ELF"
outputType="executable"
compilerBuildOptions="
-I${CG_TOOL_ROOT}/include/c
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source
-I${MOTOR_CONTROL_SDK_PATH}/source
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f
-mcpu=cortex-r5
-mfloat-abi=hard
-mfpu=vfpv3-d16
-mthumb
-Wall
-Werror
-g
-Wno-gnu-variable-sized-type-not-at-end
-Wno-unused-function
-DSOC_AM243X
"
linkerBuildOptions="
-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib
-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib
-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib
-i${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/lib
-i${CG_TOOL_ROOT}/lib
-m=hdsl_diagnostic_ddr.${ConfigName}.map
--diag_suppress=10063
--ram_model
--reread_libs
"
postBuildStep="$(MAKE) -C ${CCS_PROJECT_DIR} -f makefile_ccs_bootimage_gen OUTNAME=${BuildArtifactFileBaseName} PROFILE=${ConfigName} MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} CG_TOOL_ROOT=${CG_TOOL_ROOT} CCS_INSTALL_DIR=${CCS_INSTALL_DIR} CCS_IDE_MODE=${CCS_IDE_MODE} DEVICE=am243x"
enableSysConfigTool="true"
sysConfigBuildOptions="
--context r5fss0-0 --part ALV --package ALV
"
description="A Hdsl Diagnostic Ddr FREERTOS project">
<configuration name="Debug"
compilerBuildOptions="
-D_DEBUG_=1
"
linkerBuildOptions="
-lfreertos.am243x.r5f.ti-arm-clang.debug.lib
-ldrivers.am243x.r5f.ti-arm-clang.debug.lib
-lboard.am243x.r5f.ti-arm-clang.debug.lib
-lmotorcontrol_hdsl.am243x.r5f.ti-arm-clang.debug.lib
-llibc.a
-llibsysbm.a
"
></configuration>
<configuration name="Release"
compilerBuildOptions="
-Os
"
linkerBuildOptions="
-lfreertos.am243x.r5f.ti-arm-clang.release.lib
-ldrivers.am243x.r5f.ti-arm-clang.release.lib
-lboard.am243x.r5f.ti-arm-clang.release.lib
-lmotorcontrol_hdsl.am243x.r5f.ti-arm-clang.release.lib
-llibc.a
-llibsysbm.a
"
></configuration>
<pathVariable name="MOTOR_CONTROL_SDK_PATH" path="${COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR}" scope="project" />
<file path="../../../hdsl_diagnostic_ddr.c" openOnCreation="false" excludeFromBuild="false" action="copy">
</file>
<file path="../main.c" openOnCreation="false" excludeFromBuild="false" action="copy">
</file>
<file path="linker.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
</file>
<file path="../example.syscfg" openOnCreation="false" excludeFromBuild="false" action="copy">
</file>
<file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am243x/EXAMPLE_MOTORCONTROL_HDSL.html"
openOnCreation="false" excludeFromBuild="false" targetName="README.html" action="link">
</file>
<file path="../../../hdsl_diagnostic_ddr.h" openOnCreation="false" excludeFromBuild="true" action="copy">
</file>
<file path="syscfg_c.rov.xs" openOnCreation="false" excludeFromBuild="false" action="copy">
</file>
<file path="makefile_ccs_bootimage_gen" openOnCreation="false" excludeFromBuild="false" action="copy">
</file>
</project>
</projectSpec>

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@ -1,153 +0,0 @@
/* This is the stack that is used by code running within main()
* In case of NORTOS,
* - This means all the code outside of ISR uses this stack
* In case of FreeRTOS
* - This means all the code until vTaskStartScheduler() is called in main()
* uses this stack.
* - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
*/
--stack_size=16384
/* This is the heap size for malloc() API in NORTOS and FreeRTOS
* This is also the heap used by pvPortMalloc in FreeRTOS
*/
--heap_size=32768
-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
/* This is the size of stack when R5 is in IRQ mode
* In NORTOS,
* - Here interrupt nesting is enabled
* - This is the stack used by ISRs registered as type IRQ
* In FreeRTOS,
* - Here interrupt nesting is disabled
* - This is stack that is used initally when a IRQ is received
* - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
* - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
*/
__IRQ_STACK_SIZE = 256;
/* This is the size of stack when R5 is in IRQ mode
* - In both NORTOS and FreeRTOS nesting is disabled for FIQ
*/
__FIQ_STACK_SIZE = 256;
__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */
__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */
/* section identifier
*/
SECTIONS
{
/* This has the R5F entry point and vector table, this MUST be at 0x0 */
.vectors:{} palign(8) > R5F_VECS
/* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
* i.e this cannot be placed in DDR
*/
GROUP {
.text.hwi: palign(8)
.text.cache: palign(8)
.text.mpu: palign(8)
.text.boot: palign(8)
.text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
} > MSRAM
/* This is rest of code. This can be placed in DDR if DDR is available and needed */
GROUP {
.text: {} palign(8) /* This is where code resides */
.rodata: {} palign(8) /* This is where const's go */
} > MSRAM
/* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
GROUP {
.data: {} palign(8) /* This is where initialized globals and static go */
} > MSRAM
/* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
GROUP {
.bss: {} palign(8) /* This is where uninitialized globals go */
RUN_START(__BSS_START)
RUN_END(__BSS_END)
.sysmem: {} palign(8) /* This is where the malloc heap goes */
.stack: {} palign(8) /* This is where the main() stack goes */
} > MSRAM
/* This is where the stacks for different R5F modes go */
GROUP {
.irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
RUN_START(__IRQ_STACK_START)
RUN_END(__IRQ_STACK_END)
.fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
RUN_START(__FIQ_STACK_START)
RUN_END(__FIQ_STACK_END)
.svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
RUN_START(__SVC_STACK_START)
RUN_END(__SVC_STACK_END)
.abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
RUN_START(__ABORT_STACK_START)
RUN_END(__ABORT_STACK_END)
.undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
RUN_START(__UNDEFINED_STACK_START)
RUN_END(__UNDEFINED_STACK_END)
} > MSRAM
/* Sections needed for C++ projects */
GROUP {
.ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
.init_array: {} palign(8) /* Contains function pointers called before main */
.fini_array: {} palign(8) /* Contains function pointers called after main */
} > MSRAM
/* General purpose user shared memory, used in some examples */
.bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
/* this is used when Debug log's to shared memory are enabled, else this is not used */
.bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
/* this is used only when IPC RPMessage is enabled, else this is not used */
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
.hdslInterface_ddr_mem (NOLOAD) > DDR
}
/*
NOTE: Below memory is reserved for DMSC usage
- During Boot till security handoff is complete
0x701E0000 - 0x701FFFFF (128KB)
- After "Security Handoff" is complete (i.e at run time)
0x701F4000 - 0x701FFFFF (48KB)
Security handoff is complete when this message is sent to the DMSC,
TISCI_MSG_SEC_HANDOVER
This should be sent once all cores are loaded and all application
specific firewall calls are setup.
*/
MEMORY
{
R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
/* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
/* when using multi-core application's i.e more than one R5F/M4F active, make sure
* this memory does not overlap with other R5F's
*/
MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x60000
/* DDR segment of memory */
DDR : ORIGIN = 0x80000000 , LENGTH = 0x3FFFFFFF
/* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
* other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
*/
FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000
/* shared memory segments */
/* On R5F,
* - make sure there is a MPU entry which maps below regions as non-cache
*/
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80
LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
}

307
examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile
View File

@ -1,307 +0,0 @@
#
# Auto generated makefile
#
export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..)
include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak
CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
CC=$(CG_TOOL_ROOT)/bin/tiarmclang
LNK=$(CG_TOOL_ROOT)/bin/tiarmclang
STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
ifeq ($(OS), Windows_NT)
PYTHON=python
else
PYTHON=python3
endif
PROFILE?=release
ConfigName:=$(PROFILE)
OUTNAME:=hdsl_diagnostic_ddr.$(PROFILE).out
BOOTIMAGE_PATH=$(abspath .)
BOOTIMAGE_NAME:=hdsl_diagnostic_ddr.$(PROFILE).appimage
BOOTIMAGE_NAME_XIP:=hdsl_diagnostic_ddr.$(PROFILE).appimage_xip
BOOTIMAGE_NAME_SIGNED:=hdsl_diagnostic_ddr.$(PROFILE).appimage.signed
BOOTIMAGE_RPRC_NAME:=hdsl_diagnostic_ddr.$(PROFILE).rprc
BOOTIMAGE_RPRC_NAME_XIP:=hdsl_diagnostic_ddr.$(PROFILE).rprc_xip
BOOTIMAGE_RPRC_NAME_TMP:=hdsl_diagnostic_ddr.$(PROFILE).rprc_tmp
BOOTIMAGE_NAME_HS:=hdsl_diagnostic_ddr.$(PROFILE).appimage.hs
BOOTIMAGE_NAME_HS_FS:=hdsl_diagnostic_ddr.$(PROFILE).appimage.hs_fs
TARGETS := $(BOOTIMAGE_NAME)
ifeq ($(DEVICE_TYPE), HS)
TARGETS += $(BOOTIMAGE_NAME_HS)
endif
FILES_common := \
hdsl_diagnostic_ddr.c \
main.c \
ti_drivers_config.c \
ti_drivers_open_close.c \
ti_board_config.c \
ti_board_open_close.c \
ti_dpl_config.c \
ti_pinmux_config.c \
ti_power_clock_config.c \
FILES_PATH_common = \
.. \
../../.. \
generated \
INCLUDES_common := \
-I${CG_TOOL_ROOT}/include/c \
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source \
-I${MOTOR_CONTROL_SDK_PATH}/source \
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include \
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \
-Igenerated \
DEFINES_common := \
-DSOC_AM243X \
CFLAGS_common := \
-mcpu=cortex-r5 \
-mfloat-abi=hard \
-mfpu=vfpv3-d16 \
-mthumb \
-Wall \
-Werror \
-g \
-Wno-gnu-variable-sized-type-not-at-end \
-Wno-unused-function \
CFLAGS_cpp_common := \
-Wno-c99-designator \
-Wno-extern-c-compat \
-Wno-c++11-narrowing \
-Wno-reorder-init-list \
-Wno-deprecated-register \
-Wno-writable-strings \
-Wno-enum-compare \
-Wno-reserved-user-defined-literal \
-Wno-unused-const-variable \
-x c++ \
CFLAGS_debug := \
-D_DEBUG_=1 \
CFLAGS_release := \
-Os \
LNK_FILES_common = \
linker.cmd \
LIBS_PATH_common = \
-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
-Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/lib \
-Wl,-i${CG_TOOL_ROOT}/lib \
LIBS_common = \
-lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
-ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
-lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
-lmotorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
-llibc.a \
-llibsysbm.a \
LFLAGS_common = \
-Wl,--diag_suppress=10063 \
-Wl,--ram_model \
-Wl,--reread_libs \
LIBS_NAME = \
freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
motorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
libc.a \
libsysbm.a \
LIBS_PATH_NAME = \
${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/lib \
${CG_TOOL_ROOT}/lib \
FILES := $(FILES_common) $(FILES_$(PROFILE))
ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
LIBS := $(LIBS_common) $(LIBS_$(PROFILE))
LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE))
LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE))
LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE))
LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE))
OBJDIR := obj/$(PROFILE)/
OBJS := $(FILES:%.c=%.obj)
OBJS += $(ASMFILES:%.S=%.obj)
DEPS := $(FILES:%.c=%.d)
vpath %.obj $(OBJDIR)
vpath %.c $(FILES_PATH)
vpath %.S $(FILES_PATH)
vpath %.lib $(LIBS_PATH_NAME)
vpath %.a $(LIBS_PATH_NAME)
$(OBJDIR)/%.obj %.obj: %.c
@echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $<
$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
$(OBJDIR)/%.obj %.obj: %.S
@echo Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $<
$(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
all: $(TARGETS)
SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h
SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h
SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h
SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c
SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h
SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h
$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME)
@echo .
@echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ...
$(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES)
@echo Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
@echo .
clean:
@echo Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
$(RMDIR) $(OBJDIR)
$(RM) $(OUTNAME)
$(RM) $(BOOTIMAGE_NAME)
$(RM) $(BOOTIMAGE_NAME_XIP)
$(RM) $(BOOTIMAGE_NAME_SIGNED)
$(RM) $(BOOTIMAGE_NAME_HS)
$(RM) $(BOOTIMAGE_NAME_HS_FS)
$(RM) $(BOOTIMAGE_RPRC_NAME)
$(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
$(RMDIR) generated/
scrub:
@echo Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang hdsl_diagnostic_ddr ...
$(RMDIR) obj
ifeq ($(OS),Windows_NT)
$(RM) \*.out
$(RM) \*.map
$(RM) \*.appimage*
$(RM) \*.rprc*
$(RM) \*.tiimage*
$(RM) \*.bin
else
$(RM) *.out
$(RM) *.map
$(RM) *.appimage*
$(RM) *.rprc*
$(RM) *.tiimage*
$(RM) *.bin
endif
$(RMDIR) generated
$(OBJS): | $(OBJDIR)
$(OBJDIR):
$(MKDIR) $@
.NOTPARALLEL:
.INTERMEDIATE: syscfg
$(SYSCFG_GEN_FILES): syscfg
syscfg: ../example.syscfg
@echo Generating SysConfig files ...
$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg
syscfg-gui:
$(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALV_beta --context r5fss0-0 --part ALV --package ALV --output generated/ ../example.syscfg
#
# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
#
ifeq ($(OS),Windows_NT)
EXE_EXT=.exe
endif
ifeq ($(OS),Windows_NT)
BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
else
BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
endif
BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_r5fss0-1 = 5
BOOTIMAGE_CORE_ID_r5fss1-0 = 6
BOOTIMAGE_CORE_ID_r5fss1-1 = 7
BOOTIMAGE_CORE_ID_m4fss0-0 = 14
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
OUTRPRC_CMD = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
ifeq ($(OS),Windows_NT)
XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
else
XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
endif
MULTI_CORE_IMAGE_PARAMS = \
$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
MULTI_CORE_IMAGE_PARAMS_XIP = \
$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
$(BOOTIMAGE_NAME): $(OUTNAME)
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
ifneq ($(OS),Windows_NT)
$(CHMOD) a+x $(XIPGEN_CMD)
endif
$(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
$(RM) $(BOOTIMAGE_RPRC_NAME)
$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
# Sign the appimage for HS-FS using appimage signing script
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!!
@echo .
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
@echo .
$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME)
ifeq ($(DEVICE_TYPE), HS)
# Sign the appimage using appimage signing script
ifeq ($(ENC_ENABLED),no)
@echo Boot image signing: Encryption is disabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
else
@echo Boot image signing: Encryption is enabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
$(RM) $(BOOTIMAGE_NAME)-enc
endif
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
@echo .
endif
-include $(addprefix $(OBJDIR)/, $(DEPS))

106
examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
View File

@ -1,106 +0,0 @@
#
# Auto generated makefile
#
# Below variables need to be defined outside this file or via command line
# - MOTOR_CONTROL_SDK_PATH
# - PROFILE
# - CG_TOOL_ROOT
# - OUTNAME
# - CCS_INSTALL_DIR
# - CCS_IDE_MODE
CCS_PATH=$(CCS_INSTALL_DIR)
include ${MOTOR_CONTROL_SDK_PATH}/imports.mak
include ${MOTOR_CONTROL_SDK_PATH}/devconfig/devconfig.mak
STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
ifeq ($(OS), Windows_NT)
PYTHON=python
else
PYTHON=python3
endif
OUTFILE=$(PROFILE)/$(OUTNAME).out
BOOTIMAGE_PATH=$(abspath ${PROFILE})
BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
#
# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
#
ifeq ($(OS),Windows_NT)
EXE_EXT=.exe
endif
ifeq ($(OS),Windows_NT)
BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
else
BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
endif
BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_r5fss0-1 = 5
BOOTIMAGE_CORE_ID_r5fss1-0 = 6
BOOTIMAGE_CORE_ID_r5fss1-1 = 7
BOOTIMAGE_CORE_ID_m4fss0-0 = 14
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
OUTRPRC_CMD = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
ifeq ($(OS),Windows_NT)
XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
else
XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
endif
MULTI_CORE_IMAGE_PARAMS = \
$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
MULTI_CORE_IMAGE_PARAMS_XIP = \
$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
all:
ifeq ($(CCS_IDE_MODE),cloud)
# No post build steps
else
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ...
$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
$(RM) $(BOOTIMAGE_RPRC_NAME)
$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
# Sign the appimage for HS-FS using appimage signing script
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
ifeq ($(DEVICE_TYPE),HS)
# Sign the appimage using appimage signing script
ifeq ($(ENC_ENABLED),no)
@echo Boot image signing: Encryption is disabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
else
@echo Boot image signing: Encryption is enabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
$(RM) $(BOOTIMAGE_NAME)-enc
endif
endif
$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
@echo .
ifeq ($(DEVICE_TYPE),HS)
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
@echo .
else
@echo Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
@echo .
endif
endif

20
examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
View File

@ -1,20 +0,0 @@
#
# Auto generated makefile
#
export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..)
include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
PROFILE?=Release
PROJECT_NAME=hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang
all:
$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
clean:
$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
export:
$(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full

8
examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
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/*
* ======== syscfg_c.rov.xs ========
* This file contains the information needed by the Runtime Object
* View (ROV) tool.
*/
var crovFiles = [
"kernel/freertos/rov/FreeRTOS.rov.js",
];

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/**
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
* @cliArgs --device "AM64x" --package "ALV" --part "Default" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK@09.00.00"
* @versions {"tool":"1.17.0+3128"}
*/
/**
* Import the modules used in this configuration.
*/
const gpio = scripting.addModule("/drivers/gpio/gpio", {}, false);
const gpio1 = gpio.addInstance();
const gpio2 = gpio.addInstance();
const gpio3 = gpio.addInstance();
const i2c = scripting.addModule("/drivers/i2c/i2c", {}, false);
const i2c1 = i2c.addInstance();
const pruicss = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
const pruicss1 = pruicss.addInstance();
const udma = scripting.addModule("/drivers/udma/udma", {}, false);
const udma1 = udma.addInstance();
const debug_log = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71 = mpu_armv7.addInstance();
const mpu_armv72 = mpu_armv7.addInstance();
const mpu_armv73 = mpu_armv7.addInstance();
const mpu_armv74 = mpu_armv7.addInstance();
const mpu_armv75 = mpu_armv7.addInstance();
const mpu_armv76 = mpu_armv7.addInstance();
const hdsl = scripting.addModule("/position_sense/hdsl", {}, false);
const hdsl1 = hdsl.addInstance();
/**
* Write custom configuration values to the imported modules.
*/
gpio1.$name = "CONFIG_GPIO0";
gpio1.pinDir = "OUTPUT";
gpio1.GPIO.gpioPin.rx = false;
gpio1.GPIO.gpioPin.$assign = "GPMC0_CSn1";
gpio2.$name = "CONFIG_GPIO_COPY";
gpio2.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO17";
gpio3.$name = "CONFIG_GPIO_TEST_COPY";
gpio3.GPIO.gpioPin.$assign = "PRG1_PRU0_GPO18";
i2c1.$name = "CONFIG_I2C0";
i2c1.I2C.$assign = "I2C1";
pruicss1.$name = "CONFIG_PRU_ICSS1";
pruicss1.instance = "ICSSG1";
pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
udma1.$name = "CONFIG_UDMA0";
udma1.udmaBlkCopyChannel.create(1);
udma1.udmaBlkCopyChannel[0].$name = "CONFIG_UDMA_BLKCOPY_CH0";
udma1.udmaBlkCopyChannel[0].intrEnable = true;
udma1.udmaBlkCopyChannel[0].transferCallbackFxn = "App_udmaEventCb";
debug_log.enableUartLog = true;
debug_log.enableCssLog = false;
debug_log.uartLog.$name = "CONFIG_UART0";
debug_log.uartLog.UART.$assign = "USART0";
mpu_armv71.$name = "CONFIG_MPU_REGION0";
mpu_armv71.size = 31;
mpu_armv71.attributes = "Device";
mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute = false;
mpu_armv72.$name = "CONFIG_MPU_REGION1";
mpu_armv72.size = 15;
mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv73.$name = "CONFIG_MPU_REGION2";
mpu_armv73.baseAddr = 0x41010000;
mpu_armv73.size = 15;
mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv74.$name = "CONFIG_MPU_REGION3";
mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv74.baseAddr = 0x70000000;
mpu_armv74.size = 21;
mpu_armv75.$name = "CONFIG_MPU_REGION4";
mpu_armv75.baseAddr = 0x60000000;
mpu_armv75.size = 28;
mpu_armv75.accessPermissions = "Supervisor RD, User RD";
mpu_armv76.$name = "CONFIG_MPU_REGION5";
mpu_armv76.baseAddr = 0x80000000;
mpu_armv76.size = 31;
hdsl1.$name = "CONFIG_HDSL0";
hdsl1.coreClk = 300000000;
hdsl1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1";
const pruicss2 = pruicss.addInstance({}, false);
pruicss2.$name = "CONFIG_PRU_ICSS0";
pruicss2.instance = scripting.forceWrite("ICSSG0");
hdsl1.pru = pruicss2;
pruicss2.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO2";
/**
* Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
* version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to
* re-solve from scratch.
*/
gpio1.GPIO.$suggestSolution = "GPIO0";
gpio2.GPIO.$suggestSolution = "GPIO0";
gpio3.GPIO.$suggestSolution = "GPIO0";
i2c1.I2C.SCL.$suggestSolution = "I2C1_SCL";
i2c1.I2C.SDA.$suggestSolution = "I2C1_SDA";
debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD";
debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD";
hdsl1.PRU_ICSSG0_PRU.GPO2.$suggestSolution = "PRG0_PRU1_GPO2";
hdsl1.PRU_ICSSG0_PRU.GPO1.$suggestSolution = "PRG0_PRU1_GPO1";
hdsl1.PRU_ICSSG0_PRU.GPO0.$suggestSolution = "PRG0_PRU1_GPO0";
hdsl1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13";
hdsl1.PRU_ICSSG0_PRU.GPO5.$suggestSolution = "PRG0_PRU1_GPO5";
hdsl1.PRU_ICSSG0_PRU.GPO4.$suggestSolution = "PRG0_PRU1_GPO4";
hdsl1.PRU_ICSSG0_PRU.GPO3.$suggestSolution = "PRG0_PRU1_GPO3";
hdsl1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14";
hdsl1.PRU_ICSSG0_PRU.GPO8.$suggestSolution = "PRG0_PRU1_GPO8";
hdsl1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12";
hdsl1.PRU_ICSSG0_PRU.GPO6.$suggestSolution = "PRG0_PRU1_GPO6";
hdsl1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11";

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examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/main.c
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/*
* Copyright (C) 2018-2021 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdlib.h>
#include <kernel/dpl/DebugP.h>
#include "ti_drivers_config.h"
#include "ti_board_config.h"
#include "FreeRTOS.h"
#include "task.h"
#define MAIN_TASK_PRI (configMAX_PRIORITIES-1)
#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE))
StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
StaticTask_t gMainTaskObj;
TaskHandle_t gMainTask;
void hdsl_diagnostic_main(void *args);
void freertos_main(void *args)
{
hdsl_diagnostic_main(NULL);
vTaskDelete(NULL);
}
int main(void)
{
/* init SOC specific modules */
System_init();
Board_init();
/* This task is created at highest priority, it should create more tasks and then delete itself */
gMainTask = xTaskCreateStatic( freertos_main, /* Pointer to the function that implements the task. */
"freertos_main", /* Text name for the task. This is to facilitate debugging only. */
MAIN_TASK_SIZE, /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
NULL, /* We are not using the task parameter. */
MAIN_TASK_PRI, /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
gMainTaskStack, /* pointer to stack base */
&gMainTaskObj ); /* pointer to statically allocated task object memory */
configASSERT(gMainTask != NULL);
/* Start the scheduler to start the tasks executing. */
vTaskStartScheduler();
/* The following line should never be reached because vTaskStartScheduler()
will only return if there was not enough FreeRTOS heap memory available to
create the Idle and (if configured) Timer tasks. Heap management, and
techniques for trapping heap exhaustion, are described in the book text. */
DebugP_assertNoLog(0);
return 0;
}

115
examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/example.projectspec
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<?xml version="1.0" encoding="UTF-8"?>
<projectSpec>
<applicability>
<when>
<context
deviceFamily="ARM"
deviceId="Cortex R.AM64x"
/>
</when>
</applicability>
<project
title="Hdsl Diagnostic Ddr"
name = "hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang"
products="sysconfig;com.ti.MOTOR_CONTROL_SDK_AMXXX;"
configurations="
Debug,
Release,
"
connection="TIXDS110_Connection.xml"
toolChain="TICLANG"
cgtVersion="2.1.3"
device="Cortex R.AM64x"
deviceCore="MAIN_PULSAR_Cortex_R5_0_0"
ignoreDefaultDeviceSettings="true"
ignoreDefaultCCSSettings="true"
endianness="little"
outputFormat="ELF"
outputType="executable"
compilerBuildOptions="
-I${CG_TOOL_ROOT}/include/c
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source
-I${MOTOR_CONTROL_SDK_PATH}/source
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am64x/r5f
-mcpu=cortex-r5
-mfloat-abi=hard
-mfpu=vfpv3-d16
-mthumb
-Wall
-Werror
-g
-Wno-gnu-variable-sized-type-not-at-end
-Wno-unused-function
-DSOC_AM64X
"
linkerBuildOptions="
-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib
-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib
-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib
-i${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/lib
-i${CG_TOOL_ROOT}/lib
-m=hdsl_diagnostic_ddr.${ConfigName}.map
--diag_suppress=10063
--ram_model
--reread_libs
"
postBuildStep="$(MAKE) -C ${CCS_PROJECT_DIR} -f makefile_ccs_bootimage_gen OUTNAME=${BuildArtifactFileBaseName} PROFILE=${ConfigName} MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} CG_TOOL_ROOT=${CG_TOOL_ROOT} CCS_INSTALL_DIR=${CCS_INSTALL_DIR} CCS_IDE_MODE=${CCS_IDE_MODE} DEVICE=am64x"
enableSysConfigTool="true"
sysConfigBuildOptions="
--context r5fss0-0 --part Default --package ALV
"
description="A Hdsl Diagnostic Ddr FREERTOS project">
<configuration name="Debug"
compilerBuildOptions="
-D_DEBUG_=1
"
linkerBuildOptions="
-lfreertos.am64x.r5f.ti-arm-clang.debug.lib
-ldrivers.am64x.r5f.ti-arm-clang.debug.lib
-lboard.am64x.r5f.ti-arm-clang.debug.lib
-lmotorcontrol_hdsl.am64x.r5f.ti-arm-clang.debug.lib
-llibc.a
-llibsysbm.a
"
></configuration>
<configuration name="Release"
compilerBuildOptions="
-Os
"
linkerBuildOptions="
-lfreertos.am64x.r5f.ti-arm-clang.release.lib
-ldrivers.am64x.r5f.ti-arm-clang.release.lib
-lboard.am64x.r5f.ti-arm-clang.release.lib
-lmotorcontrol_hdsl.am64x.r5f.ti-arm-clang.release.lib
-llibc.a
-llibsysbm.a
"
></configuration>
<pathVariable name="MOTOR_CONTROL_SDK_PATH" path="${COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR}" scope="project" />
<file path="../../../hdsl_diagnostic_ddr.c" openOnCreation="false" excludeFromBuild="false" action="copy">
</file>
<file path="../main.c" openOnCreation="false" excludeFromBuild="false" action="copy">
</file>
<file path="linker.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
</file>
<file path="../example.syscfg" openOnCreation="false" excludeFromBuild="false" action="copy">
</file>
<file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am64x/EXAMPLE_MOTORCONTROL_HDSL.html"
openOnCreation="false" excludeFromBuild="false" targetName="README.html" action="link">
</file>
<file path="../../../hdsl_diagnostic_ddr.h" openOnCreation="false" excludeFromBuild="true" action="copy">
</file>
<file path="syscfg_c.rov.xs" openOnCreation="false" excludeFromBuild="false" action="copy">
</file>
<file path="makefile_ccs_bootimage_gen" openOnCreation="false" excludeFromBuild="false" action="copy">
</file>
</project>
</projectSpec>

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/* This is the stack that is used by code running within main()
* In case of NORTOS,
* - This means all the code outside of ISR uses this stack
* In case of FreeRTOS
* - This means all the code until vTaskStartScheduler() is called in main()
* uses this stack.
* - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
*/
--stack_size=16384
/* This is the heap size for malloc() API in NORTOS and FreeRTOS
* This is also the heap used by pvPortMalloc in FreeRTOS
*/
--heap_size=32768
-e_vectors /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
/* This is the size of stack when R5 is in IRQ mode
* In NORTOS,
* - Here interrupt nesting is enabled
* - This is the stack used by ISRs registered as type IRQ
* In FreeRTOS,
* - Here interrupt nesting is disabled
* - This is stack that is used initally when a IRQ is received
* - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
* - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
*/
__IRQ_STACK_SIZE = 256;
/* This is the size of stack when R5 is in IRQ mode
* - In both NORTOS and FreeRTOS nesting is disabled for FIQ
*/
__FIQ_STACK_SIZE = 256;
__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
__ABORT_STACK_SIZE = 256; /* This is the size of stack when R5 is in ABORT mode */
__UNDEFINED_STACK_SIZE = 256; /* This is the size of stack when R5 is in UNDEF mode */
/* section identifier
*/
SECTIONS
{
/* This has the R5F entry point and vector table, this MUST be at 0x0 */
.vectors:{} palign(8) > R5F_VECS
/* This has the R5F boot code until MPU is enabled, this MUST be at a address < 0x80000000
* i.e this cannot be placed in DDR
*/
GROUP {
.text.hwi: palign(8)
.text.cache: palign(8)
.text.mpu: palign(8)
.text.boot: palign(8)
.text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
} > MSRAM
/* This is rest of code. This can be placed in DDR if DDR is available and needed */
GROUP {
.text: {} palign(8) /* This is where code resides */
.rodata: {} palign(8) /* This is where const's go */
} > MSRAM
/* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
GROUP {
.data: {} palign(8) /* This is where initialized globals and static go */
} > MSRAM
/* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
GROUP {
.bss: {} palign(8) /* This is where uninitialized globals go */
RUN_START(__BSS_START)
RUN_END(__BSS_END)
.sysmem: {} palign(8) /* This is where the malloc heap goes */
.stack: {} palign(8) /* This is where the main() stack goes */
} > MSRAM
/* This is where the stacks for different R5F modes go */
GROUP {
.irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
RUN_START(__IRQ_STACK_START)
RUN_END(__IRQ_STACK_END)
.fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
RUN_START(__FIQ_STACK_START)
RUN_END(__FIQ_STACK_END)
.svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
RUN_START(__SVC_STACK_START)
RUN_END(__SVC_STACK_END)
.abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
RUN_START(__ABORT_STACK_START)
RUN_END(__ABORT_STACK_END)
.undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
RUN_START(__UNDEFINED_STACK_START)
RUN_END(__UNDEFINED_STACK_END)
} > MSRAM
/* Sections needed for C++ projects */
GROUP {
.ARM.exidx: {} palign(8) /* Needed for C++ exception handling */
.init_array: {} palign(8) /* Contains function pointers called before main */
.fini_array: {} palign(8) /* Contains function pointers called after main */
} > MSRAM
/* General purpose user shared memory, used in some examples */
.bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
/* this is used when Debug log's to shared memory are enabled, else this is not used */
.bss.log_shared_mem (NOLOAD) : {} > LOG_SHM_MEM
/* this is used only when IPC RPMessage is enabled, else this is not used */
.bss.ipc_vring_mem (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
/* General purpose non cacheable memory, used in some examples */
.bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
.hdslInterface_ddr_mem (NOLOAD) > DDR
}
/*
NOTE: Below memory is reserved for DMSC usage
- During Boot till security handoff is complete
0x701E0000 - 0x701FFFFF (128KB)
- After "Security Handoff" is complete (i.e at run time)
0x701F4000 - 0x701FFFFF (48KB)
Security handoff is complete when this message is sent to the DMSC,
TISCI_MSG_SEC_HANDOVER
This should be sent once all cores are loaded and all application
specific firewall calls are setup.
*/
MEMORY
{
R5F_VECS : ORIGIN = 0x00000000 , LENGTH = 0x00000040
R5F_TCMA : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
/* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
/* when using multi-core application's i.e more than one R5F/M4F active, make sure
* this memory does not overlap with other R5F's
*/
MSRAM : ORIGIN = 0x70080000 , LENGTH = 0x60000
/* DDR segment of memory */
DDR : ORIGIN = 0x80000000 , LENGTH = 0x3FFFFFFF
/* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
* other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
*/
FLASH : ORIGIN = 0x60100000 , LENGTH = 0x80000
/* shared memory segments */
/* On R5F,
* - make sure there is a MPU entry which maps below regions as non-cache
*/
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x80
LOG_SHM_MEM : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
}

308
examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile
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@ -1,308 +0,0 @@
#
# Auto generated makefile
#
export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..)
include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak
CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
CC=$(CG_TOOL_ROOT)/bin/tiarmclang
LNK=$(CG_TOOL_ROOT)/bin/tiarmclang
STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
ifeq ($(OS), Windows_NT)
PYTHON=python
else
PYTHON=python3
endif
PROFILE?=release
ConfigName:=$(PROFILE)
OUTNAME:=hdsl_diagnostic_ddr.$(PROFILE).out
BOOTIMAGE_PATH=$(abspath .)
BOOTIMAGE_NAME:=hdsl_diagnostic_ddr.$(PROFILE).appimage
BOOTIMAGE_NAME_XIP:=hdsl_diagnostic_ddr.$(PROFILE).appimage_xip
BOOTIMAGE_NAME_SIGNED:=hdsl_diagnostic_ddr.$(PROFILE).appimage.signed
BOOTIMAGE_RPRC_NAME:=hdsl_diagnostic_ddr.$(PROFILE).rprc
BOOTIMAGE_RPRC_NAME_XIP:=hdsl_diagnostic_ddr.$(PROFILE).rprc_xip
BOOTIMAGE_RPRC_NAME_TMP:=hdsl_diagnostic_ddr.$(PROFILE).rprc_tmp
BOOTIMAGE_NAME_HS:=hdsl_diagnostic_ddr.$(PROFILE).appimage.hs
BOOTIMAGE_NAME_HS_FS:=hdsl_diagnostic_ddr.$(PROFILE).appimage.hs_fs
TARGETS := $(BOOTIMAGE_NAME)
ifeq ($(DEVICE_TYPE), HS)
TARGETS += $(BOOTIMAGE_NAME_HS)
endif
FILES_common := \
hdsl_diagnostic_ddr.c \
main.c \
ti_drivers_config.c \
ti_drivers_open_close.c \
ti_board_config.c \
ti_board_open_close.c \
ti_dpl_config.c \
ti_pinmux_config.c \
ti_power_clock_config.c \
FILES_PATH_common = \
.. \
../../.. \
generated \
INCLUDES_common := \
-I${CG_TOOL_ROOT}/include/c \
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source \
-I${MOTOR_CONTROL_SDK_PATH}/source \
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include \
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am64x/r5f \
-Igenerated \
DEFINES_common := \
-DSOC_AM64X \
CFLAGS_common := \
-mcpu=cortex-r5 \
-mfloat-abi=hard \
-mfpu=vfpv3-d16 \
-mthumb \
-Wall \
-Werror \
-g \
-Wno-gnu-variable-sized-type-not-at-end \
-Wno-unused-function \
CFLAGS_cpp_common := \
-Wno-c99-designator \
-Wno-extern-c-compat \
-Wno-c++11-narrowing \
-Wno-reorder-init-list \
-Wno-deprecated-register \
-Wno-writable-strings \
-Wno-enum-compare \
-Wno-reserved-user-defined-literal \
-Wno-unused-const-variable \
-x c++ \
CFLAGS_debug := \
-D_DEBUG_=1 \
CFLAGS_release := \
-Os \
LNK_FILES_common = \
linker.cmd \
LIBS_PATH_common = \
-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
-Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/lib \
-Wl,-i${CG_TOOL_ROOT}/lib \
LIBS_common = \
-lfreertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
-ldrivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
-lboard.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
-lmotorcontrol_hdsl.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
-llibc.a \
-llibsysbm.a \
LFLAGS_common = \
-Wl,--diag_suppress=10063 \
-Wl,--ram_model \
-Wl,--reread_libs \
LIBS_NAME = \
freertos.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
drivers.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
board.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
motorcontrol_hdsl.am64x.r5f.ti-arm-clang.${ConfigName}.lib \
libc.a \
libsysbm.a \
LIBS_PATH_NAME = \
${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/lib \
${CG_TOOL_ROOT}/lib \
FILES := $(FILES_common) $(FILES_$(PROFILE))
ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
LIBS := $(LIBS_common) $(LIBS_$(PROFILE))
LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE))
LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE))
LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE))
LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE))
OBJDIR := obj/$(PROFILE)/
OBJS := $(FILES:%.c=%.obj)
OBJS += $(ASMFILES:%.S=%.obj)
DEPS := $(FILES:%.c=%.d)
vpath %.obj $(OBJDIR)
vpath %.c $(FILES_PATH)
vpath %.S $(FILES_PATH)
vpath %.lib $(LIBS_PATH_NAME)
vpath %.a $(LIBS_PATH_NAME)
$(OBJDIR)/%.obj %.obj: %.c
@echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $<
$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
$(OBJDIR)/%.obj %.obj: %.S
@echo Compiling: am64x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $<
$(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
all: $(TARGETS)
SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h
SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h
SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h
SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c
SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h
SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h
$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME)
@echo .
@echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ ...
$(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES)
@echo Linking: am64x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
@echo .
clean:
@echo Cleaning: am64x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
$(RMDIR) $(OBJDIR)
$(RM) $(OUTNAME)
$(RM) $(BOOTIMAGE_NAME)
$(RM) $(BOOTIMAGE_NAME_XIP)
$(RM) $(BOOTIMAGE_NAME_SIGNED)
$(RM) $(BOOTIMAGE_NAME_HS)
$(RM) $(BOOTIMAGE_NAME_HS_FS)
$(RM) $(BOOTIMAGE_RPRC_NAME)
$(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
$(RMDIR) generated/
scrub:
@echo Scrubing: am64x:r5fss0-0:freertos:ti-arm-clang hdsl_diagnostic_ddr ...
$(RMDIR) obj
ifeq ($(OS),Windows_NT)
$(RM) \*.out
$(RM) \*.map
$(RM) \*.appimage*
$(RM) \*.rprc*
$(RM) \*.tiimage*
$(RM) \*.bin
else
$(RM) *.out
$(RM) *.map
$(RM) *.appimage*
$(RM) *.rprc*
$(RM) *.tiimage*
$(RM) *.bin
endif
$(RMDIR) generated
$(OBJS): | $(OBJDIR)
$(OBJDIR):
$(MKDIR) $@
.NOTPARALLEL:
.INTERMEDIATE: syscfg
$(SYSCFG_GEN_FILES): syscfg
syscfg: ../example.syscfg
@echo Generating SysConfig files ...
$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg
syscfg-gui:
$(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device AM64x --context r5fss0-0 --part Default --package ALV --output generated/ ../example.syscfg
#
# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
#
ifeq ($(OS),Windows_NT)
EXE_EXT=.exe
endif
ifeq ($(OS),Windows_NT)
BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
else
BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
endif
BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
BOOTIMAGE_CORE_ID_a53ss0-0 = 0
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_r5fss0-1 = 5
BOOTIMAGE_CORE_ID_r5fss1-0 = 6
BOOTIMAGE_CORE_ID_r5fss1-1 = 7
BOOTIMAGE_CORE_ID_m4fss0-0 = 14
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
OUTRPRC_CMD = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
ifeq ($(OS),Windows_NT)
XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
else
XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
endif
MULTI_CORE_IMAGE_PARAMS = \
$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
MULTI_CORE_IMAGE_PARAMS_XIP = \
$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
$(BOOTIMAGE_NAME): $(OUTNAME)
@echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
ifneq ($(OS),Windows_NT)
$(CHMOD) a+x $(XIPGEN_CMD)
endif
$(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
$(RM) $(BOOTIMAGE_RPRC_NAME)
$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
# Sign the appimage for HS-FS using appimage signing script
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
@echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!!
@echo .
@echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
@echo .
$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME)
ifeq ($(DEVICE_TYPE), HS)
# Sign the appimage using appimage signing script
ifeq ($(ENC_ENABLED),no)
@echo Boot image signing: Encryption is disabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
else
@echo Boot image signing: Encryption is enabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
$(RM) $(BOOTIMAGE_NAME)-enc
endif
@echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
@echo .
endif
-include $(addprefix $(OBJDIR)/, $(DEPS))

107
examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen
View File

@ -1,107 +0,0 @@
#
# Auto generated makefile
#
# Below variables need to be defined outside this file or via command line
# - MOTOR_CONTROL_SDK_PATH
# - PROFILE
# - CG_TOOL_ROOT
# - OUTNAME
# - CCS_INSTALL_DIR
# - CCS_IDE_MODE
CCS_PATH=$(CCS_INSTALL_DIR)
include ${MOTOR_CONTROL_SDK_PATH}/imports.mak
include ${MOTOR_CONTROL_SDK_PATH}/devconfig/devconfig.mak
STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
ifeq ($(OS), Windows_NT)
PYTHON=python
else
PYTHON=python3
endif
OUTFILE=$(PROFILE)/$(OUTNAME).out
BOOTIMAGE_PATH=$(abspath ${PROFILE})
BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
#
# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
#
ifeq ($(OS),Windows_NT)
EXE_EXT=.exe
endif
ifeq ($(OS),Windows_NT)
BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
else
BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
endif
BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
BOOTIMAGE_CORE_ID_a53ss0-0 = 0
BOOTIMAGE_CORE_ID_r5fss0-0 = 4
BOOTIMAGE_CORE_ID_r5fss0-1 = 5
BOOTIMAGE_CORE_ID_r5fss1-0 = 6
BOOTIMAGE_CORE_ID_r5fss1-1 = 7
BOOTIMAGE_CORE_ID_m4fss0-0 = 14
SBL_RUN_ADDRESS=0x70000000
SBL_DEV_ID=55
MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
OUTRPRC_CMD = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
ifeq ($(OS),Windows_NT)
XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
else
XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
endif
MULTI_CORE_IMAGE_PARAMS = \
$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
MULTI_CORE_IMAGE_PARAMS_XIP = \
$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
all:
ifeq ($(CCS_IDE_MODE),cloud)
# No post build steps
else
@echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) ...
$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
$(RM) $(BOOTIMAGE_RPRC_NAME)
$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
# Sign the appimage for HS-FS using appimage signing script
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
ifeq ($(DEVICE_TYPE),HS)
# Sign the appimage using appimage signing script
ifeq ($(ENC_ENABLED),no)
@echo Boot image signing: Encryption is disabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
else
@echo Boot image signing: Encryption is enabled.
$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
$(RM) $(BOOTIMAGE_NAME)-enc
endif
endif
$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
@echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
@echo .
ifeq ($(DEVICE_TYPE),HS)
@echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
@echo .
else
@echo Boot image: am64x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
@echo .
endif
endif

20
examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec
View File

@ -1,20 +0,0 @@
#
# Auto generated makefile
#
export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../..)
include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
PROFILE?=Release
PROJECT_NAME=hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang
all:
$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
clean:
$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
export:
$(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full

8
examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs
View File

@ -1,8 +0,0 @@
/*
* ======== syscfg_c.rov.xs ========
* This file contains the information needed by the Runtime Object
* View (ROV) tool.
*/
var crovFiles = [
"kernel/freertos/rov/FreeRTOS.rov.js",
];

925
examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.c
View File

@ -1,925 +0,0 @@
/*
* Copyright (C) 2021-2023 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPgResS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <stdbool.h>
#include <kernel/dpl/HwiP.h>
#include <kernel/dpl/CacheP.h>
#include <kernel/dpl/DebugP.h>
#include <kernel/dpl/SemaphoreP.h>
#include <kernel/dpl/ClockP.h>
#include <drivers/pruicss.h>
#include <drivers/udma.h>
#include "ti_drivers_config.h"
#include "ti_drivers_open_close.h"
#include "ti_board_open_close.h"
#include "hdsl_diagnostic_ddr.h"
#include <position_sense/hdsl/include/hdsl_drv.h>
#include <position_sense/hdsl/include/pruss_intc_mapping.h>
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000)
#include <position_sense/hdsl/firmware/hdsl_master_icssg_freerun_225_mhz_bin.h>
#include <position_sense/hdsl/firmware/hdsl_master_icssg_sync_225_mhz_bin.h>
/* Divide factor for normal clock (default value for 225 MHz=23) */
#define DIV_FACTOR_NORMAL 23
/* Divide factor for oversampled clock (default value for 225 MHz=2) */
#define DIV_FACTOR_OVERSAMPLED 2
#endif
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000)
#include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h>
#include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h>
#include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h>
#include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h>
/* Divide factor for normal clock (default value for 300 MHz=31) */
#define DIV_FACTOR_NORMAL 31
/* Divide factor for oversampled clock (default value for 300 MHz=3) */
#define DIV_FACTOR_OVERSAMPLED 3
#endif
#ifdef HDSL_AM64xE1_TRANSCEIVER
#include <board/ioexp/ioexp_tca6424.h>
#endif
#define PRUICSS_PRUx PRUICSS_PRU1
/* Oversample rate 8*/
#define OVERSAMPLE_RATE 7
#define HDSL_EN (0x1 << 26)
/* OCP as clock, div 32 */
#define HDSL_TX_CFG (0x10 | (DIV_FACTOR_NORMAL << 16))
/* OCP as clock, div 4, 8x OSR */
#define HDSL_RX_CFG (0x10 | (DIV_FACTOR_OVERSAMPLED << 16) | OVERSAMPLE_RATE | 0x08)
#define CTR_EN (1 << 3)
#define MAX_WAIT 20000
/* DDR Trace is triggered for each H-Frame. SYS_EVENT_21 is triggered for each
H-Frame from PRU. SYS_EVENT_21 is mapped to PRU_ICSSG0_PR1_HOST_INTR_PEND_3 of R5F
in INTC Mapping. */
/*Event number for SYS_EVENT_21 (pr1_pru_mst_intr<5>_int_req) */
#define HDSL_DDR_TRACE_ICSS_INTC_EVENT_NUM (21U)
/* R5F Interrupt number for DDR Traces */
#define HDSL_DDR_TRACE_R5F_IRQ_NUM (CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_3)
extern PRUICSS_Config gPruicssConfig[2];
Udma_ChHandle chHandle;
/* To store user input to start DDR copy*/
volatile uint8_t start_copy;
/* To store user input number of count of DDR copy*/
uint16_t ddr_trace_count;
/* To save log count during DDR copy*/
uint32_t temp_count_arr[NUM_RESOURCES];
/* To save log v-frame count during DDR copy*/
uint32_t v_frames_count_arr[NUM_RESOURCES];
/* To copy HDSL Interface structure ddr location */
HDSL_Interface gHdslInterface_ddr[NUM_RESOURCES] __attribute__((aligned(128), section(".hdslInterface_ddr_mem")));
HwiP_Object gPRUHwiObject;
/** \brief Global Structure pointer holding PRUSS1 memory Map. */
PRUICSS_Handle gPruIcss0Handle;
PRUICSS_IntcInitData gPruss0_intc_initdata = PRU_ICSS0_INTC_INITDATA;
PRUICSS_Handle gPruIcss1Handle;
PRUICSS_IntcInitData gPruss1_intc_initdata = PRU_ICSS1_INTC_INITDATA;
HDSL_Handle gHdslHandleCh0;
static void *gPru_cfg;
static char gUart_buffer[256];
void *gPru_dramx;
void *gPru_dramx_0;
void *gPru_dramx_1;
int get_pos=1;
uint32_t gMulti_turn, gRes;
uint64_t gMask;
uint8_t gPc_data;
uint8_t gPc_addrh, gPc_addrl, gPc_offh, gPc_offl, gPc_buf0, gPc_buf1, gPc_buf2, gPc_buf3, gPc_buf4, gPc_buf5, gPc_buf6, gPc_buf7;
#ifdef HDSL_AM64xE1_TRANSCEIVER
static TCA6424_Config gTCA6424_Config;
#endif
/* Semaphore to indicate transfer completion */
static SemaphoreP_Object gUdmaTestDoneSem;
/* UDMA TRPD Memory */
uint8_t gUdmaTestTrpdMem[UDMA_TEST_TRPD_SIZE] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
void App_udmaEventCb(Udma_EventHandle eventHandle, uint32_t eventType, void *appData);
static void App_udmaTrpdInit(Udma_ChHandle chHandle,
uint8_t *trpdMem,
const void *destBuf,
const void *srcBuf,
uint32_t length);
void sync_calculation(HDSL_Handle hdslHandle)
{
uint8_t ES;
uint16_t wait_before_start;
uint32_t counter, period, index;
volatile uint32_t cap6_rise0, cap6_rise1, cap6_fall0, cap6_fall1;
uint8_t EXTRA_EDGE_ARR[8] = {0x00 ,0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0xFC, 0xFE};
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000)
uint32_t minm_bits = 112, cycle_per_bit = 24, max_stuffing = 26, stuffing_size = 6, cycle_per_overclock_bit =3, minm_extra_size = 4, sync_param_mem_start = 0xDC;
uint32_t cycles_left, additional_bits, minm_cycles, time_gRest, extra_edge, extra_size, num_of_stuffing, extra_size_remainder, stuffing_remainder, bottom_up_cycles;
#endif
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000)
uint32_t minm_bits = 112, cycle_per_bit = 32, max_stuffing = 26, stuffing_size = 6, cycle_per_overclock_bit =4, minm_extra_size = 4, sync_param_mem_start = 0xDC;
uint32_t cycles_left, additional_bits, minm_cycles, time_gRest, extra_edge, extra_size, num_of_stuffing, extra_size_remainder, stuffing_remainder, bottom_up_cycles;
#endif
/*measure of SYNC period starts*/
ES = HDSL_get_sync_ctrl(hdslHandle);
volatile uint32_t* carp6_rise_addr = (uint32_t*)(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP1_SLV_REGS_BASE + CSL_ICSS_G_PR1_IEP0_SLV_CAPR6_REG0);
volatile uint32_t* carp6_fall_addr = (uint32_t*)(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP1_SLV_REGS_BASE + CSL_ICSS_G_PR1_IEP0_SLV_CAPF6_REG0);
cap6_rise0 = *(carp6_rise_addr);
cap6_fall0 = *(carp6_fall_addr);
cap6_rise1 = cap6_rise0;
cap6_fall1 = cap6_fall0;
counter = 0;
for(index = 0 ; index <2 ; index++)
{
cap6_rise0 = cap6_rise1;
cap6_fall0 = cap6_fall1;
while((cap6_fall0 == cap6_fall1) || (cap6_rise0 == cap6_rise1))
{
cap6_rise1 = *(carp6_rise_addr);
cap6_fall1 = *(carp6_fall_addr);
counter++;
if(counter > MAX_WAIT)
{
DebugP_log("\r\n SYNC PULSE NOT FOUND, WAITING FOR SYNC PULSE");
counter = 0;
}
}
}
period = cap6_rise1 - cap6_rise0;
/*measure of SYNC period ends*/
minm_cycles = minm_bits * ES * cycle_per_bit;
cycles_left = period - minm_cycles;
time_gRest = (cycles_left % cycle_per_bit) / cycle_per_overclock_bit;
additional_bits = cycles_left / cycle_per_bit;
extra_edge = EXTRA_EDGE_ARR[time_gRest];
num_of_stuffing = additional_bits / stuffing_size;
extra_size = additional_bits % stuffing_size;
extra_size = extra_size + minm_extra_size * ES;
if(num_of_stuffing > ES * max_stuffing)
{
extra_size = extra_size + (((num_of_stuffing) - (max_stuffing * ES)) * stuffing_size);
num_of_stuffing = ES * max_stuffing;
}
extra_size_remainder = extra_size % ES;
extra_size = extra_size / ES;
stuffing_remainder = num_of_stuffing % ES;
num_of_stuffing = num_of_stuffing / ES;
bottom_up_cycles = (minm_cycles - minm_extra_size * ES * cycle_per_bit);
bottom_up_cycles = bottom_up_cycles + (stuffing_size * (ES * num_of_stuffing + stuffing_remainder))*cycle_per_bit;
bottom_up_cycles = bottom_up_cycles + ((ES * extra_size + extra_size_remainder) * cycle_per_bit ) + time_gRest * cycle_per_overclock_bit;
wait_before_start = (84 * cycle_per_bit)+((8 - time_gRest)*cycle_per_overclock_bit)+(num_of_stuffing * stuffing_size * cycle_per_bit);
if(stuffing_remainder != 0)
{
wait_before_start = wait_before_start+(stuffing_size * cycle_per_bit);
}
wait_before_start = wait_before_start - 51;
if(extra_size < 4 || extra_size > 9)
{
DebugP_log("\r\n ERROR: ES or period selected is Invalid ");
}
DebugP_log("\r\n ********************************************************************");
DebugP_log("\r\n SYNC MODE: period = %d", period);
DebugP_log("\r\n SYNC MODE: ES = %d", ES);
DebugP_log("\r\n SYNC MODE: counter = %d", counter);
DebugP_log("\r\n SYNC MODE: wait_before_start = %d", wait_before_start);
DebugP_log("\r\n SYNC MODE: bottom_up_cycles = %d", bottom_up_cycles);
DebugP_log("\r\n SYNC MODE: extra_size = %d", extra_size);
DebugP_log("\r\n SYNC MODE: temp_gRest = %d", time_gRest);
DebugP_log("\r\n SYNC MODE: extra_edge = %d", extra_edge);
DebugP_log("\r\n SYNC MODE: num_of_stuffing = %d", num_of_stuffing);
DebugP_log("\r\n SYNC MODE: extra_size_remainder = %d", extra_size_remainder);
DebugP_log("\r\n SYNC MODE: stuffing_remainder = %d", stuffing_remainder);
DebugP_log("\r\n ********************************************************************");
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000)
sync_param_mem_start =sync_param_mem_start + (uint32_t)gPru_dramx;
#endif
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000)
sync_param_mem_start =sync_param_mem_start + (uint32_t)hdslHandle->baseMemAddr;
#endif
HWREGB(sync_param_mem_start) = extra_size;
sync_param_mem_start = sync_param_mem_start + 1;
HWREGB(sync_param_mem_start) = num_of_stuffing;
sync_param_mem_start = sync_param_mem_start + 1;
HWREGB(sync_param_mem_start) = extra_edge;
sync_param_mem_start = sync_param_mem_start + 1;
HWREGB(sync_param_mem_start) = time_gRest;
sync_param_mem_start = sync_param_mem_start + 1;
HWREGB(sync_param_mem_start) = extra_size_remainder;
sync_param_mem_start = sync_param_mem_start + 1;
HWREGB(sync_param_mem_start) = stuffing_remainder;
sync_param_mem_start = sync_param_mem_start + 1;
HWREGH(sync_param_mem_start) = wait_before_start;
}
void udma_copy(uint8_t *srcBuf,uint8_t *destBuf,uint32_t length)
{
int32_t retVal = UDMA_SOK;
uint64_t pDesc;
uint32_t trRespStatus;
uint8_t *trpdMem = &gUdmaTestTrpdMem[0U];
uint64_t trpdMemPhy = (uint64_t) Udma_defaultVirtToPhyFxn(trpdMem, 0U, NULL);
/* Init TR packet descriptor */
App_udmaTrpdInit(chHandle, trpdMem, destBuf, srcBuf, length);
/* Submit TRPD to channel */
retVal = Udma_ringQueueRaw(Udma_chGetFqRingHandle(chHandle), trpdMemPhy);
DebugP_assert(UDMA_SOK == retVal);
/* Wait for return descriptor in completion ring - this marks transfer completion */
SemaphoreP_pend(&gUdmaTestDoneSem, SystemP_WAIT_FOREVER);
retVal = Udma_ringDequeueRaw(Udma_chGetCqRingHandle(chHandle), &pDesc);
DebugP_assert(UDMA_SOK == retVal);
/* Check TR response status */
CacheP_inv(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD);
trRespStatus = UdmaUtils_getTrpdTr15Response(trpdMem, 1U, 0U);
//DebugP_log("\r\n.trRespStatus = %u ", trRespStatus);
DebugP_assert(CSL_UDMAP_TR_RESPONSE_STATUS_COMPLETE == trRespStatus);
/* Validate data in ddr */
CacheP_inv(destBuf, length, CacheP_TYPE_ALLD);
}
void App_udmaEventCb(Udma_EventHandle eventHandle, uint32_t eventType, void *appData)
{
if(UDMA_EVENT_TYPE_DMA_COMPLETION == eventType)
{
SemaphoreP_post(&gUdmaTestDoneSem);
}
}
static void App_udmaTrpdInit(Udma_ChHandle chHandle,
uint8_t *trpdMem,
const void *destBuf,
const void *srcBuf,
uint32_t length)
{
CSL_UdmapTR15 *pTr;
uint32_t cqRingNum = Udma_chGetCqRingNum(chHandle);
/* Make TRPD with TR15 TR type */
UdmaUtils_makeTrpdTr15(trpdMem, 1U, cqRingNum);
/* Setup TR */
pTr = UdmaUtils_getTrpdTr15Pointer(trpdMem, 0U);
pTr->flags = CSL_FMK(UDMAP_TR_FLAGS_TYPE, CSL_UDMAP_TR_FLAGS_TYPE_4D_BLOCK_MOVE_REPACKING_INDIRECTION);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_STATIC, 0U);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOL, CSL_UDMAP_TR_FLAGS_EOL_MATCH_SOL_EOL);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EVENT_SIZE, CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0_TYPE, CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1_TYPE, CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_CMD_ID, 0x25U); /* This will come back in TR response */
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_SA_INDIRECT, 0U);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_DA_INDIRECT, 0U);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOP, 1U);
pTr->icnt0 = length;
pTr->icnt1 = 1U;
pTr->icnt2 = 1U;
pTr->icnt3 = 1U;
pTr->dim1 = pTr->icnt0;
pTr->dim2 = (pTr->icnt0 * pTr->icnt1);
pTr->dim3 = (pTr->icnt0 * pTr->icnt1 * pTr->icnt2);
pTr->addr = (uint64_t) Udma_defaultVirtToPhyFxn(srcBuf, 0U, NULL);
pTr->fmtflags = 0x00000000U; /* Linear addressing, 1 byte per elem */
pTr->dicnt0 = length;
pTr->dicnt1 = 1U;
pTr->dicnt2 = 1U;
pTr->dicnt3 = 1U;
pTr->ddim1 = pTr->dicnt0;
pTr->ddim2 = (pTr->dicnt0 * pTr->dicnt1);
pTr->ddim3 = (pTr->dicnt0 * pTr->dicnt1 * pTr->dicnt2);
pTr->daddr = (uint64_t) Udma_defaultVirtToPhyFxn(destBuf, 0U, NULL);
/* Perform cache writeback */
CacheP_wb(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD);
return;
}
void process_request(HDSL_Handle hdslHandle,int menu){
switch(menu)
{
case MENU_HDSL_REG_INTO_DDR:
traces_into_ddr(hdslHandle);
break;
case MENU_HDSL_REG_INTO_DDR_GPIO:
TC_input_start_copy();
break;
default:
DebugP_log( "\r\n ERROR: invalid request");
break;
}
}
void hdsl_pruss_init(void)
{
PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh0->icssCore);
/* clear ICSS0 PRU data RAM */
gPru_dramx = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_PRUx));
memset(gPru_dramx, 0, (4 * 1024));
gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase);
HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_GPCFG1, HDSL_EN);
HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, HDSL_TX_CFG);
HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1RXCFGREGISTER, HDSL_RX_CFG);
PRUICSS_intcInit(gPruIcss0Handle, &gPruss0_intc_initdata);
PRUICSS_intcInit(gPruIcss1Handle, &gPruss1_intc_initdata);
/* configure C28 to PRU_ICSS_CTRL and C29 to EDMA + 0x1000 */
/*6.4.14.1.1 ICSSG_PRU_CONTROL RegisterPRU_ICSSG0_PR1_PDSP0_IRAM 00B0 2400h*/
PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRUx, PRUICSS_CONST_TBL_ENTRY_C28, 0x0240);
/*IEP1 base */
PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRUx, PRUICSS_CONST_TBL_ENTRY_C29, 0x0002F000);
/* enable cycle counter */
HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE), CTR_EN);
}
void hdsl_pruss_init_300m(void)
{
PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh0->icssCore);
/* Clear PRU_DRAM0 and PRU_DRAM1 memory */
gPru_dramx_0 = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_RTU_PRU1));
gPru_dramx_1 = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_PRU1));
memset(gPru_dramx_0, 0, (4 * 1024));
memset(gPru_dramx_1, 0, (4 * 1024));
memset((void *) CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, 0, (16 * 1024));
memset((void *) CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE, 0, (16 * 1024));
gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase);
HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_GPCFG1, HDSL_EN);
HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, HDSL_TX_CFG);
HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1RXCFGREGISTER, HDSL_RX_CFG);
PRUICSS_intcInit(gPruIcss0Handle, &gPruss0_intc_initdata);
/* configure C28 to PRU_ICSS_CTRL and C29 to EDMA + 0x1000 */
/*6.4.14.1.1 ICSSG_PRU_CONTROL RegisterPRU_ICSSG0_PR1_PDSP0_IRAM 00B0 2400h*/
HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_PROG_PTR_0) = 0xF0000238; // Address = 0x30023828
PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C28, 0x0240);
HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_PROG_PTR_0) = 0xF0000258; // Address = 0x30025828
/*IEP1 base */
PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C29, 0x0002F000);
HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_BLOCK_INDEX_0) = 0x0000; // RTU Core
PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C24, 0x0007); // PRU Core
HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_BLOCK_INDEX_0) = 0x000E; // TX_PRU Core
/* enable cycle counter */
HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE), CTR_EN); // RTU_PRU Core
HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE), CTR_EN);
HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE), CTR_EN); // TX_PRU Core
}
void hdsl_pruss_load_run_fw(HDSL_Handle hdslHandle)
{
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000)
PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_PRUx);
if(HDSL_get_sync_ctrl(hdslHandle) == 0)
{
/*free run*/
PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(PRUICSS_PRUx),
0, (uint32_t *) Hiperface_DSL2_0_RTU_0,
sizeof(Hiperface_DSL2_0_RTU_0));
}
else
{
/*sync_mode*/
PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(PRUICSS_PRUx),
0, (uint32_t *) Hiperface_DSL_SYNC2_0_RTU_0,
sizeof(Hiperface_DSL_SYNC2_0_RTU_0));
}
PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_PRUx);
/*Run firmware*/
PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_PRUx);
#endif
}
void hdsl_pruss_load_run_fw_300m(HDSL_Handle hdslHandle)
{
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==300000000)
PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_RTU_PRU1); // ch0
PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_PRU1); // ch1
/* Enable Load Share mode */
gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase);
hdsl_enable_load_share_mode(gPru_cfg,PRUICSS_PRUx);
if(HDSL_get_sync_ctrl(hdslHandle) == 0)
{
/*free run*/
PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_RTU_PRU(1),
0, (uint32_t *) Hiperface_DSL2_0_RTU_0,
sizeof(Hiperface_DSL2_0_RTU_0));
PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(1),
0, (uint32_t *) Hiperface_DSL2_0_PRU_0,
sizeof(Hiperface_DSL2_0_PRU_0));
}
else
{
/*Sync mode*/
PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_RTU_PRU(1),
0, (uint32_t *) Hiperface_DSL_SYNC2_0_RTU_0,
sizeof(Hiperface_DSL_SYNC2_0_RTU_0));
PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(1),
0, (uint32_t *) Hiperface_DSL_SYNC2_0_PRU_0,
sizeof(Hiperface_DSL_SYNC2_0_PRU_0));
}
PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_RTU_PRU1);
PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_PRU1);
/*Run firmware*/
PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_RTU_PRU1);
PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_PRU1);
#endif
}
void hdsl_init(void)
{
uint8_t ES;
uint32_t period;
HwiP_Params hwiPrms;
uint32_t intrNum;
intrNum = HDSL_DDR_TRACE_R5F_IRQ_NUM;
hdsl_pruss_init();
/* Register PRU interrupt */
HwiP_Params_init(&hwiPrms);
hwiPrms.intNum = intrNum;
hwiPrms.callback = (void*)&HDSL_IsrFxn;
HwiP_construct(&gPRUHwiObject, &hwiPrms);
HDSL_iep_init(gHdslHandleCh0);
ClockP_usleep(5000);
if(CONFIG_HDSL0_MODE==0)
{
ES=0;
}
else
{
ES=1;
}
HDSL_set_sync_ctrl(gHdslHandleCh0, ES);
if(ES != 0)
{
DebugP_log("\r\nSYNC MODE\n");
DebugP_log("\r\nEnter period for SYNC PULSE in unit of cycles(1 cycle = 4.44ns):");
DebugP_scanf("%d",&period);
HDSL_enable_sync_signal(ES,period);
HDSL_generate_memory_image(gHdslHandleCh0);
sync_calculation(gHdslHandleCh0);
}
else
{
DebugP_log( "\r\nFREE RUN MODE\n");
HDSL_generate_memory_image(gHdslHandleCh0);
}
}
void hdsl_init_300m(void)
{
uint8_t ES;
uint32_t period;
HwiP_Params hwiPrms;
uint32_t intrNum;
intrNum = HDSL_DDR_TRACE_R5F_IRQ_NUM;
hdsl_pruss_init_300m();
/* Register PRU interrupt */
HwiP_Params_init(&hwiPrms);
hwiPrms.intNum = intrNum;
hwiPrms.callback = (void*)&HDSL_IsrFxn;
HwiP_construct(&gPRUHwiObject, &hwiPrms);
HDSL_iep_init(gHdslHandleCh0);
ClockP_usleep(5000);
if(CONFIG_HDSL0_MODE==0)
{
ES=0;
}
else
{
ES=1;
}
if (CONFIG_HDSL0_CHANNEL0==1)
{
HDSL_set_sync_ctrl(gHdslHandleCh0, ES);
}
if(ES != 0)
{
DebugP_log("\r\nSYNC MODE\n");
DebugP_log("\r\nEnter period for SYNC PULSE in unit of cycles(1 cycle = 3.33ns):");
DebugP_scanf("%d",&period);
HDSL_enable_sync_signal(ES,period);
if (CONFIG_HDSL0_CHANNEL0==1)
{
HDSL_generate_memory_image(gHdslHandleCh0);
sync_calculation(gHdslHandleCh0);
}
}
else
{
DebugP_log( "\r\nFREE RUN MODE\n");
if (CONFIG_HDSL0_CHANNEL0==1)
{
HDSL_generate_memory_image(gHdslHandleCh0);
}
}
}
static void HDSL_IsrFxn()
{
static uint64_t v_frames_count=0;
static int temp = 0;
uint8_t *srcBuf;//= (uint8_t*)gHdslInterface;
uint8_t *destBuf = (uint8_t*)&gHdslInterface_ddr[0U];
uint32_t length;// = sizeof(hdslInterface);
srcBuf = (uint8_t*)HDSL_get_src_loc(gHdslHandleCh0);
length = HDSL_get_length(gHdslHandleCh0);
PRUICSS_clearEvent(gPruIcss0Handle, HDSL_DDR_TRACE_ICSS_INTC_EVENT_NUM);
/* No of v-frames count */
v_frames_count++;
if((start_copy == 1) && (temp < ddr_trace_count))
{
/* Init buffers and TR packet descriptor */
destBuf = (uint8_t*)&gHdslInterface_ddr[temp];
/* start UDMA copying data from src to dest */
udma_copy(srcBuf,destBuf,length);
//temp_count_arr[temp] = temp_count++;
v_frames_count_arr[temp] = v_frames_count;
temp++;
}
else
{
start_copy = 0;
temp = 0;
}
}
static void display_menu(void)
{
DebugP_log("\r\n");
DebugP_log("\r\n |------------------------------------------------------------------------------|");
DebugP_log("\r\n | MENU |");
DebugP_log("\r\n |------------------------------------------------------------------------------|");
DebugP_log("\r\n | %2d : HDSL registers into DDR |", MENU_HDSL_REG_INTO_DDR);
DebugP_log("\r\n | %2d : HDSL registers into DDR using GPIO |", MENU_HDSL_REG_INTO_DDR_GPIO);
DebugP_log("\r\n |------------------------------------------------------------------------------|");
DebugP_log("\r\n Enter value: ");
}
void traces_into_ddr(HDSL_Handle hdslHandle)
{
int i= 0;
uint32_t length;
length = HDSL_get_length(hdslHandle);
DebugP_log("\r\n sizeof(hdslInterface)_count = %u", length);
DebugP_log("\r\n Start address of DDR location = %u", DDR_START_OFFSET);
DebugP_log("\r\n End address of DDR location = %u", DDR_END_OFFSET);
DebugP_log("\r\n No of HDSL-Interface-Register-Structure to copy = %u", ddr_trace_count);
start_copy = 1;
/* Testing:
* To test this input use function TC_input_start_copy()
* Connect the header pins J16 and J17 together
* J16 is used as input for copy start
* J17 is used to create high/low pulses each second
*/
while(start_copy)
{
ClockP_sleep(1);
}
for(i=0;i< ddr_trace_count; i++)
{
DebugP_log("\r\n %u .....v_frames_count = %u ",i, v_frames_count_arr[i]);
}
}
/* run this test case function to continuously make the start copy input pin high and low every 1 second */
void TC_input_start_copy()
{
int i= 0, j =0;
/* Read the value of J16 header on board */
start_copy = (uint8_t) GPIO_pinRead(CONFIG_GPIO_COPY_BASE_ADDR, CONFIG_GPIO_COPY_PIN);
while(j < 10)
{
/* Set the J17 header pin on board as LOW (Active low) */
GPIO_pinWriteLow(CONFIG_GPIO_TEST_COPY_BASE_ADDR, CONFIG_GPIO_TEST_COPY_PIN);
/* Wait for 1 second */
ClockP_sleep(1);
for(i=0;i< ddr_trace_count; i++)
{
DebugP_log("\r\n %u .....v_frames_count = %u ",(j*ddr_trace_count + i), v_frames_count_arr[i]);
}
/* Set the J17 header pin on board as HIGH */
GPIO_pinWriteHigh(CONFIG_GPIO_TEST_COPY_BASE_ADDR, CONFIG_GPIO_TEST_COPY_PIN);
/* Wait for 1 second */
ClockP_sleep(1);
j++;
}
}
static int get_menu(void)
{
unsigned int cmd;
if(DebugP_scanf("%d\n", &cmd) < 0 || cmd >= MENU_LIMIT)
{
DebugP_log("\r\n WARNING: invalid option, Safe position selected");
cmd = MENU_SAFE_POSITION;
DebugP_log( "\r\n Enter 0 :Fast Position \r\n Enter 1: Safe Position 1 \r\n Enter 2: Safe Position 2 \r");
if((DebugP_scanf("%d", &get_pos) < 0) || get_pos > 2)
{
DebugP_log("\r\n WARNING: invalid position value");
}
}
if (cmd == MENU_HDSL_REG_INTO_DDR)
{
DebugP_log("\r\n| How many traces you want to copy : ");
if(DebugP_scanf("%u\n", &ddr_trace_count) < 0 || ddr_trace_count >= NUM_RESOURCES)
{
DebugP_log("\r\n| WARNING: invalid data\n|\n|\n");
return MENU_INVALID;
}
}
if (cmd == MENU_HDSL_REG_INTO_DDR_GPIO)
{
DebugP_log("\r\n| How many traces you want to copy : ");
if(DebugP_scanf("%u\n", &ddr_trace_count) < 0 || ddr_trace_count >= NUM_RESOURCES)
{
DebugP_log("\r\n| WARNING: invalid data\n|\n|\n");
return MENU_INVALID;
}
}
return cmd;
}
#ifdef HDSL_AM64xE1_TRANSCEIVER
static void hdsl_i2c_io_expander(void *args)
{
int32_t status = SystemP_SUCCESS;
/* P20 = LED 3 bits, pin, 2 bits port.*/
uint32_t ioIndex = 0x10;
TCA6424_Params tca6424Params;
TCA6424_Params_init(&tca6424Params);
status = TCA6424_open(&gTCA6424_Config, &tca6424Params);
if(status == SystemP_SUCCESS)
{
/* Set output to HIGH before config so that LED start with On state */
status = TCA6424_setOutput(
&gTCA6424_Config,
ioIndex,
TCA6424_OUT_STATE_HIGH);
/* Configure as output */
status += TCA6424_config(
&gTCA6424_Config,
ioIndex,
TCA6424_MODE_OUTPUT);
/* set P12 high which controls CPSW_FET_SEL -> enable PRU1 and PRU0 GPIOs */
ioIndex = 0x0a;
status = TCA6424_setOutput(
&gTCA6424_Config,
ioIndex,
TCA6424_OUT_STATE_HIGH);
/* Configure as output */
status += TCA6424_config(
&gTCA6424_Config,
ioIndex,
TCA6424_MODE_OUTPUT);
}
TCA6424_close(&gTCA6424_Config);
}
#endif
void hdsl_diagnostic_main(void *arg)
{
uint32_t val, acc_bits, pos_bits;
uint8_t ureg;
int32_t retVal = UDMA_SOK, status;
/* Open drivers to open the UART driver for console */
Drivers_open();
Board_driversOpen();
/* UDMA initialization */
chHandle = gConfigUdma0BlkCopyChHandle[0]; /* Has to be done after driver open */
/* Make the J16 pin on board as input for copy start */
GPIO_setDirMode(CONFIG_GPIO_COPY_BASE_ADDR, CONFIG_GPIO_COPY_PIN, GPIO_DIRECTION_INPUT);
/* For Testing copy input: */
/* Make the J17 header pin on board as output as copy start test pin */
GPIO_setDirMode(CONFIG_GPIO_TEST_COPY_BASE_ADDR, CONFIG_GPIO_TEST_COPY_PIN, GPIO_DIRECTION_OUTPUT);
/* Channel enable */
retVal = Udma_chEnable(chHandle);
DebugP_assert(UDMA_SOK == retVal);
status = SemaphoreP_constructBinary(&gUdmaTestDoneSem, 0);
DebugP_assert(SystemP_SUCCESS == status);
#ifndef HDSL_AM64xE1_TRANSCEIVER
/* Configure g_mux_en to 1 in ICSSG_SA_MX_REG Register. This is required to remap EnDAT signals correctly via Interface card.*/
HW_WR_REG32((CSL_PRU_ICSSG0_PR1_CFG_SLV_BASE+0x40), (0x80));
/*Configure GPIO42 for HDSL mode.*/
GPIO_setDirMode(CONFIG_GPIO0_BASE_ADDR, CONFIG_GPIO0_PIN, CONFIG_GPIO0_DIR);
GPIO_pinWriteHigh(CONFIG_GPIO0_BASE_ADDR, CONFIG_GPIO0_PIN);
#else
/* Configure g_mux_en to 0 in ICSSG_SA_MX_REG Register. */
HW_WR_REG32((CSL_PRU_ICSSG0_PR1_CFG_SLV_BASE+0x40), (0x00));
/*Configure GPIO42 for HDSL mode. New transceiver card needs the pin to be configured as input*/
HW_WR_REG32(0x000F41D4, 0x00050001); /* PRG0_PRU1_GPI9 as input */
hdsl_i2c_io_expander(NULL);
#endif
DebugP_log( "\n\n Hiperface DSL diagnostic\n");
gPruIcss0Handle = PRUICSS_open(CONFIG_PRU_ICSS0);
#if (CONFIG_HDSL0_CHANNEL1==1)
DebugP_log("\r\n Channel 1 not supported in DDR Trace application");
while(1);
#endif
#if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==225000000)
gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_PRUx,0);
hdsl_init();
hdsl_pruss_load_run_fw(gHdslHandleCh0);
#else
gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_RTU_PRU1,1);
hdsl_init_300m();
hdsl_pruss_load_run_fw_300m(gHdslHandleCh0);
#endif
DebugP_log("\r\n HDSL Setup finished");
/*need some extra time for SYNC mode since frames are longer*/
hdsl_pruss_load_run_fw(gHdslHandleCh0);
#if (CONFIG_HDSL0_CHANNEL0==1)
//Channel 0 starts here:
ClockP_usleep(1000);
for (ureg = HDSL_get_master_qm(gHdslHandleCh0), val = 0; !(ureg & 0x80); ureg = HDSL_get_master_qm(gHdslHandleCh0), val++, ClockP_usleep(10))
{
if (val > 100)
{ /* wait 1ms to detect, increase if reqd. */
while(1)
{
DebugP_log( "\r\n Hiperface DSL encoder not detected\n");
ClockP_usleep(5000);
}
}
}
DebugP_log("\r\n ");
DebugP_log("\r\n |-------------------------------------------------------------------------------|");
DebugP_log("\r\n | Hiperface DSL diagnostic |");
DebugP_log("\r\n |-------------------------------------------------------------------------------|");
DebugP_log("\r\n | Quality monitoring value: %u |", ureg & 0xF);
ureg = HDSL_get_edges(gHdslHandleCh0);
DebugP_log("\r\n | Edges: 0x%x |", ureg);
ureg = HDSL_get_delay(gHdslHandleCh0);
DebugP_log("\r\n | Cable delay: %u |", ureg & 0xF);
DebugP_log("\r\n | RSSI: %u |", (ureg & 0xF0) >> 4);
val = HDSL_get_enc_id(gHdslHandleCh0, 0) | (HDSL_get_enc_id(gHdslHandleCh0, 1) << 8) | (HDSL_get_enc_id(gHdslHandleCh0, 2) << 16);
acc_bits = val & 0xF;
acc_bits += 8;
pos_bits = (val & 0x3F0) >> 4;
pos_bits += acc_bits;
DebugP_log("\r\n | Encoder ID: 0x%x", val);
DebugP_log("(");
DebugP_log("Acceleration bits: %u, ", acc_bits);
DebugP_log("Position bits: %u,", pos_bits);
DebugP_log("%s", val & 0x400 ? " Bipolar position" : " Unipolar position");
DebugP_log(")|");
DebugP_log("\r\n |-------------------------------------------------------------------------------|");
DebugP_log("\r\n Enter single turn bits: ");
if((DebugP_scanf("%d", &gRes) < 0) || gRes > pos_bits)
{
DebugP_log("\r\n WARNING: invalid single turn bits, assuming single turn encoder");
gRes = pos_bits;
}
gMulti_turn = pos_bits - gRes;
gMask = pow(2, gRes) - 1;
if (gMulti_turn)
{
DebugP_log("\r\n Multi turn bits: %u", gMulti_turn);
}
#endif
while(1)
{
int menu;
display_menu();
menu = get_menu();
if (CONFIG_HDSL0_CHANNEL0==1)
{
DebugP_log( "|\r\n Channel 0 ");
process_request(gHdslHandleCh0, menu);
DebugP_log( "\r%s", gUart_buffer);
}
}
Board_driversClose();
Drivers_close();
}

80
examples/position_sense/hdsl_diagnostic_with_traces/hdsl_diagnostic_ddr.h
View File

@ -1,80 +0,0 @@
/*
* Copyright (C) 2021-2023 Texas Instruments Incorporated
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef MENU_HDSL_REG_INTO_DDR_H_
#define MENU_HDSL_REG_INTO_DDR_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <drivers/hw_include/hw_types.h>
#define HWREG(x) \
(*((volatile uint32_t *)(x)))
#define HWREGB(x) \
(*((volatile uint8_t *)(x)))
#define HWREGH(x) \
(*((volatile uint16_t *)(x)))
/* for DDR trace*/
#define DDR_START_OFFSET 0x80000000
#define DDR_LIMIT 0x3FFFFFFF
#define DDR_END_OFFSET 0xBFFFFFF
#define NUM_RESOURCES 5000 //4210752 (0x3fff_ffff div 0xff)
/* UDMA TR packet descriptor memory size - with one TR */
#define UDMA_TEST_TRPD_SIZE (UDMA_GET_TRPD_TR15_SIZE(1U))
/* ISR for v-frame-reception */
static void HDSL_IsrFxn(void);
/*
* @brief It will test DDR traces into DDR
* \n Here user will decide how many copies of HDSL_Interface_Register
* \n will be copied into DDR
*/
void traces_into_ddr();
/*
* @brief It will test DDR traces into DDR using GPIO pins
* \ connect J17 and J16 pint on AM64x board using wire
* \n Set the J17 header pin on board as LOW (Active low)
* \n wait for 1 second and print traces on UART
* \n Set the J17 header pin on board as HIGH
*/
void TC_input_start_copy();
int HDSL_sync_calculation(void);
#ifdef __cplusplus
}
#endif
#endif

13
makefile.am243x
View File

@ -53,7 +53,6 @@ help:
@echo $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@ -180,7 +179,6 @@ BUILD_COMBO_EXAMPLE_ALL += endat_diagnostic_multi_channel_single_pru_am243x-evm_
BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang
@ -232,9 +230,6 @@ examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL)
hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang:
$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile all
hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang:
$(MAKE) -C examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all
tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all
@ -305,7 +300,6 @@ BUILD_COMBO_EXAMPLE_CLEAN_ALL += endat_diagnostic_multi_channel_single_pru_am243
BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
@ -357,9 +351,6 @@ examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL)
hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile clean
hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean
tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean
@ -430,7 +421,6 @@ BUILD_COMBO_EXAMPLE_SCRUB_ALL += endat_diagnostic_multi_channel_single_pru_am243
BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
@ -482,9 +472,6 @@ examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL)
hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub:
$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub:
$(MAKE) -C examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub

13
makefile.am64x
View File

@ -51,7 +51,6 @@ help:
@echo $(MAKE) -s -C examples/position_sense/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@echo $(MAKE) -s -C examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@ -173,7 +172,6 @@ BUILD_COMBO_EXAMPLE_ALL += endat_diagnostic_multi_channel_load_share_am64x-evm_r
BUILD_COMBO_EXAMPLE_ALL += endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang
BUILD_COMBO_EXAMPLE_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang
@ -216,9 +214,6 @@ examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL)
hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang:
$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all
hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang:
$(MAKE) -C examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all
tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all
@ -278,7 +273,6 @@ BUILD_COMBO_EXAMPLE_CLEAN_ALL += endat_diagnostic_multi_channel_load_share_am64x
BUILD_COMBO_EXAMPLE_CLEAN_ALL += endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_CLEAN_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
@ -321,9 +315,6 @@ examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL)
hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean
hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean
tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean
@ -383,7 +374,6 @@ BUILD_COMBO_EXAMPLE_SCRUB_ALL += endat_diagnostic_multi_channel_load_share_am64x
BUILD_COMBO_EXAMPLE_SCRUB_ALL += endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
BUILD_COMBO_EXAMPLE_SCRUB_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
@ -426,9 +416,6 @@ examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL)
hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub:
$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub:
$(MAKE) -C examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_scrub:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub

13
makefile_projectspec.am243x
View File

@ -14,7 +14,6 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += endat_diagnostic_multi_channel_sing
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
@ -66,9 +65,6 @@ all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL)
hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build:
$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build:
$(MAKE) -C examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
@ -140,7 +136,6 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += endat_diagnostic_multi_channel_sing
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
@ -192,9 +187,6 @@ clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL)
hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
@ -266,7 +258,6 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += endat_diagnostic_multi_channel_sin
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
@ -318,9 +309,6 @@ export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL)
hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export:
$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
hdsl_diagnostic_ddr_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export:
$(MAKE) -C examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
@ -417,7 +405,6 @@ help:
@echo $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/position_sense/hdsl_diagnostic_with_traces/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]

13
makefile_projectspec.am64x
View File

@ -12,7 +12,6 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += endat_diagnostic_multi_channel_load
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build
BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build
@ -55,9 +54,6 @@ all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL)
hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build:
$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build:
$(MAKE) -C examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_build:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
@ -118,7 +114,6 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += endat_diagnostic_multi_channel_load
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean
@ -161,9 +156,6 @@ clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL)
hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
@ -224,7 +216,6 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += endat_diagnostic_multi_channel_loa
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += endat_diagnostic_multi_channel_single_pru_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export
BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += icss_sdfm_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export
@ -267,9 +258,6 @@ export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL)
hdsl_diagnostic_single_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export:
$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
hdsl_diagnostic_ddr_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export:
$(MAKE) -C examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
tamagawa_diagnostic_multi_channel_am64x-evm_r5fss0-0_freertos_ti-arm-clang_export:
$(MAKE) -C examples/position_sense/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
@ -355,7 +343,6 @@ help:
@echo $(MAKE) -s -C examples/position_sense/endat_diagnostic/multi_channel_single_pru/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/position_sense/hdsl_diagnostic_with_traces/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@echo $(MAKE) -s -C examples/current_sense/icss_sdfm/am64x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]

4
source/position_sense/hdsl/include/hdsl_drv.h
View File

@ -103,14 +103,12 @@ enum {
MENU_RSSI,
MENU_PC_SHORT_MSG_WRITE,
MENU_PC_SHORT_MSG_READ,
MENU_PC_LONG_MSG_WRITE,
MENU_HDSL_REG_INTO_DDR,
MENU_HDSL_REG_INTO_DDR_GPIO,
MENU_DIRECT_READ_RID0_LENGTH8,
MENU_DIRECT_READ_RID81_LENGTH8,
MENU_DIRECT_READ_RID81_LENGTH2,
MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0,
MENU_INDIRECT_WRITE_RID0_LENGTH8,
MENU_HDSL_REG_INTO_MEMORY,
MENU_LIMIT,
MENU_INVALID,
};