am64x/am243x: hdsl: Add support for third channel

- Add example and firmware projects for third channel
- Update diagnostic application changes to support 3rd channel
- Add overlay based firmware build for third channel
- Update sysconfig module for third channel
- Add driver APIs for configuring copy table and channel mask
- Add IPC among cores when overlay based loading is needed for
  third channel
- Add logic to reset all channels when one channel is reset

Fixes: PINDSW-7051

Signed-off-by: Rajul Bhambay <r-bhambay@ti.com>
Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>

.metadata/.tirex/am243x.content.tirex.json

@@ -614,6 +614,39 @@
             ]
         ]
     },
+    {
+        "resourceType": "project.ccs",
+        "resourceClass": [
+            "example"
+        ],
+        "resourceSubClass": [
+            "example.general"
+        ],
+        "description": "A Hdsl Diagnostic Multi Channel Example. CPU is R5FSS0-0 running FREERTOS.",
+        "name": "hdsl_diagnostic_multi_channel",
+        "location": "../../examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec",
+        "devtools": [
+            "AM243x_LAUNCHPAD"
+        ],
+        "kernel": [
+            "freertos"
+        ],
+        "compiler": [
+            "ticlang"
+        ],
+        "subCategories": [
+            "position_sense",
+            "hdsl_diagnostic",
+            "multi_channel",
+            "r5fss0-0_freertos"
+        ],
+        "mainCategories": [
+            [
+                "Examples",
+                "Development Tools"
+            ]
+        ]
+    },
     {
         "resourceType": "project.ccs",
         "resourceClass": [

.project/device/project_am243x.js

@@ -44,8 +44,10 @@ const example_file_list = [
     "source/position_sense/hdsl/firmware/freerun_225_mhz/.project/project.js",
     "source/position_sense/hdsl/firmware/multichannel_ch0/.project/project.js",
     "source/position_sense/hdsl/firmware/multichannel_ch1/.project/project.js",
+    "source/position_sense/hdsl/firmware/multichannel_ch2/.project/project.js",
     "source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project.js",
     "source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project.js",
+    "source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/.project/project.js",
     "source/position_sense/hdsl/firmware/sync_225_mhz/.project/project.js",
     "source/position_sense/tamagawa/firmware/multi_channel/.project/project.js",
     "source/position_sense/tamagawa/firmware/single_channel/.project/project.js",

.project/device/project_am64x.js

@@ -28,8 +28,10 @@ const example_file_list = [
     "source/position_sense/hdsl/firmware/freerun_225_mhz/.project/project.js",
     "source/position_sense/hdsl/firmware/multichannel_ch0/.project/project.js",
     "source/position_sense/hdsl/firmware/multichannel_ch1/.project/project.js",
+    "source/position_sense/hdsl/firmware/multichannel_ch2/.project/project.js",
     "source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project.js",
     "source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project.js",
+    "source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/.project/project.js",
     "source/position_sense/hdsl/firmware/sync_225_mhz/.project/project.js",
     "source/position_sense/tamagawa/firmware/multi_channel/.project/project.js",
     "source/position_sense/tamagawa/firmware/single_channel/.project/project.js",

examples/position_sense/hdsl_diagnostic/hdsl_diagnostic.c

@@ -77,24 +77,27 @@
 #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==PRU_CLK_FREQ_300M)
 #include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_bin.h>
 #include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_bin.h>
+#include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_bin.h>
 #include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch0_sync_mode_bin.h>
 #include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch1_sync_mode_bin.h>
+#include <position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h>
+#endif
 
 /* ========================================================================== */
 /*                           Macros & Typedefs                                */
 /* ========================================================================== */
 
-#if (CONFIG_HDSL0_CHANNEL0 + CONFIG_HDSL0_CHANNEL1 > 1)
+#if (CONFIG_HDSL0_CHANNEL0 + CONFIG_HDSL0_CHANNEL1  + CONFIG_HDSL0_CHANNEL2 > 1)
 #define HDSL_MULTI_CHANNEL
 #endif
 
+#define TXPRU_IRAM_SIZE             (6*1024) /*6 kB*/
 #define SYNC_PULSE_WAIT_CLK_CYCLES  5505
 
 /* Divide factor for normal clock (default value for 300 MHz=31) */
 #define DIV_FACTOR_NORMAL 31
 /* Divide factor for oversampled clock (default value for 300 MHz=3) */
 #define DIV_FACTOR_OVERSAMPLED 3
-#endif
 
 #ifdef HDSL_AM64xE1_TRANSCEIVER
 #include <board/ioexp/ioexp_tca6424.h>
@@ -209,19 +212,21 @@ void traces_into_memory(HDSL_Handle hdslHandle);
 /*                            Global Variables                                */
 /* ========================================================================== */
 
-HDSL_Handle     gHdslHandleCh0;
+HDSL_Handle gHdslHandleCh[HDSL_MAX_CHANNELS];
-HDSL_Handle     gHdslHandleCh1;
 
 PRUICSS_Handle  gPruIcss0Handle;
 PRUICSS_IntcInitData gPruss0_intc_initdata = PRU_ICSS0_INTC_INITDATA;
 PRUICSS_Handle gPruIcss1Handle;
 PRUICSS_IntcInitData gPruss1_intc_initdata = PRU_ICSS1_INTC_INITDATA;
 
+HDSL_CopyTable *copyTable;
+
 static char gUart_buffer[256];
 static void *gPru_cfg;
 void *gPru_dramx;
 void *gPru_dramx_0;
 void *gPru_dramx_1;
+void *gPru_dramx_2;
 int32_t get_pos=1;
 
 uint32_t gMulti_turn, gRes;
@@ -365,8 +370,8 @@ static void HDSL_IsrFxn()
     uint8_t         *destBuf;
     uint32_t        length;
 
-    srcBuf = (uint8_t*)HDSL_get_src_loc(gHdslHandleCh0);
+    srcBuf = (uint8_t*)HDSL_get_src_loc(gHdslHandleCh[0]);
-    length = HDSL_get_length(gHdslHandleCh0);
+    length = HDSL_get_length(gHdslHandleCh[0]);
     PRUICSS_clearEvent(gPruIcss0Handle, HDSL_MEMORY_TRACE_ICSS_INTC_EVENT_NUM);
 
     /* No of h-frames count */
@@ -433,7 +438,8 @@ void sync_calculation(HDSL_Handle hdslHandle)
         uint32_t cycles_left, additional_bits, minm_cycles, time_gRest, extra_edge, extra_size, num_of_stuffing, extra_size_remainder, stuffing_remainder, bottom_up_cycles;
     #endif
     /*measure of SYNC period starts*/
-    ES =  HDSL_get_sync_ctrl(hdslHandle);
+
+    ES=HDSL_get_sync_ctrl(hdslHandle);
     volatile uint32_t* carp6_rise_addr =   (uint32_t*)(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP1_SLV_REGS_BASE + CSL_ICSS_G_PR1_IEP0_SLV_CAPR6_REG0);
     volatile uint32_t* carp6_fall_addr =   (uint32_t*)(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP1_SLV_REGS_BASE + CSL_ICSS_G_PR1_IEP0_SLV_CAPF6_REG0);
     cap6_rise0 = *(carp6_rise_addr);
@@ -676,70 +682,81 @@ void process_request(HDSL_Handle hdslHandle,int32_t menu)
 
 void hdsl_pruss_init(void)
 {
-        PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh0->icssCore);
+    PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh[0]->icssCore);
 
-        /* clear ICSS0 PRU data RAM */
+    /* clear ICSS0 PRU data RAM */
-        gPru_dramx = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_PRUx));
+    gPru_dramx = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_PRUx));
-        memset(gPru_dramx, 0, (4 * 1024));
+    memset(gPru_dramx, 0, (4 * 1024));
 
-        gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase);
+    gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase);
 
-        HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_GPCFG1, HDSL_EN);
+    HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_GPCFG1, HDSL_EN);
 
-        HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, HDSL_TX_CFG);
+    HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, HDSL_TX_CFG);
 
-        HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1RXCFGREGISTER, HDSL_RX_CFG);
+    HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1RXCFGREGISTER, HDSL_RX_CFG);
 
-        PRUICSS_intcInit(gPruIcss0Handle, &gPruss0_intc_initdata);
+    PRUICSS_intcInit(gPruIcss0Handle, &gPruss0_intc_initdata);
 
-        PRUICSS_intcInit(gPruIcss1Handle, &gPruss1_intc_initdata);
+    PRUICSS_intcInit(gPruIcss1Handle, &gPruss1_intc_initdata);
 
-        /* configure C28 to PRU_ICSS_CTRL and C29 to EDMA + 0x1000 */
+    /* configure C28 to PRU_ICSS_CTRL and C29 to EDMA + 0x1000 */
-        /*6.4.14.1.1 ICSSG_PRU_CONTROL RegisterPRU_ICSSG0_PR1_PDSP0_IRAM 00B0 2400h*/
+    /*6.4.14.1.1 ICSSG_PRU_CONTROL RegisterPRU_ICSSG0_PR1_PDSP0_IRAM 00B0 2400h*/
-        PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRUx, PRUICSS_CONST_TBL_ENTRY_C28, 0x0240);
+    PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRUx, PRUICSS_CONST_TBL_ENTRY_C28, 0x0240);
-        /*IEP1 base */
+    /*IEP1 base */
-        PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRUx, PRUICSS_CONST_TBL_ENTRY_C29, 0x0002F000);
+    PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRUx, PRUICSS_CONST_TBL_ENTRY_C29, 0x0002F000);
 
-        /* enable cycle counter */
+    /* enable cycle counter */
-        HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE), CTR_EN);
+    HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE), CTR_EN);
 }
 
 void hdsl_pruss_init_300m(void)
 {
-        PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh0->icssCore);
+#if (CONFIG_HDSL0_CHANNEL0 == 1)
-        PRUICSS_disableCore(gPruIcss0Handle, gHdslHandleCh1->icssCore);
+    PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_RTU_PRU1);    // ch0
-        /* Clear PRU_DRAM0 and PRU_DRAM1 memory */
+#endif
 
-        gPru_dramx_0 = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_RTU_PRU1));
+#if (CONFIG_HDSL0_CHANNEL1 == 1)
-        gPru_dramx_1 = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_PRU1));
+    PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_PRU1);        // ch1
-        memset(gPru_dramx_0, 0, (4 * 1024));
+#endif
-        memset(gPru_dramx_1, 0, (4 * 1024));
-        memset((void *) CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, 0, (16 * 1024));
-        memset((void *) CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE, 0, (16 * 1024));
 
-        gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase);
+#if (CONFIG_HDSL0_CHANNEL2 == 1)
+    PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_TX_PRU1);        // ch2
+#endif
+    /* Clear PRU_DRAM0 and PRU_DRAM1 memory */
 
-        HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_GPCFG1, HDSL_EN);
+    gPru_dramx_0 = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_RTU_PRU1));
-        HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, HDSL_TX_CFG);
+    gPru_dramx_1 = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_PRU1));
-        HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1RXCFGREGISTER, HDSL_RX_CFG);
+    gPru_dramx_2 = (void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + PRUICSS_DATARAM(PRUICSS_TX_PRU1));
-        PRUICSS_intcInit(gPruIcss0Handle, &gPruss0_intc_initdata);
+    memset(gPru_dramx_0, 0, (4 * 1024));
+    memset(gPru_dramx_1, 0, (4 * 1024));
+    memset(gPru_dramx_2, 0, (4 * 1024));
+    memset((void *) CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, 0, (16 * 1024));
+    memset((void *) CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE, 0, (16 * 1024));
 
-        /* configure C28 to PRU_ICSS_CTRL and C29 to EDMA + 0x1000 */
+    gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase);
-        /*6.4.14.1.1 ICSSG_PRU_CONTROL RegisterPRU_ICSSG0_PR1_PDSP0_IRAM 00B0 2400h*/
-        HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_PROG_PTR_0) = 0xF0000238; // Address = 0x30023828
-        PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C28, 0x0240);
-        HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_PROG_PTR_0) = 0xF0000258; // Address = 0x30025828
-        /*IEP1 base */
-        PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C29, 0x0002F000);
 
-        HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_BLOCK_INDEX_0) = 0x0000; // RTU Core
+    HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_GPCFG1, HDSL_EN);
-        PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C24, 0x0007);        // PRU Core
+    HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, HDSL_TX_CFG);
-        HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_BLOCK_INDEX_0) = 0x000E; // TX_PRU Core
+    HW_WR_REG32(gPru_cfg + CSL_ICSSCFG_EDPRU1RXCFGREGISTER, HDSL_RX_CFG);
+    PRUICSS_intcInit(gPruIcss0Handle, &gPruss0_intc_initdata);
 
-        /* enable cycle counter */
+    /* configure C28 to PRU_ICSS_CTRL and C29 to EDMA + 0x1000 */
-        HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE), CTR_EN);   // RTU_PRU Core
+    /*6.4.14.1.1 ICSSG_PRU_CONTROL RegisterPRU_ICSSG0_PR1_PDSP0_IRAM 00B0 2400h*/
-        HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE), CTR_EN);
+    HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_PROG_PTR_0) = 0xF0000238; // Address = 0x30023828
-        HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE), CTR_EN);        // TX_PRU Core
+    PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C28, 0x0240);
+    HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_PROG_PTR_0) = 0xF0000258; // Address = 0x30025828
+    /*IEP1 base */
+    PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C29, 0x0002F000);
+
+    HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_BLOCK_INDEX_0) = 0x0000; // RTU Core
+    PRUICSS_setConstantTblEntry(gPruIcss0Handle, PRUICSS_PRU1, PRUICSS_CONST_TBL_ENTRY_C24, 0x0007);        // PRU Core
+    HWREG(CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE + CSL_ICSS_G_PR1_PDSP0_IRAM_CONSTANT_TABLE_BLOCK_INDEX_0) = 0x000E; // TX_PRU Core
+
+    /* enable cycle counter */
+    HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_RTU1_PR1_RTU1_IRAM_REGS_BASE), CTR_EN);   // RTU_PRU Core
+    HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP1_IRAM_REGS_BASE), CTR_EN);
+    HW_WR_REG32((void *)((((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->baseAddr) + CSL_ICSS_G_PR1_PDSP_TX1_IRAM_REGS_BASE), CTR_EN);        // TX_PRU Core
 
 }
 
@@ -769,13 +786,25 @@ void hdsl_pruss_load_run_fw(HDSL_Handle hdslHandle)
 
 void hdsl_pruss_load_run_fw_300m(HDSL_Handle hdslHandle)
 {
+#if (CONFIG_HDSL0_CHANNEL2 == 1)
+    uint32_t txpruFwSize = 0;
+#endif
 #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==PRU_CLK_FREQ_300M)
-        PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_RTU_PRU1);    // ch0
+#if (CONFIG_HDSL0_CHANNEL0 == 1)
-        PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_PRU1);        // ch1
+    PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_RTU_PRU1);    // ch0
+#endif
 
-        /* Enable Load Share mode */
+#if (CONFIG_HDSL0_CHANNEL1 == 1)
-        gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase);
+    PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_PRU1);        // ch1
-        hdsl_enable_load_share_mode(gPru_cfg,PRUICSS_PRUx);
+#endif
+
+#if (CONFIG_HDSL0_CHANNEL2 == 1)
+    PRUICSS_disableCore(gPruIcss0Handle, PRUICSS_TX_PRU1);        // ch2
+#endif
+
+    /* Enable Load Share mode */
+    gPru_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcss0Handle->hwAttrs))->cfgRegBase);
+    hdsl_enable_load_share_mode(gPru_cfg,PRUICSS_PRUx);
 
     if(HDSL_get_sync_ctrl(hdslHandle) == 0)
     {
@@ -789,6 +818,31 @@ void hdsl_pruss_load_run_fw_300m(HDSL_Handle hdslHandle)
             PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(1),
                         0, (uint32_t *) Hiperface_DSL2_0_PRU_0,
                         sizeof(Hiperface_DSL2_0_PRU_0));
+#endif
+#if (CONFIG_HDSL0_CHANNEL2 == 1)
+            PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_TX_PRU(1),
+                        0, (uint32_t *) Hiperface_DSL2_0_TX_PRU_0,
+                        sizeof(Hiperface_DSL2_0_TX_PRU_0));
+
+            /*
+            NOTE: As this array is typecasted into a structure with 32-bit variables,
+            32b alignment is required. This is done using linker.
+            */
+            copyTable = (HDSL_CopyTable *)&Hiperface_DSL2_0_TX_PRU_2;
+            txpruFwSize = (copyTable->size1 > copyTable->size2)?(sizeof(Hiperface_DSL2_0_TX_PRU_0) + copyTable->size1):(sizeof(Hiperface_DSL2_0_TX_PRU_0) + copyTable->size2);
+            DebugP_assert(txpruFwSize <= TXPRU_IRAM_SIZE);
+
+            PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_DATARAM(1), 0x1500, (uint32_t *)Hiperface_DSL2_0_TX_PRU_1, copyTable->size1 + copyTable->size2);
+            if(copyTable->loadAddr1 < copyTable->loadAddr2)
+            {
+                PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_TX_PRU(1), copyTable->runAddr1, (uint32_t *) ((uint8_t *)Hiperface_DSL2_0_TX_PRU_1), copyTable->size1);
+            }
+            else
+            {
+                PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_TX_PRU(1), copyTable->runAddr1, (uint32_t *) ((uint8_t *)Hiperface_DSL2_0_TX_PRU_1 + copyTable->size2), copyTable->size1);
+            }
+
+            HDSL_config_copy_table(hdslHandle, copyTable);
 #endif
     }
     else
@@ -803,22 +857,56 @@ void hdsl_pruss_load_run_fw_300m(HDSL_Handle hdslHandle)
             PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_PRU(1),
                         0, (uint32_t *) Hiperface_DSL_SYNC2_0_PRU_0,
                         sizeof(Hiperface_DSL_SYNC2_0_PRU_0));
+#endif
+#if (CONFIG_HDSL0_CHANNEL2 == 1)
+            PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_TX_PRU(1),
+                       0, (uint32_t *) Hiperface_DSL_SYNC2_0_TX_PRU_0,
+                       sizeof(Hiperface_DSL_SYNC2_0_TX_PRU_0));
+
+            /*
+            NOTE: As this array is typecasted into a structure with 32-bit variables,
+            32b alignment is required. This is done using linker.
+            */
+            copyTable = (HDSL_CopyTable *)&Hiperface_DSL_SYNC2_0_TX_PRU_2;
+            txpruFwSize = (copyTable->size1 > copyTable->size2)?(sizeof(Hiperface_DSL_SYNC2_0_TX_PRU_0) + copyTable->size1):(sizeof(Hiperface_DSL_SYNC2_0_TX_PRU_0) + copyTable->size2);
+            DebugP_assert(txpruFwSize <= TXPRU_IRAM_SIZE);
+
+            PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_DATARAM(1), 0x1500, (uint32_t *)Hiperface_DSL_SYNC2_0_TX_PRU_1, copyTable->size1 + copyTable->size2);
+            if(copyTable->loadAddr1 < copyTable->loadAddr2)
+            {
+                PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_TX_PRU(1), copyTable->runAddr1, (uint32_t *) ((uint8_t *)Hiperface_DSL_SYNC2_0_TX_PRU_1), copyTable->size1);
+            }
+            else
+            {
+                PRUICSS_writeMemory(gPruIcss0Handle, PRUICSS_IRAM_TX_PRU(1), copyTable->runAddr1, (uint32_t *) ((uint8_t *)Hiperface_DSL_SYNC2_0_TX_PRU_1 + copyTable->size2), copyTable->size1);
+            }
+
+            HDSL_config_copy_table(hdslHandle, copyTable);
 #endif
     }
 
-        /*Run firmware*/
+
+
+
 #if (CONFIG_HDSL0_CHANNEL0 == 1)
         PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_RTU_PRU1);
 #endif
 #if (CONFIG_HDSL0_CHANNEL1 == 1)
         PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_PRU1);
 #endif
+#if (CONFIG_HDSL0_CHANNEL2 == 1)
+        PRUICSS_resetCore(gPruIcss0Handle, PRUICSS_TX_PRU1);
+#endif
+        /*Run firmware*/
 #if (CONFIG_HDSL0_CHANNEL0 == 1)
         PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_RTU_PRU1);
 #endif
 #if (CONFIG_HDSL0_CHANNEL1 == 1)
         PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_PRU1);
 #endif
+#if (CONFIG_HDSL0_CHANNEL2 == 1)
+        PRUICSS_enableCore(gPruIcss0Handle, PRUICSS_TX_PRU1);
+#endif
 #endif
 }
 
@@ -830,9 +918,9 @@ void hdsl_init(void)
     HwiP_Params     hwiPrms;
     uint32_t        intrNum = HDSL_MEMORY_TRACE_R5F_IRQ_NUM;
 #endif
-    
+
     hdsl_pruss_init();
-    
+
 #if !defined(HDSL_MULTI_CHANNEL) && defined(_DEBUG_)
     /* Register PRU interrupt */
     HwiP_Params_init(&hwiPrms);
@@ -841,7 +929,7 @@ void hdsl_init(void)
     HwiP_construct(&gPRUHwiObject, &hwiPrms);
 #endif
 
-    HDSL_iep_init(gHdslHandleCh0);
+    HDSL_iep_init(gHdslHandleCh[0]);
     ClockP_usleep(5000);
     if(CONFIG_HDSL0_MODE==0)
     {
@@ -851,26 +939,27 @@ void hdsl_init(void)
     {
         ES=1;
     }
-    HDSL_set_sync_ctrl(gHdslHandleCh0, ES);
+    HDSL_set_sync_ctrl(gHdslHandleCh[0], ES);
     if(ES != 0)
     {
         DebugP_log("\r\nSYNC MODE\n");
         DebugP_log("\r\nEnter period for SYNC PULSE in unit of cycles(1 cycle = 4.44ns):");
         DebugP_scanf("%d",&period);
         HDSL_enable_sync_signal(ES,period);
-        HDSL_generate_memory_image(gHdslHandleCh0);
+        HDSL_generate_memory_image(gHdslHandleCh[0]);
-        sync_calculation(gHdslHandleCh0);
+        sync_calculation(gHdslHandleCh[0]);
     }
     else
     {
         DebugP_log( "\r\nFREE RUN MODE\n");
-        HDSL_generate_memory_image(gHdslHandleCh0);
+        ClockP_sleep(5);
+        HDSL_generate_memory_image(gHdslHandleCh[0]);
     }
 }
 
 void hdsl_init_300m(void)
 {
-    uint8_t         ES;
+    uint8_t         ES = 0;
     uint32_t        period;
 #if !defined(HDSL_MULTI_CHANNEL) && defined(_DEBUG_)
     HwiP_Params     hwiPrms;
@@ -887,34 +976,29 @@ void hdsl_init_300m(void)
     HwiP_construct(&gPRUHwiObject, &hwiPrms);
 #endif
 
-    HDSL_iep_init(gHdslHandleCh0);
+    HDSL_iep_init(gHdslHandleCh[0]);
     ClockP_usleep(5000);
-    if(CONFIG_HDSL0_MODE==0)
+
-    {
+    if(CONFIG_HDSL0_MODE == 1)
-        ES=0;
-    }
-    else
-    {
-        ES=1;
-    }
-    if (CONFIG_HDSL0_CHANNEL0==1)
-        {
-            HDSL_set_sync_ctrl(gHdslHandleCh0, ES);
-        }
-     if (CONFIG_HDSL0_CHANNEL1==1)
-        {
-            HDSL_set_sync_ctrl(gHdslHandleCh1, ES);
-        }
-    
-    if(ES != 0)
     {
         DebugP_log("\r\nSYNC MODE\n");
-        DebugP_log("\r\nEnter ES and period for SYNC PULSE in unit of cycles(1 cycle = 3.33ns):");
+        DebugP_log("\r\nEnter ES and period for SYNC PULSE in unit of cycles(1 cycle = 3.33ns):\r\n");
         DebugP_scanf("%d",&ES);
-
-        HDSL_set_sync_ctrl(gHdslHandleCh0,ES);
-        HDSL_set_sync_ctrl(gHdslHandleCh1,ES);
         DebugP_scanf("%d",&period);
+
+        if(CONFIG_HDSL0_CHANNEL0==1)
+        {
+            HDSL_set_sync_ctrl(gHdslHandleCh[0], ES);
+        }
+        if(CONFIG_HDSL0_CHANNEL1==1)
+        {
+            HDSL_set_sync_ctrl(gHdslHandleCh[1], ES);
+        }
+        if(CONFIG_HDSL0_CHANNEL2==1)
+        {
+            HDSL_set_sync_ctrl(gHdslHandleCh[2], ES);
+        }
+
         /*  Check Sync period condition
 
         (Tsync= Cycle time for input SYNC pulse signal ,
@@ -932,25 +1016,41 @@ void hdsl_init_300m(void)
         HDSL_enable_sync_signal(ES,period);
         if (CONFIG_HDSL0_CHANNEL0==1)
         {
-            HDSL_generate_memory_image(gHdslHandleCh0);
+
-            sync_calculation(gHdslHandleCh0);
+            HDSL_generate_memory_image(gHdslHandleCh[0]);
+            sync_calculation(gHdslHandleCh[0]);
         }
         if (CONFIG_HDSL0_CHANNEL1==1)
         {
-            HDSL_generate_memory_image(gHdslHandleCh1);
+
-            sync_calculation(gHdslHandleCh1);
+            HDSL_generate_memory_image(gHdslHandleCh[1]);
+            sync_calculation(gHdslHandleCh[1]);
+        }
+        if (CONFIG_HDSL0_CHANNEL2==1)
+        {
+
+            HDSL_generate_memory_image(gHdslHandleCh[2]);
+            sync_calculation(gHdslHandleCh[2]);
         }
     }
     else
     {
         DebugP_log( "\r\nFREE RUN MODE\n");
-        if (CONFIG_HDSL0_CHANNEL0==1)
+
+        if(CONFIG_HDSL0_CHANNEL0==1)
         {
-            HDSL_generate_memory_image(gHdslHandleCh0);
+            HDSL_set_sync_ctrl(gHdslHandleCh[0], ES);
+            HDSL_generate_memory_image(gHdslHandleCh[0]);
         }
-     if (CONFIG_HDSL0_CHANNEL1==1)
+        if(CONFIG_HDSL0_CHANNEL1==1)
         {
-            HDSL_generate_memory_image(gHdslHandleCh1);
+            HDSL_set_sync_ctrl(gHdslHandleCh[1], ES);
+            HDSL_generate_memory_image(gHdslHandleCh[1]);
+        }
+        if(CONFIG_HDSL0_CHANNEL2==1)
+        {
+            HDSL_set_sync_ctrl(gHdslHandleCh[2], ES);
+            HDSL_generate_memory_image(gHdslHandleCh[2]);
         }
     }
 }
@@ -1397,6 +1497,7 @@ void hdsl_diagnostic_main(void *arg)
 {
     uint32_t    val, acc_bits, pos_bits;
     uint8_t     ureg;
+    uint8_t     chMask = 0;
 
 #if !defined(HDSL_MULTI_CHANNEL) && defined(_DEBUG_)
     int32_t     retVal = UDMA_SOK;
@@ -1414,19 +1515,26 @@ void hdsl_diagnostic_main(void *arg)
     DebugP_assert(UDMA_SOK == retVal);
 #endif
 
-/*C16 pin High for Enabling ch0 in booster pack */
+    /*C16 pin High for Enabling ch0 in booster pack */
-    #if (CONFIG_HDSL0_BOOSTER_PACK)
+    #if(CONFIG_HDSL0_BOOSTER_PACK && CONFIG_HDSL0_CHANNEL0)
-        GPIO_setDirMode(ENC1_EN_BASE_ADDR, ENC1_EN_PIN, ENC1_EN_DIR);
+        GPIO_setDirMode(ENC0_EN_BASE_ADDR, ENC0_EN_PIN, ENC0_EN_DIR);
-        GPIO_pinWriteHigh(ENC1_EN_BASE_ADDR, ENC1_EN_PIN);
+        GPIO_pinWriteHigh(ENC0_EN_BASE_ADDR, ENC0_EN_PIN);
+    #endif
+    /*B17 pin High for Enabling ch2 in booster pack */
+    #if(CONFIG_HDSL0_BOOSTER_PACK && CONFIG_HDSL0_CHANNEL2)
+        GPIO_setDirMode(ENC2_EN_BASE_ADDR, ENC2_EN_PIN, ENC2_EN_DIR);
+        GPIO_pinWriteHigh(ENC2_EN_BASE_ADDR, ENC2_EN_PIN);
     #endif
 
     #ifndef HDSL_AM64xE1_TRANSCEIVER
         /* Configure g_mux_en to 1 in ICSSG_SA_MX_REG Register. This is required to remap EnDAT signals correctly via Interface card.*/
         HW_WR_REG32((CSL_PRU_ICSSG0_PR1_CFG_SLV_BASE+0x40), (0x80));
 
+    #if (CONFIG_HDSL0_BOOSTER_PACK == 0)
         /*Configure GPIO42 for HDSL mode.*/
         GPIO_setDirMode(CONFIG_GPIO0_BASE_ADDR, CONFIG_GPIO0_PIN, CONFIG_GPIO0_DIR);
         GPIO_pinWriteHigh(CONFIG_GPIO0_BASE_ADDR, CONFIG_GPIO0_PIN);
+    #endif
     #else
         /* Configure g_mux_en to 0 in ICSSG_SA_MX_REG Register. */
         HW_WR_REG32((CSL_PRU_ICSSG0_PR1_CFG_SLV_BASE+0x40), (0x00));
@@ -1438,14 +1546,36 @@ void hdsl_diagnostic_main(void *arg)
     // initialize hdsl handle
     DebugP_log( "\n\n Hiperface DSL diagnostic\n");
     #if (CONFIG_PRU_ICSS0_CORE_CLK_FREQ_HZ==PRU_CLK_FREQ_225M)
-    gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_PRUx,0);
+    gHdslHandleCh[0] = HDSL_open(gPruIcss0Handle, PRUICSS_PRUx, 0);
     hdsl_init();
-    hdsl_pruss_load_run_fw(gHdslHandleCh0);
+    hdsl_pruss_load_run_fw(gHdslHandleCh[0]);
     #else
-    gHdslHandleCh0 = HDSL_open(gPruIcss0Handle, PRUICSS_RTU_PRU1,1);
+#if (CONFIG_HDSL0_CHANNEL0==1)
-    gHdslHandleCh1 = HDSL_open(gPruIcss0Handle, PRUICSS_PRU1,1);
+    gHdslHandleCh[0] = HDSL_open(gPruIcss0Handle, PRUICSS_RTU_PRU1, 1);
+    DebugP_assert(gHdslHandleCh[0] != NULL);
+    chMask |= CHANNEL_0_ENABLED;
+#endif
+#if (CONFIG_HDSL0_CHANNEL1==1)
+    gHdslHandleCh[1] = HDSL_open(gPruIcss0Handle, PRUICSS_PRU1, 1);
+    DebugP_assert(gHdslHandleCh[1] != NULL);
+    chMask |= CHANNEL_1_ENABLED;
+#endif
+#if (CONFIG_HDSL0_CHANNEL2==1)
+    gHdslHandleCh[2] = HDSL_open(gPruIcss0Handle, PRUICSS_TX_PRU1, 1);
+    DebugP_assert(gHdslHandleCh[2] != NULL);
+    chMask |= CHANNEL_2_ENABLED;
+#endif
     hdsl_init_300m();
-    hdsl_pruss_load_run_fw_300m(gHdslHandleCh0);
+#if (CONFIG_HDSL0_CHANNEL0==1)
+    HDSL_config_channel_mask(gHdslHandleCh[0], chMask);
+#endif
+#if (CONFIG_HDSL0_CHANNEL1==1)
+    HDSL_config_channel_mask(gHdslHandleCh[1], chMask);
+#endif
+#if (CONFIG_HDSL0_CHANNEL2==1)
+    HDSL_config_channel_mask(gHdslHandleCh[2], chMask);
+#endif
+    hdsl_pruss_load_run_fw_300m(gHdslHandleCh[0]);
     #endif
     DebugP_log( "\r\n HDSL setup finished\n");
 
@@ -1453,7 +1583,7 @@ void hdsl_diagnostic_main(void *arg)
     /* Channel 0 starts here */
     while(1)
     {
-        ureg = HDSL_get_master_qm(gHdslHandleCh0);
+        ureg = HDSL_get_master_qm(gHdslHandleCh[0]);
 
         if((ureg & QM_LINK_ESTABLISHED) != 0)
             break;
@@ -1465,7 +1595,7 @@ void hdsl_diagnostic_main(void *arg)
     /* Wait until QM is 15 */
     while(1)
     {
-        ureg = HDSL_get_master_qm(gHdslHandleCh0);
+        ureg = HDSL_get_master_qm(gHdslHandleCh[0]);
 
         if(ureg == QM_LINK_ESTABLISHED_AND_VALUE_15)
             break;
@@ -1480,13 +1610,13 @@ void hdsl_diagnostic_main(void *arg)
     DebugP_log( "\r |-------------------------------------------------------------------------------|\n");
     DebugP_log( "\r |                                                                               |\n");
     DebugP_log( "\r | Quality monitoring value: %u                                                  |\n", ureg & 0xF);
-    ureg = HDSL_get_edges(gHdslHandleCh0);
+    ureg = HDSL_get_edges(gHdslHandleCh[0]);
     DebugP_log( "\r | Edges: 0x%x                                                                    |", ureg);
-    ureg = HDSL_get_delay(gHdslHandleCh0);
+    ureg = HDSL_get_delay(gHdslHandleCh[0]);
     DebugP_log("\r\n | Cable delay: %u                                                                |", ureg & 0xF);
     DebugP_log("\r\n | RSSI: %u                                                                       |", (ureg & 0xF0) >> 4);
-    val =HDSL_get_enc_id(gHdslHandleCh0, 0) | (HDSL_get_enc_id(gHdslHandleCh0, 1) << 8) |
+    val =HDSL_get_enc_id(gHdslHandleCh[0], 0) | (HDSL_get_enc_id(gHdslHandleCh[0], 1) << 8) |
-              (HDSL_get_enc_id(gHdslHandleCh0, 2) << 16);
+              (HDSL_get_enc_id(gHdslHandleCh[0], 2) << 16);
     acc_bits = val & 0xF;
     acc_bits += 8;
     pos_bits = (val & 0x3F0) >> 4;
@@ -1497,12 +1627,12 @@ void hdsl_diagnostic_main(void *arg)
     DebugP_log( "Position bits: %u,", pos_bits);
     DebugP_log( "%s", val & 0x400 ? " Bipolar position" : " Unipolar position");
     DebugP_log(")|");
-    gHdslHandleCh0->res = read_encoder_resolution(gHdslHandleCh0);
+    gHdslHandleCh[0]->res = read_encoder_resolution(gHdslHandleCh[0]);
-    gHdslHandleCh0->multi_turn = pos_bits - gHdslHandleCh0->res;
+    gHdslHandleCh[0]->multi_turn = pos_bits - gHdslHandleCh[0]->res;
-    gHdslHandleCh0->mask = pow(2, gHdslHandleCh0->res) - 1;
+    gHdslHandleCh[0]->mask = pow(2, gHdslHandleCh[0]->res) - 1;
-    if(gHdslHandleCh0->multi_turn)
+    if(gHdslHandleCh[0]->multi_turn)
     {
-        DebugP_log( "\r\n | Single-turn bits: %u, Multi-turn bits: %u                                     |", pos_bits - gHdslHandleCh0->multi_turn, gHdslHandleCh0->multi_turn);
+        DebugP_log( "\r\n | Single-turn bits: %u, Multi-turn bits: %u                                     |", pos_bits - gHdslHandleCh[0]->multi_turn, gHdslHandleCh[0]->multi_turn);
     }
     else
     {
@@ -1517,7 +1647,7 @@ void hdsl_diagnostic_main(void *arg)
     /* Channel 1 starts here */
     while(1)
     {
-        ureg = HDSL_get_master_qm(gHdslHandleCh1);
+        ureg = HDSL_get_master_qm(gHdslHandleCh[1]);
 
         if((ureg & QM_LINK_ESTABLISHED) != 0)
             break;
@@ -1529,7 +1659,7 @@ void hdsl_diagnostic_main(void *arg)
     /* Wait until QM is 15 */
     while(1)
     {
-        ureg = HDSL_get_master_qm(gHdslHandleCh1);
+        ureg = HDSL_get_master_qm(gHdslHandleCh[1]);
 
         if(ureg == QM_LINK_ESTABLISHED_AND_VALUE_15)
             break;
@@ -1544,13 +1674,13 @@ void hdsl_diagnostic_main(void *arg)
     DebugP_log( "\r |-------------------------------------------------------------------------------|\n");
     DebugP_log( "\r |                                                                               |\n");
     DebugP_log( "\r | Quality monitoring value: %u                                                  |\n", ureg & 0xF);
-    ureg = HDSL_get_edges(gHdslHandleCh1);
+    ureg = HDSL_get_edges(gHdslHandleCh[1]);
     DebugP_log( "\r | Edges: 0x%x                                                                    |", ureg);
-    ureg = HDSL_get_delay(gHdslHandleCh1);
+    ureg = HDSL_get_delay(gHdslHandleCh[1]);
     DebugP_log("\r\n | Cable delay: %u                                                                |", ureg & 0xF);
     DebugP_log("\r\n | RSSI: %u                                                                       |", (ureg & 0xF0) >> 4);
-    val =HDSL_get_enc_id(gHdslHandleCh1, 0) | (HDSL_get_enc_id(gHdslHandleCh1, 1) << 8) |
+    val =HDSL_get_enc_id(gHdslHandleCh[1], 0) | (HDSL_get_enc_id(gHdslHandleCh[1], 1) << 8) |
-                (HDSL_get_enc_id(gHdslHandleCh1, 2) << 16);
+                (HDSL_get_enc_id(gHdslHandleCh[1], 2) << 16);
     acc_bits = val & 0xF;
     acc_bits += 8;
     pos_bits = (val & 0x3F0) >> 4;
@@ -1561,12 +1691,12 @@ void hdsl_diagnostic_main(void *arg)
     DebugP_log( "Position bits: %u,", pos_bits);
     DebugP_log( "%s", val & 0x400 ? " Bipolar position" : " Unipolar position");
     DebugP_log(")|");
-    gHdslHandleCh1->res = read_encoder_resolution(gHdslHandleCh1);
+    gHdslHandleCh[1]->res = read_encoder_resolution(gHdslHandleCh[1]);
-    gHdslHandleCh1->multi_turn = pos_bits - gHdslHandleCh1->res;
+    gHdslHandleCh[1]->multi_turn = pos_bits - gHdslHandleCh[1]->res;
-    gHdslHandleCh1->mask = pow(2, gHdslHandleCh1->res) - 1;
+    gHdslHandleCh[1]->mask = pow(2, gHdslHandleCh[1]->res) - 1;
-    if(gHdslHandleCh0->multi_turn)
+    if(gHdslHandleCh[1]->multi_turn)
     {
-        DebugP_log( "\r\n | Single-turn bits: %u, Multi-turn bits: %u                                     |", pos_bits - gHdslHandleCh1->multi_turn, gHdslHandleCh1->multi_turn);
+        DebugP_log( "\r\n | Single-turn bits: %u, Multi-turn bits: %u                                     |", pos_bits - gHdslHandleCh[1]->multi_turn, gHdslHandleCh[1]->multi_turn);
     }
     else
     {
@@ -1574,7 +1704,68 @@ void hdsl_diagnostic_main(void *arg)
     }
     DebugP_log("\r\n |-------------------------------------------------------------------------------|");
     #endif
+    #if (CONFIG_HDSL0_CHANNEL2==1)
 
+    /* Channel 2 starts here */
+    while(1)
+    {
+        ureg = HDSL_get_master_qm(gHdslHandleCh[2]);
+
+        if((ureg & QM_LINK_ESTABLISHED) != 0)
+            break;
+
+        DebugP_log( "\r\n Hiperface DSL encoder not detected\n");
+        ClockP_usleep(10000);
+    }
+
+    /* Wait until QM is 15 */
+    while(1)
+    {
+        ureg = HDSL_get_master_qm(gHdslHandleCh[2]);
+
+        if(ureg == QM_LINK_ESTABLISHED_AND_VALUE_15)
+            break;
+
+        DebugP_log( "\r\n QM is not 15 \n");
+        ClockP_usleep(10000);
+    }
+
+    DebugP_log( "\r\n");
+    DebugP_log( "\r |-------------------------------------------------------------------------------|\n");
+    DebugP_log( "\r |            Hiperface DSL Diagnostic : Channel 2                               |\n");
+    DebugP_log( "\r |-------------------------------------------------------------------------------|\n");
+    DebugP_log( "\r |                                                                               |\n");
+    DebugP_log( "\r | Quality monitoring value: %u                                                  |\n", ureg & 0xF);
+    ureg = HDSL_get_edges(gHdslHandleCh[2]);
+    DebugP_log( "\r | Edges: 0x%x                                                                    |", ureg);
+    ureg = HDSL_get_delay(gHdslHandleCh[2]);
+    DebugP_log("\r\n | Cable delay: %u                                                                |", ureg & 0xF);
+    DebugP_log("\r\n | RSSI: %u                                                                       |", (ureg & 0xF0) >> 4);
+    val =HDSL_get_enc_id(gHdslHandleCh[2], 0) | (HDSL_get_enc_id(gHdslHandleCh[2], 1) << 8) |
+                (HDSL_get_enc_id(gHdslHandleCh[2], 2) << 16);
+    acc_bits = val & 0xF;
+    acc_bits += 8;
+    pos_bits = (val & 0x3F0) >> 4;
+    pos_bits += acc_bits;
+    DebugP_log("\r\n | Encoder ID: 0x%x", val);
+    DebugP_log( "(");
+    DebugP_log( "Acceleration bits: %u, ", acc_bits);
+    DebugP_log( "Position bits: %u,", pos_bits);
+    DebugP_log( "%s", val & 0x400 ? " Bipolar position" : " Unipolar position");
+    DebugP_log(")|");
+    gHdslHandleCh[2]->res = read_encoder_resolution(gHdslHandleCh[2]);
+    gHdslHandleCh[2]->multi_turn = pos_bits - gHdslHandleCh[2]->res;
+    gHdslHandleCh[2]->mask = pow(2, gHdslHandleCh[2]->res) - 1;
+    if(gHdslHandleCh[2]->multi_turn)
+    {
+        DebugP_log( "\r\n | Single-turn bits: %u, Multi-turn bits: %u                                     |", pos_bits - gHdslHandleCh[2]->multi_turn, gHdslHandleCh[2]->multi_turn);
+    }
+    else
+    {
+        DebugP_log( "\r\n | Single-turn bits: %u                                                          |", pos_bits);
+    }
+    DebugP_log("\r\n |-------------------------------------------------------------------------------|");
+    #endif
     while(1)
     {
         int32_t menu;
@@ -1583,16 +1774,22 @@ void hdsl_diagnostic_main(void *arg)
         if (CONFIG_HDSL0_CHANNEL0==1)
         {
             DebugP_log( "|\r\n Channel 0 ");
-            process_request(gHdslHandleCh0, menu);
+            process_request(gHdslHandleCh[0], menu);
             DebugP_log( "\r%s", gUart_buffer);
         }
 
         if (CONFIG_HDSL0_CHANNEL1==1)
         {
             DebugP_log( "|\r\n Channel 1");
-            process_request(gHdslHandleCh1, menu);
+            process_request(gHdslHandleCh[1], menu);
             DebugP_log( "\r%s", gUart_buffer);
         }
+        if (CONFIG_HDSL0_CHANNEL2==1)
+        {
+           DebugP_log( "|\r\n Channel 2");
+           process_request(gHdslHandleCh[2], menu);
+           DebugP_log( "\r%s", gUart_buffer);
+        }
     }
     Board_driversClose();
     Drivers_close();

examples/position_sense/hdsl_diagnostic/multi_channel/.project/project_am243x.js

@@ -77,6 +77,7 @@ const templates_freertos_r5f =
 
 const buildOptionCombos = [
     { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-evm", os: "freertos"},
+    { device: device, cpu: "r5fss0-0", cgt: "ti-arm-clang", board: "am243x-lp", os: "freertos"},
 ];
 
 function getComponentProperty() {

examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/example.syscfg

@@ -45,6 +45,11 @@ debug_log.enableCssLog         = false;
 debug_log.uartLog.$name        = "CONFIG_UART0";
 debug_log.uartLog.UART.$assign = "USART0";
 
+const uart_v0_template  = scripting.addModule("/drivers/uart/v0/uart_v0_template", {}, false);
+const uart_v0_template1 = uart_v0_template.addInstance({}, false);
+uart_v0_template1.$name = "drivers_uart_v0_uart_v0_template0";
+debug_log.uartLog.child = uart_v0_template1;
+
 mpu_armv71.$name             = "CONFIG_MPU_REGION0";
 mpu_armv71.size              = 31;
 mpu_armv71.attributes        = "Device";
@@ -77,6 +82,7 @@ mpu_armv76.size     = 31;
 hdsl1.$name                  = "CONFIG_HDSL0";
 hdsl1.coreClk                = 300000000;
 hdsl1.channel_1              = true;
+hdsl1.channel_2              = true;
 hdsl1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1";
 
 const pruicss2                           = pruicss.addInstance({}, false);
@@ -102,3 +108,7 @@ hdsl1.PRU_ICSSG0_PRU.GPO5.$suggestSolution  = "PRG0_PRU1_GPO5";
 hdsl1.PRU_ICSSG0_PRU.GPO4.$suggestSolution  = "PRG0_PRU1_GPO4";
 hdsl1.PRU_ICSSG0_PRU.GPO3.$suggestSolution  = "PRG0_PRU1_GPO3";
 hdsl1.PRU_ICSSG0_PRU.GPI14.$suggestSolution = "PRG0_PRU1_GPO14";
+hdsl1.PRU_ICSSG0_PRU.GPO8.$suggestSolution  = "PRG0_PRU1_GPO8";
+hdsl1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12";
+hdsl1.PRU_ICSSG0_PRU.GPO6.$suggestSolution  = "PRG0_PRU1_GPO6";
+hdsl1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11";

examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd

@@ -105,6 +105,12 @@ SECTIONS
     .bss.ipc_vring_mem   (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
     /* General purpose non cacheable memory, used in some examples */
     .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
+
+    /*
+    As this array is typecasted into a structure with 32-bit variables,
+    32b alignment is required
+    */
+	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
 }
 
 /*

examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/example.syscfg

@@ -0,0 +1,112 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM243x_ALX_beta" --package "ALX" --part "ALX" --context "r5fss0-0" --product "MOTOR_CONTROL_SDK@09.01.00"
+ * @versions {"tool":"1.18.0+3266"}
+ */
+
+/**
+ * Import the modules used in this configuration.
+ */
+const i2c        = scripting.addModule("/drivers/i2c/i2c", {}, false);
+const i2c1       = i2c.addInstance();
+const pruicss    = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
+const pruicss1   = pruicss.addInstance();
+const udma       = scripting.addModule("/drivers/udma/udma", {}, false);
+const udma1      = udma.addInstance();
+const debug_log  = scripting.addModule("/kernel/dpl/debug_log");
+const mpu_armv7  = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
+const mpu_armv71 = mpu_armv7.addInstance();
+const mpu_armv72 = mpu_armv7.addInstance();
+const mpu_armv73 = mpu_armv7.addInstance();
+const mpu_armv74 = mpu_armv7.addInstance();
+const mpu_armv75 = mpu_armv7.addInstance();
+const hdsl       = scripting.addModule("/position_sense/hdsl", {}, false);
+const hdsl1      = hdsl.addInstance();
+
+/**
+ * Write custom configuration values to the imported modules.
+ */
+i2c1.$name       = "CONFIG_I2C0";
+i2c1.I2C.$assign = "I2C1";
+
+pruicss1.$name                           = "CONFIG_PRU_ICSS1";
+pruicss1.instance                        = "ICSSG1";
+pruicss1.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO1";
+
+udma1.$name                                     = "CONFIG_UDMA0";
+udma1.udmaBlkCopyChannel.create(1);
+udma1.udmaBlkCopyChannel[0].$name               = "CONFIG_UDMA_BLKCOPY_CH0";
+udma1.udmaBlkCopyChannel[0].transferCallbackFxn = "App_udmaEventCb";
+
+debug_log.enableUartLog        = true;
+debug_log.enableCssLog         = false;
+debug_log.uartLog.$name        = "CONFIG_UART_CONSOLE";
+debug_log.uartLog.UART.$assign = "USART0";
+
+const uart_v0_template  = scripting.addModule("/drivers/uart/v0/uart_v0_template", {}, false);
+const uart_v0_template1 = uart_v0_template.addInstance({}, false);
+uart_v0_template1.$name = "drivers_uart_v0_uart_v0_template0";
+debug_log.uartLog.child = uart_v0_template1;
+
+mpu_armv71.$name             = "CONFIG_MPU_REGION0";
+mpu_armv71.size              = 31;
+mpu_armv71.attributes        = "Device";
+mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv71.allowExecute      = false;
+
+mpu_armv72.$name             = "CONFIG_MPU_REGION1";
+mpu_armv72.size              = 15;
+mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv73.$name             = "CONFIG_MPU_REGION2";
+mpu_armv73.baseAddr          = 0x41010000;
+mpu_armv73.size              = 15;
+mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";
+
+mpu_armv74.$name             = "CONFIG_MPU_REGION3";
+mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
+mpu_armv74.baseAddr          = 0x70000000;
+mpu_armv74.size              = 21;
+
+mpu_armv75.$name             = "CONFIG_MPU_REGION4";
+mpu_armv75.baseAddr          = 0x60000000;
+mpu_armv75.size              = 28;
+mpu_armv75.accessPermissions = "Supervisor RD, User RD";
+
+hdsl1.$name                        = "CONFIG_HDSL0";
+hdsl1.coreClk                      = 300000000;
+hdsl1.Booster_Pack                 = true;
+hdsl1.channel_2                    = true;
+hdsl1.PRU_ICSSG0_PRU.$assign       = "PRU_ICSSG0_PRU1";
+hdsl1.ENC0_EN.$name                = "ENC0_EN";
+hdsl1.ENC0_EN.GPIO.gpioPin.rx      = false;
+hdsl1.ENC0_EN.GPIO.gpioPin.$assign = "MMC1_SDWP";
+hdsl1.ENC2_EN.$name                = "ENC2_EN";
+hdsl1.ENC2_EN.GPIO.gpioPin.rx      = false;
+hdsl1.ENC2_EN.GPIO.gpioPin.$assign = "MMC1_SDCD";
+
+const pruicss2                           = pruicss.addInstance({}, false);
+pruicss2.$name                           = "CONFIG_PRU_ICSS0";
+hdsl1.pru                                = pruicss2;
+pruicss2.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
+
+/**
+ * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
+ * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
+ * re-solve from scratch.
+ */
+i2c1.I2C.SCL.$suggestSolution               = "I2C1_SCL";
+i2c1.I2C.SDA.$suggestSolution               = "I2C1_SDA";
+debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD";
+debug_log.uartLog.UART.TXD.$suggestSolution = "UART0_TXD";
+hdsl1.PRU_ICSSG0_PRU.GPO2.$suggestSolution  = "PRG0_PRU1_GPO2";
+hdsl1.PRU_ICSSG0_PRU.GPO1.$suggestSolution  = "PRG0_PRU1_GPO1";
+hdsl1.PRU_ICSSG0_PRU.GPO0.$suggestSolution  = "PRG0_PRU1_GPO0";
+hdsl1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13";
+hdsl1.PRU_ICSSG0_PRU.GPO8.$suggestSolution  = "PRG0_PRU1_GPO8";
+hdsl1.PRU_ICSSG0_PRU.GPO12.$suggestSolution = "PRG0_PRU1_GPO12";
+hdsl1.PRU_ICSSG0_PRU.GPO6.$suggestSolution  = "PRG0_PRU1_GPO6";
+hdsl1.PRU_ICSSG0_PRU.GPI11.$suggestSolution = "PRG0_PRU1_GPO11";
+hdsl1.ENC0_EN.GPIO.$suggestSolution         = "GPIO1";
+hdsl1.ENC2_EN.GPIO.$suggestSolution         = "GPIO1";

examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/main.c

@@ -0,0 +1,84 @@
+/*
+ *  Copyright (C) 2018-2021 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdlib.h>
+#include <kernel/dpl/DebugP.h>
+#include "ti_drivers_config.h"
+#include "ti_board_config.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define MAIN_TASK_PRI  (configMAX_PRIORITIES-1)
+
+#define MAIN_TASK_SIZE (16384U/sizeof(configSTACK_DEPTH_TYPE))
+StackType_t gMainTaskStack[MAIN_TASK_SIZE] __attribute__((aligned(32)));
+
+StaticTask_t gMainTaskObj;
+TaskHandle_t gMainTask;
+
+void hdsl_diagnostic_main(void *args);
+
+void freertos_main(void *args)
+{
+    hdsl_diagnostic_main(NULL);
+
+    vTaskDelete(NULL);
+}
+
+
+int main(void)
+{
+    /* init SOC specific modules */
+    System_init();
+    Board_init();
+
+    /* This task is created at highest priority, it should create more tasks and then delete itself */
+    gMainTask = xTaskCreateStatic( freertos_main,   /* Pointer to the function that implements the task. */
+                                  "freertos_main", /* Text name for the task.  This is to facilitate debugging only. */
+                                  MAIN_TASK_SIZE,  /* Stack depth in units of StackType_t typically uint32_t on 32b CPUs */
+                                  NULL,            /* We are not using the task parameter. */
+                                  MAIN_TASK_PRI,   /* task priority, 0 is lowest priority, configMAX_PRIORITIES-1 is highest */
+                                  gMainTaskStack,  /* pointer to stack base */
+                                  &gMainTaskObj ); /* pointer to statically allocated task object memory */
+    configASSERT(gMainTask != NULL);
+
+    /* Start the scheduler to start the tasks executing. */
+    vTaskStartScheduler();
+
+    /* The following line should never be reached because vTaskStartScheduler()
+    will only return if there was not enough FreeRTOS heap memory available to
+    create the Idle and (if configured) Timer tasks.  Heap management, and
+    techniques for trapping heap exhaustion, are described in the book text. */
+    DebugP_assertNoLog(0);
+
+    return 0;
+}

examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/example.projectspec

@@ -0,0 +1,115 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectSpec>
+    <applicability>
+        <when>
+            <context
+                deviceFamily="ARM"
+                deviceId="Cortex R.AM2434_ALX"
+            />
+        </when>
+    </applicability>
+
+    <project
+        title="Hdsl Diagnostic Multi Channel"
+        name = "hdsl_diagnostic_multi_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang"
+        products="sysconfig;com.ti.MOTOR_CONTROL_SDK_AMXXX;"
+        configurations="
+                Release,
+                Debug,
+        "
+        connection="TIXDS110_Connection.xml"
+        toolChain="TICLANG"
+        cgtVersion="3.2.0"
+        device="Cortex R.AM2434_ALX"
+        deviceCore="MAIN_PULSAR_Cortex_R5_0_0"
+        ignoreDefaultDeviceSettings="true"
+        ignoreDefaultCCSSettings="true"
+        endianness="little"
+        outputFormat="ELF"
+        outputType="executable"
+
+        compilerBuildOptions="
+            -I${CG_TOOL_ROOT}/include/c
+            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source
+            -I${MOTOR_CONTROL_SDK_PATH}/source
+            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include
+            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F
+            -I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f
+            -mcpu=cortex-r5
+            -mfloat-abi=hard
+            -mfpu=vfpv3-d16
+            -mthumb
+            -Wall
+            -Werror
+            -g
+            -Wno-gnu-variable-sized-type-not-at-end
+            -Wno-unused-function
+            -DSOC_AM243X
+        "
+        linkerBuildOptions="
+            -i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib
+            -i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib
+            -i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib
+            -i${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/lib
+            -i${CG_TOOL_ROOT}/lib
+            -m=hdsl_diagnostic_multi_channel.${ConfigName}.map
+            --diag_suppress=10063
+            --ram_model
+            --reread_libs
+        "
+
+        postBuildStep="$(MAKE) -C ${CCS_PROJECT_DIR} -f makefile_ccs_bootimage_gen OUTNAME=${BuildArtifactFileBaseName} PROFILE=${ConfigName} MOTOR_CONTROL_SDK_PATH=${MOTOR_CONTROL_SDK_PATH} CG_TOOL_ROOT=${CG_TOOL_ROOT} CCS_INSTALL_DIR=${CCS_INSTALL_DIR} CCS_IDE_MODE=${CCS_IDE_MODE} DEVICE=am243x"
+
+        enableSysConfigTool="true"
+        sysConfigBuildOptions="
+            --context r5fss0-0 --part ALX --package ALX
+        "
+
+        description="A Hdsl Diagnostic Multi Channel FREERTOS project">
+
+        <configuration name="Release"
+            compilerBuildOptions="
+                -Os
+            "
+            linkerBuildOptions="
+                -lfreertos.am243x.r5f.ti-arm-clang.release.lib
+                -ldrivers.am243x.r5f.ti-arm-clang.release.lib
+                -lboard.am243x.r5f.ti-arm-clang.release.lib
+                -lmotorcontrol_hdsl.am243x.r5f.ti-arm-clang.release.lib
+                -llibc.a
+                -llibsysbm.a
+            "
+        ></configuration>
+        <configuration name="Debug"
+            compilerBuildOptions="
+                -D_DEBUG_=1
+            "
+            linkerBuildOptions="
+                -lfreertos.am243x.r5f.ti-arm-clang.debug.lib
+                -ldrivers.am243x.r5f.ti-arm-clang.debug.lib
+                -lboard.am243x.r5f.ti-arm-clang.debug.lib
+                -lmotorcontrol_hdsl.am243x.r5f.ti-arm-clang.debug.lib
+                -llibc.a
+                -llibsysbm.a
+            "
+        ></configuration>
+        <pathVariable name="MOTOR_CONTROL_SDK_PATH" path="${COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR}" scope="project" />
+        <file path="../../../../hdsl_diagnostic.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../main.c" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="linker.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../example.syscfg" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am243x/EXAMPLE_MOTORCONTROL_HDSL.html"
+                openOnCreation="false" excludeFromBuild="false" targetName="README.html" action="link">
+        </file>
+        <file path="../../../../hdsl_diagnostic.h" openOnCreation="false" excludeFromBuild="true" action="copy">
+        </file>
+        <file path="syscfg_c.rov.xs" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="makefile_ccs_bootimage_gen" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+    </project>
+</projectSpec>

examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd

@@ -0,0 +1,156 @@
+
+/* This is the stack that is used by code running within main()
+ * In case of NORTOS,
+ * - This means all the code outside of ISR uses this stack
+ * In case of FreeRTOS
+ * - This means all the code until vTaskStartScheduler() is called in main()
+ *   uses this stack.
+ * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
+ */
+--stack_size=16384
+/* This is the heap size for malloc() API in NORTOS and FreeRTOS
+ * This is also the heap used by pvPortMalloc in FreeRTOS
+ */
+--heap_size=32768
+-e_vectors  /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */
+
+/* This is the size of stack when R5 is in IRQ mode
+ * In NORTOS,
+ * - Here interrupt nesting is enabled
+ * - This is the stack used by ISRs registered as type IRQ
+ * In FreeRTOS,
+ * - Here interrupt nesting is disabled
+ * - This is stack that is used initally when a IRQ is received
+ * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
+ * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
+ */
+__IRQ_STACK_SIZE = 256;
+/* This is the size of stack when R5 is in IRQ mode
+ * - In both NORTOS and FreeRTOS nesting is disabled for FIQ
+ */
+__FIQ_STACK_SIZE = 256;
+__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
+__ABORT_STACK_SIZE = 256;  /* This is the size of stack when R5 is in ABORT mode */
+__UNDEFINED_STACK_SIZE = 256;  /* This is the size of stack when R5 is in UNDEF mode */
+
+/* section identifier
+*/
+SECTIONS
+{
+    /* This has the R5F entry point and vector table, this MUST be at 0x0 */
+    .vectors:{} palign(8) > R5F_VECS
+
+    /* This has the R5F boot code until MPU is enabled,  this MUST be at a address < 0x80000000
+     * i.e this cannot be placed in DDR
+     */
+    GROUP {
+        .text.hwi: palign(8)
+        .text.cache: palign(8)
+        .text.mpu: palign(8)
+        .text.boot: palign(8)
+        .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
+    } > MSRAM
+
+    /* This is rest of code. This can be placed in DDR if DDR is available and needed */
+    GROUP {
+        .text:   {} palign(8)   /* This is where code resides */
+        .rodata: {} palign(8)   /* This is where const's go */
+    } > MSRAM
+
+    /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
+    GROUP {
+        .data:   {} palign(8)   /* This is where initialized globals and static go */
+    } > MSRAM
+
+    /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
+    GROUP {
+        .bss:    {} palign(8)   /* This is where uninitialized globals go */
+        RUN_START(__BSS_START)
+        RUN_END(__BSS_END)
+        .sysmem: {} palign(8)   /* This is where the malloc heap goes */
+        .stack:  {} palign(8)   /* This is where the main() stack goes */
+    } > MSRAM
+
+    /* This is where the stacks for different R5F modes go */
+    GROUP {
+        .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
+        RUN_START(__IRQ_STACK_START)
+        RUN_END(__IRQ_STACK_END)
+        .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
+        RUN_START(__FIQ_STACK_START)
+        RUN_END(__FIQ_STACK_END)
+        .svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
+        RUN_START(__SVC_STACK_START)
+        RUN_END(__SVC_STACK_END)
+        .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
+        RUN_START(__ABORT_STACK_START)
+        RUN_END(__ABORT_STACK_END)
+        .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
+        RUN_START(__UNDEFINED_STACK_START)
+        RUN_END(__UNDEFINED_STACK_END)
+    } > MSRAM
+
+    /* Sections needed for C++ projects */
+    GROUP {
+        .ARM.exidx:  {} palign(8)   /* Needed for C++ exception handling */
+        .init_array: {} palign(8)   /* Contains function pointers called before main */
+        .fini_array: {} palign(8)   /* Contains function pointers called after main */
+    } > MSRAM
+
+    /* General purpose user shared memory, used in some examples */
+    .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
+    /* this is used when Debug log's to shared memory are enabled, else this is not used */
+    .bss.log_shared_mem  (NOLOAD) : {} > LOG_SHM_MEM
+    /* this is used only when IPC RPMessage is enabled, else this is not used */
+    .bss.ipc_vring_mem   (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
+    /* General purpose non cacheable memory, used in some examples */
+    .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
+
+    /*
+    As this array is typecasted into a structure with 32-bit variables,
+    32b alignment is required
+    */
+	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
+}
+
+/*
+NOTE: Below memory is reserved for DMSC usage
+ - During Boot till security handoff is complete
+   0x701E0000 - 0x701FFFFF (128KB)
+ - After "Security Handoff" is complete (i.e at run time)
+   0x701F4000 - 0x701FFFFF (48KB)
+
+ Security handoff is complete when this message is sent to the DMSC,
+   TISCI_MSG_SEC_HANDOVER
+
+ This should be sent once all cores are loaded and all application
+ specific firewall calls are setup.
+*/
+
+MEMORY
+{
+    R5F_VECS  : ORIGIN = 0x00000000 , LENGTH = 0x00000040
+    R5F_TCMA  : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
+    R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+
+    /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
+    NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000
+
+    /* when using multi-core application's i.e more than one R5F/M4F active, make sure
+     * this memory does not overlap with other R5F's
+     */
+    MSRAM     : ORIGIN = 0x70080000 , LENGTH = 0x00150000
+
+    /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
+     * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
+     */
+    FLASH     : ORIGIN = 0x60100000 , LENGTH = 0x80000
+
+    /* shared memory segments */
+    /* On R5F,
+     * - make sure there is a MPU entry which maps below regions as non-cache
+     */
+    USER_SHM_MEM            : ORIGIN = 0x701D0000, LENGTH = 0x80
+    LOG_SHM_MEM             : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
+    RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
+}

examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile

@@ -0,0 +1,308 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+include $(MOTOR_CONTROL_SDK_PATH)/devconfig/devconfig.mak
+
+CG_TOOL_ROOT=$(CGT_TI_ARM_CLANG_PATH)
+
+CC=$(CG_TOOL_ROOT)/bin/tiarmclang
+LNK=$(CG_TOOL_ROOT)/bin/tiarmclang
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+	PYTHON=python
+else
+	PYTHON=python3
+endif
+
+PROFILE?=release
+ConfigName:=$(PROFILE)
+
+OUTNAME:=hdsl_diagnostic_multi_channel.$(PROFILE).out
+
+BOOTIMAGE_PATH=$(abspath .)
+BOOTIMAGE_NAME:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage
+BOOTIMAGE_NAME_XIP:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage.signed
+BOOTIMAGE_RPRC_NAME:=hdsl_diagnostic_multi_channel.$(PROFILE).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=hdsl_diagnostic_multi_channel.$(PROFILE).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=hdsl_diagnostic_multi_channel.$(PROFILE).rprc_tmp
+BOOTIMAGE_NAME_HS:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage.hs
+BOOTIMAGE_NAME_HS_FS:=hdsl_diagnostic_multi_channel.$(PROFILE).appimage.hs_fs
+TARGETS := $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+   TARGETS += $(BOOTIMAGE_NAME_HS)
+endif
+
+FILES_common := \
+	hdsl_diagnostic.c \
+	main.c \
+	ti_drivers_config.c \
+	ti_drivers_open_close.c \
+	ti_board_config.c \
+	ti_board_open_close.c \
+	ti_dpl_config.c \
+	ti_pinmux_config.c \
+	ti_power_clock_config.c \
+
+FILES_PATH_common = \
+	.. \
+	../../.. \
+	../../../.. \
+	generated \
+
+INCLUDES_common := \
+	-I${CG_TOOL_ROOT}/include/c \
+	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source \
+	-I${MOTOR_CONTROL_SDK_PATH}/source \
+	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/FreeRTOS-Kernel/include \
+	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/portable/TI_ARM_CLANG/ARM_CR5F \
+	-I${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/config/am243x/r5f \
+	-Igenerated \
+
+DEFINES_common := \
+	-DSOC_AM243X \
+
+CFLAGS_common := \
+	-mcpu=cortex-r5 \
+	-mfloat-abi=hard \
+	-mfpu=vfpv3-d16 \
+	-mthumb \
+	-Wall \
+	-Werror \
+	-g \
+	-Wno-gnu-variable-sized-type-not-at-end \
+	-Wno-unused-function \
+
+CFLAGS_cpp_common := \
+	-Wno-c99-designator \
+	-Wno-extern-c-compat \
+	-Wno-c++11-narrowing \
+	-Wno-reorder-init-list \
+	-Wno-deprecated-register \
+	-Wno-writable-strings \
+	-Wno-enum-compare \
+	-Wno-reserved-user-defined-literal \
+	-Wno-unused-const-variable \
+	-x c++ \
+
+CFLAGS_debug := \
+	-D_DEBUG_=1 \
+
+CFLAGS_release := \
+	-Os \
+
+LNK_FILES_common = \
+	linker.cmd \
+
+LIBS_PATH_common = \
+	-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+	-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+	-Wl,-i${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+	-Wl,-i${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/lib \
+	-Wl,-i${CG_TOOL_ROOT}/lib \
+
+LIBS_common = \
+	-lfreertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-ldrivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-lboard.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-lmotorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	-llibc.a \
+	-llibsysbm.a \
+
+LFLAGS_common = \
+	-Wl,--diag_suppress=10063 \
+	-Wl,--ram_model \
+	-Wl,--reread_libs \
+
+
+LIBS_NAME = \
+	freertos.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	drivers.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	board.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	motorcontrol_hdsl.am243x.r5f.ti-arm-clang.${ConfigName}.lib \
+	libc.a \
+	libsysbm.a \
+
+LIBS_PATH_NAME = \
+	${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/kernel/freertos/lib \
+	${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/drivers/lib \
+	${MOTOR_CONTROL_SDK_PATH}/mcu_plus_sdk/source/board/lib \
+	${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/lib \
+	${CG_TOOL_ROOT}/lib \
+
+FILES := $(FILES_common) $(FILES_$(PROFILE))
+ASMFILES := $(ASMFILES_common) $(ASMFILES_$(PROFILE))
+FILES_PATH := $(FILES_PATH_common) $(FILES_PATH_$(PROFILE))
+CFLAGS := $(CFLAGS_common) $(CFLAGS_$(PROFILE))
+DEFINES := $(DEFINES_common) $(DEFINES_$(PROFILE))
+INCLUDES := $(INCLUDES_common) $(INCLUDE_$(PROFILE))
+LIBS := $(LIBS_common) $(LIBS_$(PROFILE))
+LIBS_PATH := $(LIBS_PATH_common) $(LIBS_PATH_$(PROFILE))
+LFLAGS := $(LFLAGS_common) $(LFLAGS_$(PROFILE))
+LNKOPTFLAGS := $(LNKOPTFLAGS_common) $(LNKOPTFLAGS_$(PROFILE))
+LNK_FILES := $(LNK_FILES_common) $(LNK_FILES_$(PROFILE))
+
+OBJDIR := obj/$(PROFILE)/
+OBJS := $(FILES:%.c=%.obj)
+OBJS += $(ASMFILES:%.S=%.obj)
+DEPS := $(FILES:%.c=%.d)
+
+vpath %.obj $(OBJDIR)
+vpath %.c $(FILES_PATH)
+vpath %.S $(FILES_PATH)
+vpath %.lib $(LIBS_PATH_NAME)
+vpath %.a $(LIBS_PATH_NAME)
+
+$(OBJDIR)/%.obj %.obj: %.c
+	@echo  Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME): $<
+	$(CC) -c $(CFLAGS) $(INCLUDES) $(DEFINES) -MMD -o $(OBJDIR)/$@ $<
+
+$(OBJDIR)/%.obj %.obj: %.S
+	@echo  Compiling: am243x:r5fss0-0:freertos:ti-arm-clang $(LIBNAME): $<
+	$(CC) -c $(CFLAGS) -o $(OBJDIR)/$@ $<
+
+all: $(TARGETS)
+
+SYSCFG_GEN_FILES=generated/ti_drivers_config.c generated/ti_drivers_config.h
+SYSCFG_GEN_FILES+=generated/ti_drivers_open_close.c generated/ti_drivers_open_close.h
+SYSCFG_GEN_FILES+=generated/ti_dpl_config.c generated/ti_dpl_config.h
+SYSCFG_GEN_FILES+=generated/ti_pinmux_config.c generated/ti_power_clock_config.c
+SYSCFG_GEN_FILES+=generated/ti_board_config.c generated/ti_board_config.h
+SYSCFG_GEN_FILES+=generated/ti_board_open_close.c generated/ti_board_open_close.h
+
+$(OUTNAME): syscfg $(SYSCFG_GEN_FILES) $(OBJS) $(LNK_FILES) $(LIBS_NAME)
+	@echo  .
+	@echo  Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ ...
+	$(LNK) $(LNKOPTFLAGS) $(LFLAGS) $(LIBS_PATH) -Wl,-m=$(basename $@).map -o $@ $(addprefix $(OBJDIR), $(OBJS)) $(LIBS) $(LNK_FILES)
+	@echo  Linking: am243x:r5fss0-0:freertos:ti-arm-clang $@ Done !!!
+	@echo  .
+
+clean:
+	@echo  Cleaning: am243x:r5fss0-0:freertos:ti-arm-clang $(OUTNAME) ...
+	$(RMDIR) $(OBJDIR)
+	$(RM) $(OUTNAME)
+	$(RM) $(BOOTIMAGE_NAME)
+	$(RM) $(BOOTIMAGE_NAME_XIP)
+	$(RM) $(BOOTIMAGE_NAME_SIGNED)
+	$(RM) $(BOOTIMAGE_NAME_HS)
+	$(RM) $(BOOTIMAGE_NAME_HS_FS)
+	$(RM) $(BOOTIMAGE_RPRC_NAME)
+	$(RM) $(BOOTIMAGE_RPRC_NAME_XIP)
+	$(RMDIR) generated/
+
+scrub:
+	@echo  Scrubing: am243x:r5fss0-0:freertos:ti-arm-clang hdsl_diagnostic_multi_channel ...
+	$(RMDIR) obj
+ifeq ($(OS),Windows_NT)
+	$(RM) \*.out
+	$(RM) \*.map
+	$(RM) \*.appimage*
+	$(RM) \*.rprc*
+	$(RM) \*.tiimage*
+	$(RM) \*.bin
+else
+	$(RM) *.out
+	$(RM) *.map
+	$(RM) *.appimage*
+	$(RM) *.rprc*
+	$(RM) *.tiimage*
+	$(RM) *.bin
+endif
+	$(RMDIR) generated
+
+$(OBJS): | $(OBJDIR)
+
+$(OBJDIR):
+	$(MKDIR) $@
+
+
+.NOTPARALLEL:
+
+.INTERMEDIATE: syscfg
+$(SYSCFG_GEN_FILES): syscfg
+
+syscfg: ../example.syscfg
+	@echo Generating SysConfig files ...
+	$(SYSCFG_NODE) $(SYSCFG_CLI_PATH)/dist/cli.js --product $(SYSCFG_SDKPRODUCT) --context r5fss0-0 --part ALX --package ALX --output generated/ ../example.syscfg
+
+syscfg-gui:
+	$(SYSCFG_NWJS) $(SYSCFG_PATH) --product $(SYSCFG_SDKPRODUCT) --device AM243x_ALX_beta --context r5fss0-0 --part ALX --package ALX --output generated/  ../example.syscfg
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+  BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+  BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CERT_KEY=$(APP_SIGNING_KEY)
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(SYSCFG_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+  XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+  XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+$(BOOTIMAGE_NAME): $(OUTNAME)
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ ...
+ifneq ($(OS),Windows_NT)
+	$(CHMOD) a+x $(XIPGEN_CMD)
+endif
+	$(OUTRPRC_CMD) $(OUTNAME) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+	$(RM) $(BOOTIMAGE_RPRC_NAME)
+	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS_FS)
+	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+	$(RM) $(BOOTIMAGE_TEMP_OUT_FILE)
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$@ Done !!!
+	@echo  .
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS_FS) Done !!!
+	@echo  .
+
+$(BOOTIMAGE_NAME_HS): $(BOOTIMAGE_NAME)
+ifeq ($(DEVICE_TYPE), HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+	@echo Boot image signing: Encryption is disabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME_HS)
+else
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME_HS)
+	$(RM) $(BOOTIMAGE_NAME)-enc
+endif
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_PATH)/$(BOOTIMAGE_NAME_HS) Done !!!
+	@echo  .
+endif
+-include $(addprefix $(OBJDIR)/, $(DEPS))

examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_ccs_bootimage_gen

@@ -0,0 +1,106 @@
+#
+# Auto generated makefile
+#
+
+# Below variables need to be defined outside this file or via command line
+# - MOTOR_CONTROL_SDK_PATH
+# - PROFILE
+# - CG_TOOL_ROOT
+# - OUTNAME
+# - CCS_INSTALL_DIR
+# - CCS_IDE_MODE
+
+CCS_PATH=$(CCS_INSTALL_DIR)
+include ${MOTOR_CONTROL_SDK_PATH}/imports.mak
+include ${MOTOR_CONTROL_SDK_PATH}/devconfig/devconfig.mak
+
+STRIP=$(CG_TOOL_ROOT)/bin/tiarmstrip
+OBJCOPY=$(CG_TOOL_ROOT)/bin/tiarmobjcopy
+ifeq ($(OS), Windows_NT)
+	PYTHON=python
+else
+	PYTHON=python3
+endif
+
+OUTFILE=$(PROFILE)/$(OUTNAME).out
+BOOTIMAGE_PATH=$(abspath ${PROFILE})
+BOOTIMAGE_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage
+BOOTIMAGE_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage_xip
+BOOTIMAGE_NAME_SIGNED:=$(BOOTIMAGE_PATH)/$(OUTNAME).appimage.signed
+BOOTIMAGE_RPRC_NAME:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc
+BOOTIMAGE_RPRC_NAME_XIP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_xip
+BOOTIMAGE_RPRC_NAME_TMP:=$(BOOTIMAGE_PATH)/$(OUTNAME).rprc_tmp
+
+#
+# Generation of boot image which can be loaded by Secondary Boot Loader (SBL)
+#
+ifeq ($(OS),Windows_NT)
+EXE_EXT=.exe
+endif
+ifeq ($(OS),Windows_NT)
+  BOOTIMAGE_CERT_GEN_CMD=powershell -executionpolicy unrestricted -command $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.ps1
+else
+  BOOTIMAGE_CERT_GEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/x509CertificateGen.sh
+endif
+BOOTIMAGE_TEMP_OUT_FILE=$(PROFILE)/temp_stdout_$(PROFILE).txt
+
+BOOTIMAGE_CORE_ID_r5fss0-0 = 4
+BOOTIMAGE_CORE_ID_r5fss0-1 = 5
+BOOTIMAGE_CORE_ID_r5fss1-0 = 6
+BOOTIMAGE_CORE_ID_r5fss1-1 = 7
+BOOTIMAGE_CORE_ID_m4fss0-0 = 14
+SBL_RUN_ADDRESS=0x70000000
+SBL_DEV_ID=55
+
+MULTI_CORE_IMAGE_GEN = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/multicoreImageGen/multicoreImageGen.js
+OUTRPRC_CMD = $(CCS_NODE) $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/out2rprc/elf2rprc.js
+APP_IMAGE_SIGN_CMD = $(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/signing/appimage_x509_cert_gen.py
+
+ifeq ($(OS),Windows_NT)
+  XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.exe
+else
+  XIPGEN_CMD=$(MOTOR_CONTROL_SDK_PATH)/mcu_plus_sdk/tools/boot/xipGen/xipGen.out
+endif
+
+MULTI_CORE_IMAGE_PARAMS = \
+	$(BOOTIMAGE_RPRC_NAME)@$(BOOTIMAGE_CORE_ID_r5fss0-0) \
+
+MULTI_CORE_IMAGE_PARAMS_XIP = \
+	$(BOOTIMAGE_RPRC_NAME_XIP)@$(BOOTIMAGE_CORE_ID_r5fss0-0)  \
+
+all:
+ifeq ($(CCS_IDE_MODE),cloud)
+#	No post build steps
+else
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME)  ...
+	$(OUTRPRC_CMD) $(OUTFILE) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(COPY) $(OUTNAME).rprc $(BOOTIMAGE_RPRC_NAME)
+	$(COPY) $(BOOTIMAGE_RPRC_NAME) $(BOOTIMAGE_RPRC_NAME_TMP)
+	$(RM) $(BOOTIMAGE_RPRC_NAME)
+	$(XIPGEN_CMD) -i $(BOOTIMAGE_RPRC_NAME_TMP) -o $(BOOTIMAGE_RPRC_NAME) -x $(BOOTIMAGE_RPRC_NAME_XIP) --flash-start-addr 0x60000000 -v > $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME) $(MULTI_CORE_IMAGE_PARAMS) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+	$(MULTI_CORE_IMAGE_GEN) --devID $(SBL_DEV_ID) --out $(BOOTIMAGE_NAME_XIP) $(MULTI_CORE_IMAGE_PARAMS_XIP) >> $(BOOTIMAGE_TEMP_OUT_FILE)
+# Sign the appimage for HS-FS using appimage signing script
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs_fs
+ifeq ($(DEVICE_TYPE),HS)
+# Sign the appimage using appimage signing script
+ifeq ($(ENC_ENABLED),no)
+	@echo Boot image signing: Encryption is disabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --output $(BOOTIMAGE_NAME).hs
+else
+	@echo Boot image signing: Encryption is enabled.
+	$(PYTHON) $(APP_IMAGE_SIGN_CMD) --bin $(BOOTIMAGE_NAME) --authtype 1 --key $(APP_SIGNING_KEY) --enc y --enckey $(APP_ENCRYPTION_KEY) --output $(BOOTIMAGE_NAME).hs
+	$(RM) $(BOOTIMAGE_NAME)-enc
+endif
+endif
+	$(RM) $(BOOTIMAGE_RPRC_NAME_TMP)
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME) Done !!!
+	@echo  .
+ifeq ($(DEVICE_TYPE),HS)
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs Done !!!
+	@echo  .
+else
+	@echo  Boot image: am243x:r5fss0-0:freertos:ti-arm-clang $(BOOTIMAGE_NAME).hs_fs Done !!!
+	@echo  .
+endif
+endif

examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/makefile_projectspec

@@ -0,0 +1,20 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=hdsl_diagnostic_multi_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang
+
+all:
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+	$(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full

examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/syscfg_c.rov.xs

@@ -0,0 +1,8 @@
+/*
+ *  ======== syscfg_c.rov.xs ========
+ *  This file contains the information needed by the Runtime Object
+ *  View (ROV) tool.
+ */
+var crovFiles = [
+    "mcu_plus_sdk/source/kernel/freertos/rov/FreeRTOS.rov.js",
+];

examples/position_sense/hdsl_diagnostic/multi_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd

@@ -105,6 +105,12 @@ SECTIONS
     .bss.ipc_vring_mem   (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
     /* General purpose non cacheable memory, used in some examples */
     .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
+
+    /*
+    As this array is typecasted into a structure with 32-bit variables,
+    32b alignment is required
+    */
+	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
 }
 
 /*

examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd

@@ -107,6 +107,12 @@ SECTIONS
     .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
 
 	.hdslInterface_mem (NOLOAD) > DDR
+
+    /*
+    As this array is typecasted into a structure with 32-bit variables,
+    32b alignment is required
+    */
+	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
 }
 
 /*

examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/example.syscfg

@@ -8,9 +8,6 @@
 /**
  * Import the modules used in this configuration.
  */
-const gpio       = scripting.addModule("/drivers/gpio/gpio", {}, false);
-const gpio1      = gpio.addInstance();
-const gpio2      = gpio.addInstance();
 const i2c        = scripting.addModule("/drivers/i2c/i2c", {}, false);
 const i2c1       = i2c.addInstance();
 const pruicss    = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
@@ -30,11 +27,6 @@ const hdsl1      = hdsl.addInstance();
 /**
  * Write custom configuration values to the imported modules.
  */
-gpio1.$name                = "CONFIG_GPIO0";
-gpio1.pinDir               = "OUTPUT";
-gpio1.GPIO.gpioPin.rx      = false;
-gpio1.GPIO.gpioPin.$assign = "GPMC0_AD1";
-
 i2c1.$name       = "CONFIG_I2C0";
 i2c1.I2C.$assign = "I2C1";
 
@@ -52,6 +44,11 @@ debug_log.enableCssLog         = false;
 debug_log.uartLog.$name        = "CONFIG_UART_CONSOLE";
 debug_log.uartLog.UART.$assign = "USART0";
 
+const uart_v0_template  = scripting.addModule("/drivers/uart/v0/uart_v0_template", {}, false);
+const uart_v0_template1 = uart_v0_template.addInstance({}, false);
+uart_v0_template1.$name = "drivers_uart_v0_uart_v0_template0";
+debug_log.uartLog.child = uart_v0_template1;
+
 mpu_armv71.$name             = "CONFIG_MPU_REGION0";
 mpu_armv71.size              = 31;
 mpu_armv71.attributes        = "Device";
@@ -77,16 +74,16 @@ mpu_armv75.baseAddr          = 0x60000000;
 mpu_armv75.size              = 28;
 mpu_armv75.accessPermissions = "Supervisor RD, User RD";
 
-hdsl1.$name                  = "CONFIG_HDSL0";
+hdsl1.$name                        = "CONFIG_HDSL0";
-hdsl1.Booster_Pack           = true;
+hdsl1.coreClk                      = 300000000;
-hdsl1.coreClk                = 300000000;
+hdsl1.Booster_Pack                 = true;
-hdsl1.PRU_ICSSG0_PRU.$assign = "PRU_ICSSG0_PRU1";
+hdsl1.PRU_ICSSG0_PRU.$assign       = "PRU_ICSSG0_PRU1";
-
+hdsl1.ENC0_EN.$name                = "ENC0_EN";
-hdsl1.ENC1_EN              = gpio2;
+hdsl1.ENC0_EN.GPIO.gpioPin.rx      = false;
-gpio2.$name                = "ENC1_EN";
+hdsl1.ENC0_EN.GPIO.gpioPin.$assign = "MMC1_SDWP";
-gpio2.GPIO.$assign         = "GPIO1";
+hdsl1.ENC2_EN.$name                = "ENC2_EN";
-gpio2.GPIO.gpioPin.rx      = false;
+hdsl1.ENC2_EN.GPIO.gpioPin.rx      = false;
-gpio2.GPIO.gpioPin.$assign = "MMC1_SDWP";
+hdsl1.ENC2_EN.GPIO.gpioPin.$assign = "MMC1_SDCD";
 
 const pruicss2                           = pruicss.addInstance({}, false);
 pruicss2.$name                           = "CONFIG_PRU_ICSS0";
@@ -98,7 +95,6 @@ pruicss2.AdditionalICSSSettings[0].$name = "CONFIG_PRU_ICSS_IO0";
  * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
  * re-solve from scratch.
  */
-gpio1.GPIO.$suggestSolution                 = "GPIO0";
 i2c1.I2C.SCL.$suggestSolution               = "I2C1_SCL";
 i2c1.I2C.SDA.$suggestSolution               = "I2C1_SDA";
 debug_log.uartLog.UART.RXD.$suggestSolution = "UART0_RXD";
@@ -107,3 +103,5 @@ hdsl1.PRU_ICSSG0_PRU.GPO2.$suggestSolution  = "PRG0_PRU1_GPO2";
 hdsl1.PRU_ICSSG0_PRU.GPO1.$suggestSolution  = "PRG0_PRU1_GPO1";
 hdsl1.PRU_ICSSG0_PRU.GPO0.$suggestSolution  = "PRG0_PRU1_GPO0";
 hdsl1.PRU_ICSSG0_PRU.GPI13.$suggestSolution = "PRG0_PRU1_GPO13";
+hdsl1.ENC0_EN.GPIO.$suggestSolution         = "GPIO1";
+hdsl1.ENC2_EN.GPIO.$suggestSolution         = "GPIO1";

examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang/linker.cmd

@@ -107,6 +107,12 @@ SECTIONS
     .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
 
 	.hdslInterface_mem (NOLOAD) > MSRAM
+
+    /*
+    As this array is typecasted into a structure with 32-bit variables,
+    32b alignment is required
+    */
+	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
 }
 
 /*

examples/position_sense/hdsl_diagnostic/single_channel/am64x-evm/r5fss0-0_freertos/ti-arm-clang/linker.cmd

@@ -107,6 +107,12 @@ SECTIONS
     .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
 
 	.hdslInterface_mem (NOLOAD) > DDR
+
+    /*
+    As this array is typecasted into a structure with 32-bit variables,
+    32b alignment is required
+    */
+	.rodata.Hiperface_DSL_SYNC2_0_TX_PRU_2:{} align(32) > MSRAM
 }
 
 /*

makefile.am243x

@@ -69,6 +69,7 @@ help:
 	@echo  $(MAKE) -s -C examples/position_sense/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C examples/position_sense/endat_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
+	@echo  $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang [all clean syscfg-gui syscfg]
@@ -103,8 +104,10 @@ help:
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
+	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch2/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
+	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/tamagawa/firmware/multi_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
@@ -257,6 +260,7 @@ BUILD_COMBO_EXAMPLE_ALL += endat_diagnostic_multi_channel_load_share_am243x-lp_r
 BUILD_COMBO_EXAMPLE_ALL += endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang
 BUILD_COMBO_EXAMPLE_ALL += endat_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang
 BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang
+BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_multi_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang
 BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang
 BUILD_COMBO_EXAMPLE_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang
 BUILD_COMBO_EXAMPLE_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang
@@ -295,8 +299,10 @@ BUILD_COMBO_EXAMPLE_PRIVATE_ALL += endat_peripheral_interface_multi_ch_am243x-ev
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
+BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
+BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_multi_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt
@@ -370,6 +376,9 @@ examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL)
  hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang:
 	$(MAKE) -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all
 
+ hdsl_diagnostic_multi_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang:
+	$(MAKE) -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile all
+
  hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang:
 	$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile all
 
@@ -472,12 +481,18 @@ examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL)
  hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
 
+ hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
+
  hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
 
  hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
 
+ hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
+
  hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt:
 	$(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
 
@@ -530,6 +545,7 @@ BUILD_COMBO_EXAMPLE_CLEAN_ALL += endat_diagnostic_multi_channel_load_share_am243
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += endat_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
+BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_multi_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
@@ -568,8 +584,10 @@ BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += endat_peripheral_interface_multi_ch_am2
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_multi_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_clean
@@ -643,6 +661,9 @@ examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL)
  hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
 	$(MAKE) -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean
 
+ hdsl_diagnostic_multi_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
+	$(MAKE) -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile clean
+
  hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
 	$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile clean
 
@@ -745,12 +766,18 @@ examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL)
  hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
 
+ hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
+
  hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
 
  hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
 
+ hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
+
  hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
 
@@ -803,6 +830,7 @@ BUILD_COMBO_EXAMPLE_SCRUB_ALL += endat_diagnostic_multi_channel_load_share_am243
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += endat_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
+BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_multi_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub
 BUILD_COMBO_EXAMPLE_SCRUB_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub
@@ -841,8 +869,10 @@ BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += endat_peripheral_interface_multi_ch_am2
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
+BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
+BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_multi_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_scrub
@@ -916,6 +946,9 @@ examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL)
  hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub:
 	$(MAKE) -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
 
+ hdsl_diagnostic_multi_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_scrub:
+	$(MAKE) -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
+
  hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_scrub:
 	$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile scrub
 
@@ -1018,12 +1051,18 @@ examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL)
  hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
 
+ hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
+
  hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
 
  hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
 
+ hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
+
  hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
 	$(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
 

makefile.am64x

@@ -62,8 +62,10 @@ help:
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
+	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch2/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
+	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
 	@echo  $(MAKE) -s -C source/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt [all clean syscfg-gui syscfg]
@@ -186,8 +188,10 @@ BUILD_COMBO_EXAMPLE_PRIVATE_ALL += endat_peripheral_interface_multi_ch_am64x-evm
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt
+BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt
+BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt
 BUILD_COMBO_EXAMPLE_PRIVATE_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt
@@ -245,12 +249,18 @@ examples-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_ALL)
  hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
 
+ hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
+
  hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
 
  hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
 
+ hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
+
  hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt:
 	$(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile all
 
@@ -283,8 +293,10 @@ BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += endat_peripheral_interface_multi_ch_am6
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
@@ -342,12 +354,18 @@ examples-private-clean: $(BUILD_COMBO_EXAMPLE_PRIVATE_CLEAN_ALL)
  hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
 
+ hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
+
  hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
 
  hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
 
+ hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
+
  hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile clean
 
@@ -380,8 +398,10 @@ BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += endat_peripheral_interface_multi_ch_am6
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
+BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
+BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
 BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub
@@ -439,12 +459,18 @@ examples-scrub-private: $(BUILD_COMBO_EXAMPLE_PRIVATE_SCRUB_ALL)
  hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
 
+ hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
+
  hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
 
  hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
 
+ hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
+
  hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_scrub:
 	$(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile scrub
 

makefile_projectspec.am243x

@@ -26,6 +26,7 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += endat_diagnostic_multi_channel_load
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += endat_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_multi_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build
@@ -64,8 +65,10 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += endat_peripheral_interface_
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_multi_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_build
@@ -139,6 +142,9 @@ all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL)
  hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build:
 	$(MAKE) -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
 
+ hdsl_diagnostic_multi_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_build:
+	$(MAKE) -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
+
  hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_build:
 	$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec all
 
@@ -241,12 +247,18 @@ all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL)
  hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
 
+ hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
+
  hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
 
  hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
 
+ hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
+
  hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
 	$(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
 
@@ -300,6 +312,7 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += endat_diagnostic_multi_channel_load
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += endat_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_multi_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean
@@ -338,8 +351,10 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += endat_peripheral_interface_
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_multi_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_clean
@@ -413,6 +428,9 @@ clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL)
  hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
 	$(MAKE) -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
 
+ hdsl_diagnostic_multi_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_clean:
+	$(MAKE) -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
+
  hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_clean:
 	$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec clean
 
@@ -515,12 +533,18 @@ clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL)
  hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
 
+ hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
+
  hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
 
  hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
 
+ hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
+
  hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
 
@@ -574,6 +598,7 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += endat_diagnostic_multi_channel_loa
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += endat_diagnostic_multi_channel_single_pru_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += endat_diagnostic_multi_channel_single_pru_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_multi_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += hdsl_diagnostic_single_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_ALL += tamagawa_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export
@@ -612,8 +637,10 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += endat_peripheral_interface
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_multi_channel_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_multi_channel_am243x-lp_icssg0-pru1_fw_ti-pru-cgt_export
@@ -687,6 +714,9 @@ export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL)
  hdsl_diagnostic_multi_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export:
 	$(MAKE) -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
 
+ hdsl_diagnostic_multi_channel_am243x-lp_r5fss0-0_freertos_ti-arm-clang_export:
+	$(MAKE) -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
+
  hdsl_diagnostic_single_channel_am243x-evm_r5fss0-0_freertos_ti-arm-clang_export:
 	$(MAKE) -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec export
 
@@ -789,12 +819,18 @@ export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL)
  hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
 
+ hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
+
  hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
 
  hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
 
+ hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
+
  hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
 	$(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
 
@@ -873,6 +909,7 @@ help:
 	@echo  $(MAKE) -s -C examples/position_sense/endat_diagnostic/multi_channel_single_pru/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C examples/position_sense/endat_diagnostic/multi_channel_single_pru/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
+	@echo  $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/multi_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C examples/position_sense/hdsl_diagnostic/single_channel/am243x-lp/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C examples/position_sense/tamagawa_diagnostic/multi_channel/am243x-evm/r5fss0-0_freertos/ti-arm-clang -f makefile_projectspec [export all clean]
@@ -907,8 +944,10 @@ help:
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
+	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch2/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
+	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/tamagawa/firmware/multi_channel/am243x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/tamagawa/firmware/multi_channel/am243x-lp/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]

makefile_projectspec.am64x

@@ -27,8 +27,10 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += endat_peripheral_interface_
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build
@@ -86,12 +88,18 @@ all-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_BUILD_PRIVATE_ALL)
  hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
 
+ hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
+
  hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
 
  hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
 
+ hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
+
  hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_build:
 	$(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec all
 
@@ -125,8 +133,10 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += endat_peripheral_interface_
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean
@@ -184,12 +194,18 @@ clean-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_CLEAN_PRIVATE_ALL)
  hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
 
+ hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
+
  hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
 
  hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
 
+ hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
+
  hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_clean:
 	$(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec clean
 
@@ -223,8 +239,10 @@ BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += endat_peripheral_interface
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export
+BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_multi_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export
 BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL += tamagawa_single_channel_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export
@@ -282,12 +300,18 @@ export-private: $(BUILD_COMBO_EXAMPLE_PROJECTSPEC_EXPORT_PRIVATE_ALL)
  hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
 
+ hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
+
  hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
 
  hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
 	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
 
+ hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
+	$(MAKE) -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
+
  hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_export:
 	$(MAKE) -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec export
 
@@ -342,8 +366,10 @@ help:
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
+	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch2/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
+	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/tamagawa/firmware/multi_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]
 	@echo  $(MAKE) -s -C source/position_sense/tamagawa/firmware/single_channel/am64x-evm/icssg0-pru1_fw/ti-pru-cgt -f makefile_projectspec [export all clean]

source/.meta/position_sense/hdsl.syscfg.js

@@ -8,6 +8,17 @@ function onValidate(inst, validation) {
 
     for (let instance_index in inst.$module.$instances)
     {
+        let instance = inst.$module.$instances[instance_index];
+        /* select atleast one cahnnel */
+        if ((!instance.channel_0)&&(!instance.channel_2)&&(!instance.channel_1))
+            validation.logError("Select atleast one channel",inst,"channel_0");
+
+        /* channel 0 and channel 2 are supported on am243x-lp*/
+        if((device=="am243x-lp") && (instance.channel_1))
+        {
+            validation.logError("Channel 1 is not supported on am243x-lp",inst,"channel_1");
+        }
+
         /* validation for booster pack */
         if((device!="am243x-lp")&&(instance.Booster_Pack))
         {
@@ -93,6 +104,13 @@ let hdsl_module = {
             default: false,
 
         },
+        {
+            name: "channel_2",
+            displayName: "Select Channel 2",
+            description: "Channel 2 Selection ",
+            default: false,
+
+        },
     ],
     moduleStatic: {
         modules: function(inst) {
@@ -106,8 +124,35 @@ let hdsl_module = {
     getInterfaceName: hdsl_endat_pins.getInterfaceName,
     getPeripheralPinNames: hdsl_endat_pins.getPeripheralPinNames,
     sharedModuleInstances: sharedModuleInstances,
+    moduleInstances: moduleInstances,
+    validate: onValidate,
 };
 
+function moduleInstances(instance){
+    let modInstances = new Array();
+    if(device == "am243x-lp")
+    {
+       modInstances.push({
+            name: "ENC0_EN",
+            displayName: "Booster Pack Ch0 Enable Pin",
+            moduleName: "/drivers/gpio/gpio",
+            requiredArgs: {
+                pinDir: "OUTPUT",
+
+            },
+        });
+        modInstances.push({
+            name: "ENC2_EN",
+            displayName: "Booster Pack Ch2 Enable Pin",
+            moduleName: "/drivers/gpio/gpio",
+            requiredArgs: {
+                pinDir: "OUTPUT",
+            },
+        });
+    }
+    return (modInstances);
+}
+
 function sharedModuleInstances(instance) {
     let modInstances = new Array();
 
@@ -121,18 +166,6 @@ function sharedModuleInstances(instance) {
             iepSyncMode: true,
         },
     });
-    if(device == "am243x-lp")
-    {
-       modInstances.push({
-            name: "ENC1_EN",
-            displayName: "Booster Pack Ch0 Enable Pin",
-            moduleName: "/drivers/gpio/gpio",
-            requiredArgs: {
-                pinDir: "OUTPUT"
-            },
-        });
-    }
-
     return (modInstances);
 }
 

source/.meta/position_sense/templates/hdsl_templates.h.xdt

@@ -24,5 +24,6 @@
 #define `instance.$name`                  (`i`)
 #define `instance.$name`_CHANNEL0         (`instance.channel_0 & 1`)
 #define `instance.$name`_CHANNEL1         (`instance.channel_1 & 1`)
+#define `instance.$name`_CHANNEL2         (`instance.channel_2 & 1`)
 #define `instance.$name`_MODE             (`Mode`)
 % }

source/position_sense/hdsl/driver/hdsl_drv.c

@@ -55,30 +55,39 @@
 
 #define PC_CTRL_ENABLE                  (0x01)
 
-/* Should move the below to sysconfig  generated code */
+#define PART1_LOAD_START_OFFSET		    (0x76)
-    HDSL_Config hdslConfig0;
+#define PART1_RUN_START_OFFSET		    (0x78)
-    HDSL_Config hdslConfig1;
+#define PART1_SIZE_OFFSET				(0x7A)
-    HDSL_Config hdslConfig2;
+#define PART2_LOAD_START_OFFSET		    (0x7C)
+#define PART2_RUN_START_OFFSET		    (0x7E)
+#define PART2_SIZE_OFFSET				(0x80)
 
-void hdsl_enable_load_share_mode(void *gPru_cfg ,uint32_t  PRU_SLICE)
+#define CHANNEL_MASK_OFFSET             (0x83)
+
+/* Should move the below to sysconfig  generated code */
+HDSL_Config hdslConfig0;
+HDSL_Config hdslConfig1;
+HDSL_Config hdslConfig2;
+
+void hdsl_enable_load_share_mode(void *pruCfg ,uint32_t pruSlice)
 {
-    //HW_WR_REG32(0x30026104) |= 0x0800;
+    uint32_t regVal;
-    uint32_t rgval;
+    if(pruSlice == 1)
-    if(PRU_SLICE==1)
     {
-       rgval = HW_RD_REG32((uint8_t *)gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER);
+       regVal = HW_RD_REG32((uint8_t *)pruCfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER);
-       rgval |= CSL_ICSSCFG_EDPRU1TXCFGREGISTER_PRU1_ENDAT_SHARE_EN_MASK;
+       regVal |= CSL_ICSSCFG_EDPRU1TXCFGREGISTER_PRU1_ENDAT_SHARE_EN_MASK;
-       HW_WR_REG32((uint8_t *)gPru_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, rgval);
+       HW_WR_REG32((uint8_t *)pruCfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, regVal);
     }
     else
     {
-        rgval = HW_RD_REG32((uint8_t *)gPru_cfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER);
+        regVal = HW_RD_REG32((uint8_t *)pruCfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER);
-        rgval |= CSL_ICSSCFG_EDPRU0TXCFGREGISTER_PRU0_ENDAT_SHARE_EN_MASK;
+        regVal |= CSL_ICSSCFG_EDPRU0TXCFGREGISTER_PRU0_ENDAT_SHARE_EN_MASK;
-      HW_WR_REG32((uint8_t *)gPru_cfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER, rgval);
+        HW_WR_REG32((uint8_t *)pruCfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER, regVal);
     }
 
 }
-HDSL_Handle HDSL_open(PRUICSS_Handle icssgHandle, uint32_t icssCore,uint8_t PRU_mode)
+
+HDSL_Handle HDSL_open(PRUICSS_Handle icssgHandle, uint32_t icssCore, uint8_t pruMode)
 {
     /*
         HDSL memory map:
@@ -86,11 +95,12 @@ HDSL_Handle HDSL_open(PRUICSS_Handle icssgHandle, uint32_t icssCore,uint8_t PRU_
         PRU core:       0x0700 - 0x0DFF
         TX_PRU core:    0x0E00 - 0x1500
     */
-    uint32_t DMEM_BASE_OFFSET_RTU_PRU1=0;
+    uint32_t DMEM_BASE_OFFSET_RTU_PRU1 = 0;
-    uint32_t DMEM_BASE_OFFSET_PRU1=0x700;
+    uint32_t DMEM_BASE_OFFSET_PRU1 = 0x700;
-    uint32_t DMEM_BASE_OFFSET_TX_PRU1=0xE00;
+    uint32_t DMEM_BASE_OFFSET_TX_PRU1 = 0xE00;
     HDSL_Handle hdslHandle;
-    if (PRU_mode==0)
+
+    if (pruMode == 0)
     {
         hdslHandle = &hdslConfig0;
         hdslHandle->baseMemAddr = (uint32_t *)(((PRUICSS_HwAttrs *)(icssgHandle->hwAttrs))->pru1DramBase);
@@ -100,7 +110,7 @@ HDSL_Handle HDSL_open(PRUICSS_Handle icssgHandle, uint32_t icssCore,uint8_t PRU_
         if(icssCore == PRUICSS_RTU_PRU1)
         {
             hdslHandle = &hdslConfig0;
-            hdslHandle->baseMemAddr = (uint32_t *)((((PRUICSS_HwAttrs *)(icssgHandle->hwAttrs))->pru1DramBase)+DMEM_BASE_OFFSET_RTU_PRU1);
+            hdslHandle->baseMemAddr = (uint32_t *)((((PRUICSS_HwAttrs *)(icssgHandle->hwAttrs))->pru1DramBase) + DMEM_BASE_OFFSET_RTU_PRU1);
         }
         else if(icssCore == PRUICSS_PRU1)
         {
@@ -617,3 +627,22 @@ uint32_t HDSL_get_length(HDSL_Handle hdslHandle)
     return sizeof(*(hdslHandle->hdslInterface));
 }
 
+
+int32_t HDSL_config_copy_table(HDSL_Handle hdslHandle, HDSL_CopyTable *copyTable)
+{
+
+    HW_WR_REG16((uint8_t *)hdslHandle->baseMemAddr + PART1_LOAD_START_OFFSET, (uint16_t)copyTable->loadAddr1);
+    HW_WR_REG16((uint8_t *)hdslHandle->baseMemAddr + PART1_RUN_START_OFFSET, (uint16_t)copyTable->runAddr1);
+    HW_WR_REG16((uint8_t *)hdslHandle->baseMemAddr + PART1_SIZE_OFFSET, (uint16_t)copyTable->size1);
+    HW_WR_REG16((uint8_t *)hdslHandle->baseMemAddr + PART2_LOAD_START_OFFSET, (uint16_t)copyTable->loadAddr2);
+    HW_WR_REG16((uint8_t *)hdslHandle->baseMemAddr + PART2_RUN_START_OFFSET, (uint16_t)copyTable->runAddr2);
+    HW_WR_REG16((uint8_t *)hdslHandle->baseMemAddr + PART2_SIZE_OFFSET, (uint16_t)copyTable->size2);
+
+    return SystemP_SUCCESS;
+}
+
+int32_t HDSL_config_channel_mask(HDSL_Handle hdslHandle, uint8_t channelMask)
+{
+    HW_WR_REG8((uint8_t *)hdslHandle->baseMemAddr + CHANNEL_MASK_OFFSET, channelMask);
+    return SystemP_SUCCESS;
+}

source/position_sense/hdsl/firmware/datalink.asm

@@ -34,7 +34,6 @@
 	.include "defines.inc"
 	.include "macros.inc"
 	;.sect	".text"
-	.ref transport_init
 	.ref transport_on_h_frame
 	.ref transport_on_v_frame
 	.ref transport_on_v_frame_2
@@ -87,7 +86,9 @@
 ;Initialize connection and state machine here
 datalink_init:
 ;--------------------------------------------------------------------------------------------------
-	.sect ".text"
+	; part 2 code starts here
+
+	.sect ".text:part2"
 	jmp	main
 ;--------------------------------------------------------------------------------------------------
 ;--------------------------------------------------------------------------------------------------
@@ -264,6 +265,41 @@ hframe_7_fifo_push:
  	.endif ;Multichannel
 ;--------------------------------------------------------------------------------------------------
 
+;Reroute data link abort to avoid branching error.
+datalink_abort_jmp:
+    jmp datalink_abort
+;--------------------------------------------------------------------------------------------------
+
+;--------------------------------------------------------------------------------------------------
+;Function: switch_clk (RET_ADDR1)
+;
+;input:
+;	REG_FNC.w0: new clk_div
+;	REG_FNC.b2: #of cycles to wait before switching
+;output:
+;modifies:
+;	REG_TMP0, REG_FNC
+;--------------------------------------------------------------------------------------------------
+switch_clk:
+	.if !$defined("HDSL_MULTICHANNEL")
+	WAIT_CLK_LOW		REG_TMP0
+	WAIT_CLK_HIGH		REG_TMP0
+	sub			REG_FNC.b2, REG_FNC.b2, 1
+	qbne			switch_clk, REG_FNC.b2, 1
+	WAIT_CLK_LOW		REG_TMP0
+	;ldi     		REG_SCRATCH, P0EDTXCFG+2
+	sbco			&REG_FNC.w0, ICSS_CFGx, EDTXCFG+2, 2
+	WAIT_CLK_HIGH		REG_TMP0
+	.endif
+	RET1
+
+
+
+; common code starts here
+	.sect ".text"
+
+
+
 ;--------------------------------------------------------------------------------------------------
 ;Function: receive
 ;This functions receives data without deocoding.
@@ -328,70 +364,7 @@ receive_skip_wait:
 	CALL1			send_trailer
 	CALL1			send_stuffing
 	RET
-;--------------------------------------------------------------------------------------------------
-;Function: sync_pulse (RET_ADDR1)
-;functions bussy waits for sync pulse
-;input:
-;modifies:
-;--------------------------------------------------------------------------------------------------
-;stores sync pulse period in R20 in unit of cycles
-sync_pulse:
-	lbco        &REG_TMP1, c1, IEP_CAPR6_RISE, 4
-wait_next_pulse:
-	lbco        &R20, c1, IEP_CAPR6_RISE, 4
-	QBEQ		wait_next_pulse, R20, REG_TMP1
-	SUB         R20, R20, REG_TMP1
-	RET1
-;--------------------------------------------------------------------------------------------------
-;Function: int_div (RET_ADDR1)
-;integer divides
-;input:
-;	REG_FNC.w0: Number
-;	REG_FNC.w2: Divisor
-;output:
-;	REG_FNC.w2: Result
-;	REG_FNC.w0: Rest
-;modifies:
-;--------------------------------------------------------------------------------------------------
-int_div:
-	ldi			REG_TMP0, 0
-int_div_loop:
-	qbgt			int_div_end, REG_FNC.w0, REG_FNC.w2
-	sub			REG_FNC.w0, REG_FNC.w0, REG_FNC.w2
-	add			REG_TMP0, REG_TMP0, 1
-	qba			int_div_loop
-int_div_end:
-	mov			REG_FNC.w2, REG_TMP0
-	RET1
-;--------------------------------------------------------------------------------------------------
-;Function: check_test_pattern (RET_ADDR1)
-;This function checks if the test pattern was received
-;input:
-;	r18-r20: data
-;output:
-;	REG_FNC.b0: 1 if true
-;modifies:
-;	REG_TMP0, REG_FNC
-;--------------------------------------------------------------------------------------------------
-check_test_pattern:
-;load test pattern and mask from memory
 
-	lbco			&REG_TMP0, MASTER_REGS_CONST, TEST_PATTERN0, 12
-;rm switch bit
-	and			REG_TMP11, r19, REG_TMP2
-	ldi			REG_TMP2, 0xff8
-	and			REG_TMP2, r19, REG_TMP2
-	lsl			REG_TMP2, REG_TMP2, 1
-	or			REG_TMP11, REG_TMP2, REG_TMP11
-;if found go to next step
-	qbne			check_test_pattern_false, r20, REG_TMP0
-	qbne			check_test_pattern_false, REG_TMP11, REG_TMP1
-check_test_pattern_true:
-	ldi			REG_FNC.b0, 1
-	RET1
-check_test_pattern_false:
-	ldi			REG_FNC.b0, 0
-	RET1
 ;--------------------------------------------------------------------------------------------------
 ;Function: send_01 (RET_ADDR1)
 ;This function sends 01 pattern in RESET and SYNC state
@@ -469,10 +442,7 @@ aaa8:
 	RESET_CYCLCNT
 
 	RET1
-;Reroute data link abort to avoid branching error.
+
-datalink_abort_jmp:
-    jmp datalink_abort
-;--------------------------------------------------------------------------------------------------
 
 ;--------------------------------------------------------------------------------------------------
 ;Function: recv_dec_10b (RET_ADDR1)
@@ -1834,29 +1804,47 @@ datalink_abort_no_wait:
 	lbco			&REG_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1
 	add			REG_TMP0.b0, REG_TMP0.b0, 1
 	sbco			&REG_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1
-	jmp			datalink_reset
+; Trigger a reset in all channels
-;--------------------------------------------------------------------------------------------------
+
-;Function: switch_clk (RET_ADDR1)
+	.if $defined(CHANNEL_2)
-;
+;reset PRST bit in SYS_CTRL
-;input:
+	ldi 	REG_TMP1, DMEM_CH0_START
-;	REG_FNC.w0: new clk_div
+	lbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
-;	REG_FNC.b2: #of cycles to wait before switching
+	set		REG_TMP0.b0, REG_TMP0.b0, SYS_CTRL_PRST
-;output:
+	sbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
-;modifies:
+
-;	REG_TMP0, REG_FNC
+	ldi 	REG_TMP1, DMEM_CH1_START
-;--------------------------------------------------------------------------------------------------
+	lbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
-switch_clk:
+	set		REG_TMP0.b0, REG_TMP0.b0, SYS_CTRL_PRST
-	.if !$defined("HDSL_MULTICHANNEL")
+	sbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
-	WAIT_CLK_LOW		REG_TMP0
-	WAIT_CLK_HIGH		REG_TMP0
-	sub			REG_FNC.b2, REG_FNC.b2, 1
-	qbne			switch_clk, REG_FNC.b2, 1
-	WAIT_CLK_LOW		REG_TMP0
-	;ldi     		REG_SCRATCH, P0EDTXCFG+2
-	sbco			&REG_FNC.w0, ICSS_CFGx, EDTXCFG+2, 2
-	WAIT_CLK_HIGH		REG_TMP0
 	.endif
-	RET1
+
+	.if $defined(CHANNEL_1)
+	ldi 	REG_TMP1, DMEM_CH0_START
+	lbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	set		REG_TMP0.b0, REG_TMP0.b0, SYS_CTRL_PRST
+	sbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+
+	ldi 	REG_TMP1, DMEM_CH2_START
+	lbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	set		REG_TMP0.b0, REG_TMP0.b0, SYS_CTRL_PRST
+	sbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	.endif
+
+	.if $defined(CHANNEL_0)
+	ldi 	REG_TMP1, DMEM_CH1_START
+	lbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	set		REG_TMP0.b0, REG_TMP0.b0, SYS_CTRL_PRST
+	sbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+
+	ldi 	REG_TMP1, DMEM_CH2_START
+	lbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	set		REG_TMP0.b0, REG_TMP0.b0, SYS_CTRL_PRST
+	sbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	.endif
+
+	jmp			datalink_reset
+
 ;--------------------------------------------------------------------------------------------------
 ;Function: qm_add (RET_ADDR1)
 ;Adds value to Quality Monitor and resets connection if necessary
@@ -2228,3 +2216,25 @@ L3_15:
 
 L4_15:
     RET3
+
+;--------------------------------------------------------------------------------------------------
+;Function: int_div (RET_ADDR1)
+;integer divides
+;input:
+;	REG_FNC.w0: Number
+;	REG_FNC.w2: Divisor
+;output:
+;	REG_FNC.w2: Result
+;	REG_FNC.w0: Rest
+;modifies:
+;--------------------------------------------------------------------------------------------------
+int_div:
+	ldi			REG_TMP0, 0
+int_div_loop:
+	qbgt			int_div_end, REG_FNC.w0, REG_FNC.w2
+	sub			REG_FNC.w0, REG_FNC.w0, REG_FNC.w2
+	add			REG_TMP0, REG_TMP0, 1
+	qba			int_div_loop
+int_div_end:
+	mov			REG_FNC.w2, REG_TMP0
+	RET1

source/position_sense/hdsl/firmware/datalink_init.asm

@@ -36,7 +36,6 @@
 	.include "macros.inc"
 	.ref PUSH_FIFO_2B_8x
 	.ref WAIT_TX_FIFO_FREE
-	.ref transport_init
 	.ref qm_add
 	.ref calc_rssi
 	.ref send_stuffing
@@ -52,8 +51,6 @@
 	.ref datalink_loadfw
 	.ref recv_dec
 	.ref transport_on_h_frame
-	.ref sync_pulse
-	.ref check_test_pattern
 	.ref datalink_abort_jmp
 	.ref receive
 	.ref datalink_abort
@@ -61,18 +58,150 @@
 	.global datalink_init_start
 
 
-	.sect	".text"
+	; part 1 code starts here
 
-relocatable0:
+	.sect	".text:part1"
+
+;--------------------------------------------------------------------------------------------------
+;Function: check_test_pattern (RET_ADDR1)
+;This function checks if the test pattern was received
+;input:
+;	r18-r20: data
+;output:
+;	REG_FNC.b0: 1 if true
+;modifies:
+;	REG_TMP0, REG_FNC
+;--------------------------------------------------------------------------------------------------
+check_test_pattern:
+;load test pattern and mask from memory
+
+	lbco			&REG_TMP0, MASTER_REGS_CONST, TEST_PATTERN0, 12
+;rm switch bit
+	and			REG_TMP11, r19, REG_TMP2
+	ldi			REG_TMP2, 0xff8
+	and			REG_TMP2, r19, REG_TMP2
+	lsl			REG_TMP2, REG_TMP2, 1
+	or			REG_TMP11, REG_TMP2, REG_TMP11
+;if found go to next step
+	qbne			check_test_pattern_false, r20, REG_TMP0
+	qbne			check_test_pattern_false, REG_TMP11, REG_TMP1
+check_test_pattern_true:
+	ldi			REG_FNC.b0, 1
+	RET1
+check_test_pattern_false:
+	ldi			REG_FNC.b0, 0
+	RET1
+
+;--------------------------------------------------------------------------------------------------
+;Function: sync_pulse (RET_ADDR1)
+;functions bussy waits for sync pulse
+;input:
+;modifies:
+;--------------------------------------------------------------------------------------------------
+;stores sync pulse period in R20 in unit of cycles
+sync_pulse:
+	lbco        &REG_TMP1, c1, IEP_CAPR6_RISE, 4
+wait_next_pulse:
+	lbco        &R20, c1, IEP_CAPR6_RISE, 4
+	QBEQ		wait_next_pulse, R20, REG_TMP1
+	SUB         R20, R20, REG_TMP1
+	RET1
+
+
+	; common code starts here
+
+	.sect	".text"
 
 datalink_init_start:
 datalink_reset:
+
+; Synchronization and loading overlaid part of firmware for TXPRU (Channel 2) is needed,
+; only if channel 0 and 2 are enabled
+
+
+	.if !$defined(CHANNEL_2)
+; For channel 2, we always need to check for synchronization, so this code is not needed
+	LBCO   	&REG_TMP0.b0, MASTER_REGS_CONST, CHANNEL_MASK, 1
+	qbne 	skip_overlay_load1, REG_TMP0.b0, ((1<<0) | (1<<2))
+	.endif
+
+; Set sync bit and wait for all channels
+	SET_SYNC_BIT REG_TMP0
+	CALL WAIT_SYNC_SET_ALL
+
+	.if $defined(CHANNEL_0)
+
+; Following part of code on channel 0 loads the part 1 of overlaid firmware for
+; TXPRU (Channel 2)
+
+; Disable TXPRU1 before writing into IMEM
+	LDI32	REG_TMP0, TXPRU1_CTRL
+	LBBO  	&REG_TMP1, REG_TMP0, 0, 4
+	clr   	REG_TMP1, REG_TMP1, 1
+	SBBO  	&REG_TMP1, REG_TMP0, 0, 4
+
+; Load the load address, run address and size of part 1 of overlaid firmware
+; for TXPRU (Channel 2)
+	ZERO 	&REG_TMP0, 12
+	LBCO   	&REG_TMP0.w0, MASTER_REGS_CONST, PART1_LOAD_START, 2
+	LBCO   	&REG_TMP1.w0, MASTER_REGS_CONST, PART1_RUN_START, 2
+	; Add IMEM base address to run address
+	LDI32	REG_TMP2, TXPRU1_IMEM_BASE
+	ADD		REG_TMP1.w0, REG_TMP1.w0, REG_TMP2.w0
+	ADC		REG_TMP1.w2, REG_TMP1.w2, REG_TMP2.w2
+	LBCO   	&REG_TMP2.w0, MASTER_REGS_CONST, PART1_SIZE, 2
+    LDI    	REG_TMP2.w2, 0x0
+memcpy_loop1:
+    LBBO	&SPEED.b0, REG_TMP0,  REG_TMP2.w2, 32
+    SBBO	&SPEED.b0, REG_TMP1,  REG_TMP2.w2, 32
+    ADD 	REG_TMP2.w2,  REG_TMP2.w2, 32
+    QBLE	memcpy_loop1,  REG_TMP2.w0, REG_TMP2.w2
+
+	ZERO	&SPEED, (4*8)
+
+; Enable TXPRU1 before writing into IMEM
+	LDI32	REG_TMP0, TXPRU1_CTRL
+	LBBO  	&REG_TMP1, REG_TMP0, 0, 4
+	set   	REG_TMP1, REG_TMP1, 1
+	SBBO  	&REG_TMP1, REG_TMP0, 0, 4
+
+; Clear sync bit on RTUPRU (Channel 0).
+; PRU (Channel 1) and TXPRU (Channel 2) will pend on this bit clear.
+	CLEAR_SYNC_BIT REG_TMP1
+
+	.endif
+
+	.if $defined(CHANNEL_1)
+; Wait for RTUPRU (Channel 0) to clear sync bit and clear sync bit on PRU (Channel 1)
+; which signals completion of overlay part 1 load
+	WAIT_SYNC_CLEAR_CH0 REG_TMP0, REG_TMP1
+	CLEAR_SYNC_BIT REG_TMP1
+	.endif
+
+	.if $defined(CHANNEL_2)
+; Wait for RTUPRU (Channel 0) to clear sync bit and clear sync bit on TXPRU (Channel 2)
+; which signals completion of overlay part 1 load
+	WAIT_SYNC_CLEAR_CH0 REG_TMP0, REG_TMP1
+	CLEAR_SYNC_BIT REG_TMP1
+	.endif
+
+skip_overlay_load1:
+
+	jmp datalink_reset_after_fw_load
+	; part 1 code starts here
+
+	.if $defined(CHANNEL_2)
+	.sect	".text:part1"
+	.else
+	.sect	".text"
+	.endif
+datalink_reset_after_fw_load:
 ;State RESET
+
+; Clear all registers
 	zero			&r0, 124
-;send 2 times
 
 ;setup ICSS encoder peripheral for Hiperface DSL
-	ldi			DISPARITY, 0x00
 	TX_EN
 	SET_TX_CH0
 	REINIT_TX
@@ -88,14 +217,23 @@ datalink_reset:
     sbco	&REG_TMP0.b0, MASTER_REGS_CONST, VERSION, 1
     sbco	&REG_TMP0.b0, MASTER_REGS_CONST, VERSION2, 1
 
-	zero			&H_FRAME, (4*2)
 ;init transport layer here
-	CALL			transport_init
+;Initialize transport layer here
+transport_init:
+;resert short msg ctrl
+	ldi		REG_TMP0.b0, 0x3f
+	sbco		&REG_TMP0.b0, MASTER_REGS_CONST, SLAVE_REG_CTRL, 1
+;initialize acc_err_cnt to 0
+	sbco		&SPEED.b0, MASTER_REGS_CONST, ACC_ERR_CNT, 1
+	sbco		&SPEED.b0, MASTER_REGS_CONST, POS4, 8
+;reset rel. pos
+	sbco		&SPEED, MASTER_REGS_CONST, REL_POS0, 4
+transport_init_abs_err_loop:
+	ldi 	REG_TMP0.b0, 0
+	sbco 	&REG_TMP0.b0, MASTER_REGS_CONST, ALIGN_PH, 1
+exit_transport_init:
 ;QualityMonitor is initialized with 8
 	ldi			QM, 8
-;free running mode frame size is 108
-	ldi			EXTRA_SIZE, 0
-	ldi			NUM_STUFFING, 0
 ;reset PRST bit in SYS_CTRL
 	lbco			&REG_TMP0, MASTER_REGS_CONST, SYS_CTRL, 1
 	clr			REG_TMP0.b0, REG_TMP0.b0, SYS_CTRL_PRST
@@ -523,6 +661,44 @@ datalink_abort2_no_wait:
 	add			REG_TMP0.b0, REG_TMP0.b0, 1
 	sbco			&REG_TMP0.b0, MASTER_REGS_CONST, NUM_RESETS, 1
 ;we need rel. jump here
+
+	.if $defined(CHANNEL_2)
+;reset PRST bit in SYS_CTRL
+	ldi32 	REG_TMP1, DMEM_CH0_START
+	lbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	set		REG_TMP0.b0, REG_TMP0.b0, SYS_CTRL_PRST
+	sbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+
+	ldi32 	REG_TMP1, DMEM_CH1_START
+	lbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	set		REG_TMP0.b0, REG_TMP0.b0, SYS_CTRL_PRST
+	sbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	.endif
+
+	.if $defined(CHANNEL_1)
+	ldi32 	REG_TMP1, DMEM_CH0_START
+	lbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	set		REG_TMP0.b0, REG_TMP0.b0, SYS_CTRL_PRST
+	sbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+
+	ldi32 	REG_TMP1, DMEM_CH2_START
+	lbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	set		REG_TMP0.b0, REG_TMP0.b0, SYS_CTRL_PRST
+	sbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	.endif
+
+	.if $defined(CHANNEL_0)
+	ldi32 	REG_TMP1, DMEM_CH1_START
+	lbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	set		REG_TMP0.b0, REG_TMP0.b0, SYS_CTRL_PRST
+	sbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+
+	ldi32 	REG_TMP1, DMEM_CH2_START
+	lbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	set		REG_TMP0.b0, REG_TMP0.b0, SYS_CTRL_PRST
+	sbbo	&REG_TMP0, REG_TMP1, SYS_CTRL, 1
+	.endif
+
 	qba			datalink_reset
 ;--------------------------------------------------------------------------------------------------
 ;M_PAR_LEARN does not seem to have further meaning...
@@ -637,5 +813,195 @@ datalink_id_compute:
 	ldi 		DELTA_ACC0, 0
 	;qba datalink_id_req
 	CALL1		send_stuffing
+
+; Synchronization and loading overlaid part of firmware for TXPRU (Channel 2) is needed,
+; only if channel 0 and 2 are enabled
+
+	.if !$defined(CHANNEL_2)
+; For channel 2, we always need to check for synchronization, so this code is not needed
+	LBCO   	&REG_TMP0.b0, MASTER_REGS_CONST, CHANNEL_MASK, 1
+	qbne 	datalink_wait_vsynch, REG_TMP0.b0, ((1<<0) | (1<<2))
+	.endif
+
+	.if $defined(CHANNEL_0)
+
+; Following part of code on channel 0 loads the part 2 of overlaid firmware for
+; TXPRU (Channel 2)
+datalink_loadfw_start:
+
+	ldi			REG_FNC.w0, (0x0000 | M_PAR_IDREQ)
+	.if $defined("HDSL_MULTICHANNEL")
+	CALL			send_header_300m
+	.else
+	CALL			send_header
+	.endif
+	WAIT_TX_DONE
+
+	READ_IEPCNT	REG_TMP1
+	LDI 		REG_TMP2, (74*CYCLES_BIT + 25)
+	ADD 		REG_TMP1, REG_TMP1, REG_TMP2
+
+	SBCO 		&REG_TMP1, MASTER_REGS_CONST, LOADFW_TIMESTAMP, 4
+
+; Set sync bit and wait for all channels
+	SET_SYNC_BIT REG_TMP0
+	CALL WAIT_SYNC_SET_ALL
+
+; Disable TXPRU1 before writing into IMEM
+	LDI32	REG_TMP0, TXPRU1_CTRL
+	LBBO  	&REG_TMP1, REG_TMP0, 0, 4
+	clr   	REG_TMP1, REG_TMP1, 1
+	SBBO  	&REG_TMP1, REG_TMP0, 0, 4
+
+	LBBO  &REG_TMP1, REG_TMP0, 0, 4
+	clr   REG_TMP1, REG_TMP1, 1
+	SBBO  &REG_TMP1, REG_TMP0, 0, 4
+
+; Load the load address, run address and size of part 2 of overlaid firmware
+; for TXPRU (Channel 2)
+	ZERO 	&REG_TMP0, 12
+	LBCO   	&REG_TMP0.w0, MASTER_REGS_CONST, PART2_LOAD_START, 2
+	LBCO   	&REG_TMP1.w0, MASTER_REGS_CONST, PART2_RUN_START, 2
+	; Add IMEM base address to run address
+	LDI32	REG_TMP2, TXPRU1_IMEM_BASE
+	ADD		REG_TMP1.w0, REG_TMP1.w0, REG_TMP2.w0
+	ADC		REG_TMP1.w2, REG_TMP1.w2, REG_TMP2.w2
+	LBCO   	&REG_TMP2.w0, MASTER_REGS_CONST, PART2_SIZE, 2
+    LDI    	REG_TMP2.w2, 0x0
+memcpy_loop2:
+    LBBO	&SPEED.b0, REG_TMP0,  REG_TMP2.w2, 32
+    SBBO	&SPEED.b0, REG_TMP1,  REG_TMP2.w2, 32
+    ADD 	REG_TMP2.w2,  REG_TMP2.w2, 32
+    QBLE	memcpy_loop2,  REG_TMP2.w0, REG_TMP2.w2
+
+	ZERO	&SPEED, (4*8)
+
+; Enable TXPRU1 before writing into IMEM
+	LDI32	REG_TMP0, TXPRU1_CTRL
+	LBBO  	&REG_TMP1, REG_TMP0, 0, 4
+	set   	REG_TMP1, REG_TMP1, 1
+	SBBO  	&REG_TMP1, REG_TMP0, 0, 4
+
+; Clear Synchronization bit on RTUPRU (Channel 0).
+; PRU (Channel 1) and TXPRU (Channel 2) will pend on this bit clear.
+	CLEAR_SYNC_BIT REG_TMP1
+
+	LBCO 		&REG_TMP1, MASTER_REGS_CONST, LOADFW_TIMESTAMP, 4
+
+datalink_loadfw_wait_for_rx_completion:
+	READ_IEPCNT	REG_TMP2
+	qble datalink_loadfw_wait_for_rx_completion, REG_TMP1, REG_TMP2
+
+	TX_EN
+;send TRAILER
+	CALL1			send_trailer
+	CALL1			send_stuffing
+
+	jmp         datalink_wait_vsynch
+	.endif
+
+	.if $defined(CHANNEL_1)
+datalink_loadfw_start:
+	ldi			REG_FNC.w0, (0x0000 | M_PAR_IDREQ)
+	.if $defined("HDSL_MULTICHANNEL")
+	CALL			send_header_300m
+	.else
+	CALL			send_header
+	.endif
+	WAIT_TX_DONE
+
+	READ_IEPCNT	REG_TMP1
+	LDI 		REG_TMP2, (74*CYCLES_BIT + 25)
+	ADD 		REG_TMP1, REG_TMP1, REG_TMP2
+
+	SBCO 		&REG_TMP1, MASTER_REGS_CONST, LOADFW_TIMESTAMP, 4
+
+; Set sync bit and wait for all channels
+	SET_SYNC_BIT REG_TMP0
+	CALL WAIT_SYNC_SET_ALL
+; Wait for RTUPRU (Channel 0) to clear sync bit and clear sync bit on PRU (Channel 1)
+; which signals completion of overlay part 2 load
+	WAIT_SYNC_CLEAR_CH0 REG_TMP0, REG_TMP1
+	CLEAR_SYNC_BIT REG_TMP1
+
+	LBCO 		&REG_TMP1, MASTER_REGS_CONST, LOADFW_TIMESTAMP, 4
+
+datalink_loadfw_wait_for_rx_completion:
+	READ_IEPCNT	REG_TMP2
+	qble datalink_loadfw_wait_for_rx_completion, REG_TMP1, REG_TMP2
+
+	TX_EN
+;send TRAILER
+	CALL1			send_trailer
+	CALL1			send_stuffing
+
 	jmp         datalink_wait_vsynch
 
+	.endif
+
+	.if $defined(CHANNEL_2)
+datalink_loadfw_start:
+	ldi			REG_FNC.w0, (0x0000 | M_PAR_IDREQ)
+	.if $defined("HDSL_MULTICHANNEL")
+	CALL			send_header_300m
+	.else
+	CALL			send_header
+	.endif
+	WAIT_TX_DONE
+
+	READ_IEPCNT	REG_TMP1
+	LDI 		REG_TMP2, (74*CYCLES_BIT + 25)
+	ADD 		REG_TMP1, REG_TMP1, REG_TMP2
+
+	SBCO 		&REG_TMP1, MASTER_REGS_CONST, LOADFW_TIMESTAMP, 4
+
+	jmp 		datalink_loadfw_continue
+
+;  Jumping to .text only for channel 2
+	.sect ".text"
+
+datalink_loadfw_continue:
+
+; Set sync bit and wait for all channels
+	SET_SYNC_BIT REG_TMP0
+	CALL WAIT_SYNC_SET_ALL
+
+; Wait for RTUPRU (Channel 0) to clear sync bit and clear sync bit on TXPRU (Channel 2)
+; which signals completion of overlay part 2 load
+	WAIT_SYNC_CLEAR_CH0 REG_TMP0, REG_TMP1
+	CLEAR_SYNC_BIT REG_TMP1
+
+	LBCO 		&REG_TMP1, MASTER_REGS_CONST, LOADFW_TIMESTAMP, 4
+
+datalink_loadfw_wait_for_rx_completion:
+	READ_IEPCNT	REG_TMP2
+	qble datalink_loadfw_wait_for_rx_completion, REG_TMP1, REG_TMP2
+
+	TX_EN
+;send TRAILER
+	CALL1			send_trailer
+	CALL1			send_stuffing
+
+	jmp         datalink_wait_vsynch
+
+	.endif
+
+WAIT_SYNC_SET_ALL:
+	LBCO   	&REG_TMP1.b1, MASTER_REGS_CONST, CHANNEL_MASK, 1
+	QBBC 	wait_for_channel1?, REG_TMP1.b1, 0
+wait_for_channel0?:
+	LDI 	REG_TMP0, DMEM_CH0_START
+	LBBO	&REG_TMP1.b0, REG_TMP0, CHANNEL_SYNC, 1
+    QBNE  	wait_for_channel0?, REG_TMP1.b0, 1
+wait_for_channel1?:
+	QBBC 	wait_for_channel2?, REG_TMP1.b1, 1
+	LDI 	REG_TMP0, DMEM_CH1_START
+	LBBO	&REG_TMP1.b0, REG_TMP0, CHANNEL_SYNC, 1
+    QBNE  	wait_for_channel1?, REG_TMP1.b0, 1
+wait_for_channel2?:
+	QBBC 	wait_sync_clear_all_end?, REG_TMP1.b1, 2
+	LDI 	REG_TMP0, DMEM_CH2_START
+	LBBO	&REG_TMP1.b0, REG_TMP0, CHANNEL_SYNC, 1
+    QBNE  	wait_for_channel2?, REG_TMP1.b0, 1
+wait_sync_clear_all_end?:
+	RET

source/position_sense/hdsl/firmware/defines.inc

@@ -34,7 +34,7 @@
 ;  bit7..4		major number
 FIRMWARE_VERSION_MAJOR	.set			0x0
 ;  bit3..0		minor number
-FIRMWARE_VERSION_MINOR	.set			0xD
+FIRMWARE_VERSION_MINOR	.set			0xE
 
 ICSS_FIRMWARE_RELEASE	.set            ((FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0))
 

source/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am243x.js

@@ -9,7 +9,6 @@ const files = {
         "datalink_init.asm",
         "transport.asm",
         "utils.asm",
-        "hdsl_master_icssg_hexpru.cmd",
         "hdsl_master_icssg.cmd",
     ],
 };
@@ -33,7 +32,6 @@ const includes = {
 
 const defines = {
     common: [
-        "icss1",
         "PRU1",
         "CHANNEL_0",
         "ICSS_G_V_1_0",

source/position_sense/hdsl/firmware/freerun_225_mhz/.project/project_am64x.js

@@ -9,7 +9,6 @@ const files = {
         "datalink_init.asm",
         "transport.asm",
         "utils.asm",
-        "hdsl_master_icssg_hexpru.cmd",
         "hdsl_master_icssg.cmd",
     ],
 };
@@ -33,7 +32,6 @@ const includes = {
 
 const defines = {
     common: [
-        "icss1",
         "PRU1",
         "CHANNEL_0",
         "ICSS_G_V_1_0",

source/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -34,7 +34,6 @@
             -DPRU1
             -DSLICE1
             -DSOC_AM243X
-            -Dicss1
             -DPRU1
             -DCHANNEL_0
             -DICSS_G_V_1_0
@@ -74,8 +73,6 @@
         </file>
         <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
-        <file path="../../../../hdsl_master_icssg_hexpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
-        </file>
         <file path="../../../../hdsl_master_icssg.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
         <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am243x/HDSL_DESIGN.html"

source/position_sense/hdsl/firmware/freerun_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -59,7 +59,7 @@ all: $(OBJS) $(CMD_SRCS)
 $(OBJDIR)/$(OBJS): $(ASM_SRCS) 
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: PRU Compiler'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
@@ -67,7 +67,7 @@ $(OBJDIR)/$(OBJS): $(ASM_SRCS)
 hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
 	@echo 'Building target: "$@"'
 	@echo 'Invoking: PRU Linker'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_freerun_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
 	@echo 'Finished building target: "$@"'
 	@echo ' '
 	@$(MAKE) --no-print-directory post-build

source/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -34,7 +34,6 @@
             -DPRU1
             -DSLICE1
             -DSOC_AM64X
-            -Dicss1
             -DPRU1
             -DCHANNEL_0
             -DICSS_G_V_1_0
@@ -74,8 +73,6 @@
         </file>
         <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
-        <file path="../../../../hdsl_master_icssg_hexpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
-        </file>
         <file path="../../../../hdsl_master_icssg.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
         <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am64x/HDSL_DESIGN.html"

source/position_sense/hdsl/firmware/freerun_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -59,7 +59,7 @@ all: $(OBJS) $(CMD_SRCS)
 $(OBJDIR)/$(OBJS): $(ASM_SRCS) 
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: PRU Compiler'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
@@ -67,7 +67,7 @@ $(OBJDIR)/$(OBJS): $(ASM_SRCS)
 hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
 	@echo 'Building target: "$@"'
 	@echo 'Invoking: PRU Linker'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_freerun_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
 	@echo 'Finished building target: "$@"'
 	@echo ' '
 	@$(MAKE) --no-print-directory post-build

source/position_sense/hdsl/firmware/hdsl_master_icssg.cmd

@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2021 Texas Instruments Incorporated
+ *  Copyright (C) 2021-2023 Texas Instruments Incorporated
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions
@@ -43,4 +43,6 @@ SECTIONS
 {
     .text:main		>	0x0
     .text			>	PRUIMEM, PAGE 0
+    .text:part1		>	PRUIMEM, PAGE 0
+    .text:part2		>	PRUIMEM, PAGE 0
 }

source/position_sense/hdsl/firmware/hdsl_master_icssg_hexpru.cmd

@@ -1,3 +0,0 @@
--b
--map=Hiperface_DSL2_2.map
-SECTIONS {.text}

source/position_sense/hdsl/firmware/hdsl_master_icssg_txpru.cmd

@@ -0,0 +1,59 @@
+/*
+ *  Copyright (C) 2021-2023 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+MEMORY
+{
+    PAGE 0:
+      PRUIMEM:   o = 0x00000000  l = 0x00002800  /* 6kB TXPRU Instruction RAM */
+    PAGE 1:
+      PRUDMEM:   o = 0x00001500  l = 0x00000B00  /* Part of 8kB PRU Data RAM 1 */
+    PAGE 2:
+      DUMMY: 	 o = 0x00000000  l = 0x00000100
+}
+
+SECTIONS
+{
+	GROUP
+	{
+	    .text:main
+	    .text
+    } >	PRUIMEM, PAGE 0
+
+	UNION
+	{
+		.text:part1: load = PRUDMEM, PAGE 1, table(_part1_copy_table)
+		.text:part2: load = PRUDMEM, PAGE 1, table(_part2_copy_table)
+	} run = PRUIMEM
+
+	.ovly > DUMMY, PAGE 2
+
+}

source/position_sense/hdsl/firmware/macros.inc

@@ -45,7 +45,6 @@ CALL1 .macro func
 RET1 .macro
     JMP     RET_ADDR1
     .endm
-
 CALL2 .macro func
     jal     RET_ADDR2, func
     .endm
@@ -290,6 +289,7 @@ READ_CYCLCNT .macro dst
     lbco        &dst, PRU_CTRL_CONST, PRU_CYCLCNT, 4
     .endm
 
+; Reads lower 32 bits of IEP0 Timer
 READ_IEPCNT .macro dst
     lbco        &dst, IEP_CONST, IEP_CNT, 4
     .endm
@@ -337,3 +337,77 @@ NOP_n .macro dat
     and         r0, r0, r0
 lw?:
     .endm
+
+; Set Sync bit
+SET_SYNC_BIT .macro tmp0
+	LDI 	tmp0.b0, 0x1
+	SBCO	&tmp0.b0, MASTER_REGS_CONST, CHANNEL_SYNC, 1
+	.endm
+
+; Clear Sync bit
+CLEAR_SYNC_BIT .macro tmp0
+	LDI 	tmp0.b0, 0x0
+	SBCO	&tmp0.b0, MASTER_REGS_CONST, CHANNEL_SYNC, 1
+	.endm
+
+WAIT_SYNC_CH0 .macro tmp0, tmp1
+wait_for_channel0?:
+	LDI 	tmp0, DMEM_CH0_START
+	LBBO	&tmp1.b0, tmp0, CHANNEL_SYNC, 1
+    QBNE  	wait_for_channel0?, tmp1.b0, 1
+	.endm
+
+WAIT_SYNC_CH1 .macro tmp0, tmp1
+wait_for_channel1?:
+	LDI 	tmp0, DMEM_CH1_START
+	LBBO	&tmp1.b0, tmp0, CHANNEL_SYNC, 1
+    QBNE  	wait_for_channel1?, tmp1.b0, 1
+	.endm
+
+WAIT_SYNC_CH2 .macro tmp0, tmp1
+wait_for_channel2?:
+	LDI 	tmp0, DMEM_CH2_START
+	LBBO	&tmp1.b0, tmp0, CHANNEL_SYNC, 1
+    QBNE  	wait_for_channel2?, tmp1.b0, 1
+	.endm
+
+WAIT_SYNC_CLEAR_CH0 .macro tmp0, tmp1
+wait_for_channel0?:
+	LDI 	tmp0, DMEM_CH0_START
+	LBBO	&tmp1.b0, tmp0, CHANNEL_SYNC, 1
+    QBNE  	wait_for_channel0?, tmp1.b0, 0
+	.endm
+
+WAIT_SYNC_CLEAR_CH1 .macro tmp0, tmp1
+wait_for_channel1?:
+	LDI 	tmp0, DMEM_CH1_START
+	LBBO	&tmp1.b0, tmp0, CHANNEL_SYNC, 1
+    QBNE  	wait_for_channel1?, tmp1.b0, 0
+	.endm
+
+WAIT_SYNC_CLEAR_CH2 .macro tmp0, tmp1
+wait_for_channel2?:
+	LDI 	tmp0, DMEM_CH2_START
+	LBBO	&tmp1.b0, tmp0, CHANNEL_SYNC, 1
+    QBNE  	wait_for_channel2?, tmp1.b0, 0
+	.endm
+
+WAIT_SYNC_CLEAR_ALL .macro tmp0, tmp1
+	LBCO   	&tmp1.b1, MASTER_REGS_CONST, CHANNEL_MASK, 1
+	QBBC 	wait_for_channel1?, tmp1.b1, 0
+wait_for_channel0?:
+	LDI 	tmp0, DMEM_CH0_START
+	LBBO	&tmp1.b0, tmp0, CHANNEL_SYNC, 1
+    QBNE  	wait_for_channel0?, tmp1.b0, 0
+wait_for_channel1?:
+	QBBC 	wait_for_channel2?, tmp1.b1, 1
+	LDI 	tmp0, DMEM_CH1_START
+	LBBO	&tmp1.b0, tmp0, CHANNEL_SYNC, 1
+    QBNE  	wait_for_channel1?, tmp1.b0, 0
+wait_for_channel2?:
+	QBBC 	wait_sync_clear_all_end?, tmp1.b1, 2
+	LDI 	tmp0, DMEM_CH2_START
+	LBBO	&tmp1.b0, tmp0, CHANNEL_SYNC, 1
+    QBNE  	wait_for_channel2?, tmp1.b0, 0	
+wait_sync_clear_all_end?:	
+	.endm

source/position_sense/hdsl/firmware/main.asm

@@ -37,7 +37,6 @@
 	.retain 	; Required for building .out with assembly file
 	.retainrefs ; Required for building .out with assembly file
 	.ref datalink_init
-	.ref transport_init
 	.ref load_code
 	.ref datalink_init_start
 	.global	main

source/position_sense/hdsl/firmware/memory.inc

@@ -84,7 +84,9 @@ EDCH2CFG1 .set                          P0EDCH2CFG1
 ; Each HDSL channel will use a portion of DMEM for HDSL shared/local data storage for that channel.
 ; CHANNEL_0: 0x0000 - 0x06FF
 ; CHANNEL_1: 0x0700 - 0x0DFF
-; CHANNEL_2: 0x0E00 - 0x0~FF
+; CHANNEL_2: 0x0E00 - 0x14FF
+
+; 0X1500 - 0X1FFF is used to store the overlay part of firmare for TXPRU (Channel 2)
 
     .if $defined(CHANNEL_2)   ; TX_PRU
 PDMEM00	                  .set					   0x0E00
@@ -96,6 +98,11 @@ PDMEM00		              .set					   0x0700
 PDMEM00			          .set					   0x0000
 	.endif
 
+DMEM_CH0_START .set 					0x0000
+DMEM_CH1_START .set 					0x0700
+DMEM_CH2_START .set 					0x0E00
+DMEM_CH_SIZE .set						0x0700
+
 PDMEM00_CONST .set						C24
 MASTER_REGS_CONST .set                  C24
 IEP1_BASE_CONST .set					C1
@@ -388,32 +395,22 @@ ADDR .set 0x15ff
 ;--------------------------------------------------------------------------------------------------
 ;Memory offsets
 ;--------------------------------------------------------------------------------------------------
-PRU_CTRL_CONST	.set						C28
+PRU_CTRL_CONST	.set					C28
-;PRU_CTRL	.set						0x00022000
 PRU_CYCLCNT	.set						0x0c
-PWMSS1_CONST	.set						C19     ;AM437x specific for sync pule synchronization
+PWMSS1_CONST	.set					C19
-PWMSS1_ECAP	.set						0x48302100  ;AM437x specific for sync pule synchronization
+PWMSS2_CONST	.set					C20
-PWMSS2_CONST	.set						C20     ;AM437x specific for sync pule synchronization
+ECAP		.set						0x100
-ECAP		.set						0x100       ;AM437x specific for sync pule synchronization
+ECAP_ECCLR	.set						0x30
-ECAP_ECCLR	.set						0x30        ;AM437x specific for sync pule synchronization
+ECAP_ECCTL1	.set						0x28
-ECAP_ECEINT	.set						0x2c        ;AM437x specific for sync pule synchronization
-ECAP_CAP1	.set						0x08        ;AM437x specific for sync pule synchronization
-ECAP_ECCTL1	.set						0x28        ;AM437x specific for sync pule synchronization
-INTC_SICR	.set						0x24        ;AM437x specific for sync pule synchronization
-INTC_SECR1	.set						0x284       ;AM437x specific for sync pule synchronization
-INTC_SECR0	.set						0x280       ;AM437x specific for sync pule synchronization
-INTC_CONST	.set						C0          ;AM437x specific for sync pule synchronization
 IEP_CONST	.set						C26
 IEP1_CONST  .set                        0x2F000
-IEP_CNT		.set						0x14 ;todo TSmod check as 64bit now (old0x0c)
+IEP_CNT		.set						0x10
 IEP_CAPR6_RISE .set                     0x50
-SHARED_MEM_CONST  .set                  0x0b010000;0x54442000+0x10000
+TXPRU1_CTRL .set 						0x00025800
-;--------------------------------------------------------------------------------------------------
+TXPRU1_IMEM_BASE .set 					0x0000C000
-;Memory offsets for dynamic loading of PRU code
+
-;--------------------------------------------------------------------------------------------------
+; 0X1500 - 0X1FFF is used to store the overlay part of firmare for TXPRU (Channel 2)
-CODE_BASE	.set						(0x40300000);(0x54400000+0x00040000+0x2100)
+DYNAMIC_CODE_OFFSET .set				0x1500
-CODE_SIZE	.set						0x600
-DYNAMIC_CODE_OFFSET .set				0x1000 ;0x2100
 
 ;--------------------------------------------------------------------------------------------------
 ;R31 flags for RX
@@ -516,3 +513,12 @@ VPOS2_TEMP .set                         0x63 ; 5 bytes
 VPOSCRC2_TEMP .set                      0x68 ; 2 bytes
 SAFE_SUM_TEMP .set                      0x70 ; 1 byte
 ALIGN_PH .set                      		0x71 ; 1 byte
+LOADFW_TIMESTAMP .set 					0x72 ; 4 bytes
+PART1_LOAD_START .set					0x76 ; 2 bytes
+PART1_RUN_START .set					0x78 ; 2 bytes
+PART1_SIZE .set							0x7A ; 2 bytes
+PART2_LOAD_START .set					0x7C ; 2 bytes
+PART2_RUN_START .set					0x7E ; 2 bytes
+PART2_SIZE .set							0x80 ; 2 bytes
+CHANNEL_SYNC .set						0x82 ; 1 byte
+CHANNEL_MASK .set						0x83 ; 1 byte

source/position_sense/hdsl/firmware/multichannel_ch0/.project/project_am243x.js

@@ -9,7 +9,6 @@ const files = {
         "datalink_init.asm",
         "transport.asm",
         "utils.asm",
-        "hdsl_master_icssg_hexpru.cmd",
         "hdsl_master_icssg.cmd",
     ],
 };
@@ -33,7 +32,6 @@ const includes = {
 
 const defines = {
     common: [
-        "icss1",
         "PRU1",
         "CHANNEL_0",
         "ICSS_G_V_1_0",

source/position_sense/hdsl/firmware/multichannel_ch0/.project/project_am64x.js

@@ -9,7 +9,6 @@ const files = {
         "datalink_init.asm",
         "transport.asm",
         "utils.asm",
-        "hdsl_master_icssg_hexpru.cmd",
         "hdsl_master_icssg.cmd",
     ],
 };
@@ -33,7 +32,6 @@ const includes = {
 
 const defines = {
     common: [
-        "icss1",
         "PRU1",
         "CHANNEL_0",
         "ICSS_G_V_1_0",

source/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -34,7 +34,6 @@
             -DPRU1
             -DSLICE1
             -DSOC_AM243X
-            -Dicss1
             -DPRU1
             -DCHANNEL_0
             -DICSS_G_V_1_0
@@ -76,8 +75,6 @@
         </file>
         <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
-        <file path="../../../../hdsl_master_icssg_hexpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
-        </file>
         <file path="../../../../hdsl_master_icssg.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
         <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am243x/HDSL_DESIGN.html"

source/position_sense/hdsl/firmware/multichannel_ch0/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -59,7 +59,7 @@ all: $(OBJS) $(CMD_SRCS)
 $(OBJDIR)/$(OBJS): $(ASM_SRCS) 
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: PRU Compiler'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
@@ -67,7 +67,7 @@ $(OBJDIR)/$(OBJS): $(ASM_SRCS)
 hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
 	@echo 'Building target: "$@"'
 	@echo 'Invoking: PRU Linker'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch0_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
 	@echo 'Finished building target: "$@"'
 	@echo ' '
 	@$(MAKE) --no-print-directory post-build

source/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -34,7 +34,6 @@
             -DPRU1
             -DSLICE1
             -DSOC_AM64X
-            -Dicss1
             -DPRU1
             -DCHANNEL_0
             -DICSS_G_V_1_0
@@ -76,8 +75,6 @@
         </file>
         <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
-        <file path="../../../../hdsl_master_icssg_hexpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
-        </file>
         <file path="../../../../hdsl_master_icssg.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
         <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am64x/HDSL_DESIGN.html"

source/position_sense/hdsl/firmware/multichannel_ch0/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -59,7 +59,7 @@ all: $(OBJS) $(CMD_SRCS)
 $(OBJDIR)/$(OBJS): $(ASM_SRCS) 
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: PRU Compiler'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
@@ -67,7 +67,7 @@ $(OBJDIR)/$(OBJS): $(ASM_SRCS)
 hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
 	@echo 'Building target: "$@"'
 	@echo 'Invoking: PRU Linker'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch0_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
 	@echo 'Finished building target: "$@"'
 	@echo ' '
 	@$(MAKE) --no-print-directory post-build

source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project_am243x.js

@@ -9,7 +9,6 @@ const files = {
         "datalink_init.asm",
         "transport.asm",
         "utils.asm",
-        "hdsl_master_icssg_hexpru.cmd",
         "hdsl_master_icssg.cmd",
     ],
 };
@@ -33,7 +32,6 @@ const includes = {
 
 const defines = {
     common: [
-        "icss1",
         "PRU1",
         "CHANNEL_0",
         "ICSS_G_V_1_0",

source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/.project/project_am64x.js

@@ -9,7 +9,6 @@ const files = {
         "datalink_init.asm",
         "transport.asm",
         "utils.asm",
-        "hdsl_master_icssg_hexpru.cmd",
         "hdsl_master_icssg.cmd",
     ],
 };
@@ -33,7 +32,6 @@ const includes = {
 
 const defines = {
     common: [
-        "icss1",
         "PRU1",
         "CHANNEL_0",
         "ICSS_G_V_1_0",

source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -34,7 +34,6 @@
             -DPRU1
             -DSLICE1
             -DSOC_AM243X
-            -Dicss1
             -DPRU1
             -DCHANNEL_0
             -DICSS_G_V_1_0
@@ -77,8 +76,6 @@
         </file>
         <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
-        <file path="../../../../hdsl_master_icssg_hexpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
-        </file>
         <file path="../../../../hdsl_master_icssg.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
         <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am243x/HDSL_DESIGN.html"

source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -59,7 +59,7 @@ all: $(OBJS) $(CMD_SRCS)
 $(OBJDIR)/$(OBJS): $(ASM_SRCS) 
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: PRU Compiler'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
@@ -67,7 +67,7 @@ $(OBJDIR)/$(OBJS): $(ASM_SRCS)
 hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
 	@echo 'Building target: "$@"'
 	@echo 'Invoking: PRU Linker'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch0_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
 	@echo 'Finished building target: "$@"'
 	@echo ' '
 	@$(MAKE) --no-print-directory post-build

source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -34,7 +34,6 @@
             -DPRU1
             -DSLICE1
             -DSOC_AM64X
-            -Dicss1
             -DPRU1
             -DCHANNEL_0
             -DICSS_G_V_1_0
@@ -77,8 +76,6 @@
         </file>
         <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
-        <file path="../../../../hdsl_master_icssg_hexpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
-        </file>
         <file path="../../../../hdsl_master_icssg.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
         <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am64x/HDSL_DESIGN.html"

source/position_sense/hdsl/firmware/multichannel_ch0_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -59,7 +59,7 @@ all: $(OBJS) $(CMD_SRCS)
 $(OBJDIR)/$(OBJS): $(ASM_SRCS) 
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: PRU Compiler'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
@@ -67,7 +67,7 @@ $(OBJDIR)/$(OBJS): $(ASM_SRCS)
 hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
 	@echo 'Building target: "$@"'
 	@echo 'Invoking: PRU Linker'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_0 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch0_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
 	@echo 'Finished building target: "$@"'
 	@echo ' '
 	@$(MAKE) --no-print-directory post-build

source/position_sense/hdsl/firmware/multichannel_ch1/.project/project_am243x.js

@@ -9,7 +9,6 @@ const files = {
         "datalink_init.asm",
         "transport.asm",
         "utils.asm",
-        "hdsl_master_icssg_hexpru.cmd",
         "hdsl_master_icssg.cmd",
     ],
 };
@@ -33,7 +32,6 @@ const includes = {
 
 const defines = {
     common: [
-        "icss1",
         "PRU1",
         "CHANNEL_1",
         "ICSS_G_V_1_0",

source/position_sense/hdsl/firmware/multichannel_ch1/.project/project_am64x.js

@@ -9,7 +9,6 @@ const files = {
         "datalink_init.asm",
         "transport.asm",
         "utils.asm",
-        "hdsl_master_icssg_hexpru.cmd",
         "hdsl_master_icssg.cmd",
     ],
 };
@@ -33,7 +32,6 @@ const includes = {
 
 const defines = {
     common: [
-        "icss1",
         "PRU1",
         "CHANNEL_1",
         "ICSS_G_V_1_0",

source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -34,7 +34,6 @@
             -DPRU1
             -DSLICE1
             -DSOC_AM243X
-            -Dicss1
             -DPRU1
             -DCHANNEL_1
             -DICSS_G_V_1_0
@@ -76,8 +75,6 @@
         </file>
         <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
-        <file path="../../../../hdsl_master_icssg_hexpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
-        </file>
         <file path="../../../../hdsl_master_icssg.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
         <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am243x/HDSL_DESIGN.html"

source/position_sense/hdsl/firmware/multichannel_ch1/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -59,7 +59,7 @@ all: $(OBJS) $(CMD_SRCS)
 $(OBJDIR)/$(OBJS): $(ASM_SRCS) 
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: PRU Compiler'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
@@ -67,7 +67,7 @@ $(OBJDIR)/$(OBJS): $(ASM_SRCS)
 hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
 	@echo 'Building target: "$@"'
 	@echo 'Invoking: PRU Linker'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch1_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
 	@echo 'Finished building target: "$@"'
 	@echo ' '
 	@$(MAKE) --no-print-directory post-build

source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -34,7 +34,6 @@
             -DPRU1
             -DSLICE1
             -DSOC_AM64X
-            -Dicss1
             -DPRU1
             -DCHANNEL_1
             -DICSS_G_V_1_0
@@ -76,8 +75,6 @@
         </file>
         <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
-        <file path="../../../../hdsl_master_icssg_hexpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
-        </file>
         <file path="../../../../hdsl_master_icssg.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
         <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am64x/HDSL_DESIGN.html"

source/position_sense/hdsl/firmware/multichannel_ch1/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -59,7 +59,7 @@ all: $(OBJS) $(CMD_SRCS)
 $(OBJDIR)/$(OBJS): $(ASM_SRCS) 
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: PRU Compiler'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
@@ -67,7 +67,7 @@ $(OBJDIR)/$(OBJS): $(ASM_SRCS)
 hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
 	@echo 'Building target: "$@"'
 	@echo 'Invoking: PRU Linker'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch1_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
 	@echo 'Finished building target: "$@"'
 	@echo ' '
 	@$(MAKE) --no-print-directory post-build

source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project_am243x.js

@@ -9,7 +9,6 @@ const files = {
         "datalink_init.asm",
         "transport.asm",
         "utils.asm",
-        "hdsl_master_icssg_hexpru.cmd",
         "hdsl_master_icssg.cmd",
     ],
 };
@@ -33,7 +32,6 @@ const includes = {
 
 const defines = {
     common: [
-        "icss1",
         "PRU1",
         "CHANNEL_1",
         "ICSS_G_V_1_0",

source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/.project/project_am64x.js

@@ -9,7 +9,6 @@ const files = {
         "datalink_init.asm",
         "transport.asm",
         "utils.asm",
-        "hdsl_master_icssg_hexpru.cmd",
         "hdsl_master_icssg.cmd",
     ],
 };
@@ -33,7 +32,6 @@ const includes = {
 
 const defines = {
     common: [
-        "icss1",
         "PRU1",
         "CHANNEL_1",
         "ICSS_G_V_1_0",

source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -34,7 +34,6 @@
             -DPRU1
             -DSLICE1
             -DSOC_AM243X
-            -Dicss1
             -DPRU1
             -DCHANNEL_1
             -DICSS_G_V_1_0
@@ -77,8 +76,6 @@
         </file>
         <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
-        <file path="../../../../hdsl_master_icssg_hexpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
-        </file>
         <file path="../../../../hdsl_master_icssg.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
         <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am243x/HDSL_DESIGN.html"

source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -59,7 +59,7 @@ all: $(OBJS) $(CMD_SRCS)
 $(OBJDIR)/$(OBJS): $(ASM_SRCS) 
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: PRU Compiler'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
@@ -67,7 +67,7 @@ $(OBJDIR)/$(OBJS): $(ASM_SRCS)
 hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
 	@echo 'Building target: "$@"'
 	@echo 'Invoking: PRU Linker'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch1_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
 	@echo 'Finished building target: "$@"'
 	@echo ' '
 	@$(MAKE) --no-print-directory post-build

source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -34,7 +34,6 @@
             -DPRU1
             -DSLICE1
             -DSOC_AM64X
-            -Dicss1
             -DPRU1
             -DCHANNEL_1
             -DICSS_G_V_1_0
@@ -77,8 +76,6 @@
         </file>
         <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
-        <file path="../../../../hdsl_master_icssg_hexpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
-        </file>
         <file path="../../../../hdsl_master_icssg.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
         <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am64x/HDSL_DESIGN.html"

source/position_sense/hdsl/firmware/multichannel_ch1_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -59,7 +59,7 @@ all: $(OBJS) $(CMD_SRCS)
 $(OBJDIR)/$(OBJS): $(ASM_SRCS) 
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: PRU Compiler'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
@@ -67,7 +67,7 @@ $(OBJDIR)/$(OBJS): $(ASM_SRCS)
 hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
 	@echo 'Building target: "$@"'
 	@echo 'Invoking: PRU Linker'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_1 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch1_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
 	@echo 'Finished building target: "$@"'
 	@echo ' '
 	@$(MAKE) --no-print-directory post-build

source/position_sense/hdsl/firmware/multichannel_ch2/.project/project.js

@@ -0,0 +1,14 @@
+function getComponentProperty(device)
+{
+    return require(`./project_${device}`).getComponentProperty();
+};
+
+function getComponentBuildProperty(buildOption)
+{
+    return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption);
+};
+
+module.exports = {
+    getComponentProperty,
+    getComponentBuildProperty,
+};

source/position_sense/hdsl/firmware/multichannel_ch2/.project/project_am243x.js

@@ -0,0 +1,98 @@
+let path = require('path');
+
+let device = "am243x";
+
+const files = {
+    common: [
+        "main.asm",
+        "datalink.asm",
+        "datalink_init.asm",
+        "transport.asm",
+        "utils.asm",
+        "hdsl_master_icssg_txpru.cmd",
+    ],
+};
+
+/* Relative to where the makefile will be generated
+ * Typically at <example_folder>/<BOARD>/<core_os_combo>/<compiler>
+ */
+const filedirs = {
+    common: [
+        "..",       /* core_os_combo base */
+        "../../..", /* Example base */
+        "../../../..",
+    ],
+};
+
+const includes = {
+    common: [
+        "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware",
+    ],
+};
+
+const defines = {
+    common: [
+        "PRU1",
+        "CHANNEL_2",
+        "ICSS_G_V_1_0",
+        "FREERUN_300_MHZ",
+        "HDSL_MULTICHANNEL",
+    ],
+};
+
+const lflags = {
+    common: [
+        "--disable_auto_rts",
+        "--entry_point=main",
+    ],
+};
+
+let postBuildSteps = [
+    "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_TX_PRU -o hdsl_master_icssg_multichannel_ch2_bin.h hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out;  move  hdsl_master_icssg_multichannel_ch2_bin.h  ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_bin.h"
+];
+
+
+const readmeDoxygenPageTag = "HDSL_DESIGN";
+
+const buildOptionCombos = [
+    { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"},
+];
+
+function getComponentProperty() {
+    let property = {};
+
+    property.dirPath = path.resolve(__dirname, "..");
+    property.type = "executable";
+    property.makefile = "pru";
+    property.name = "hdsl_master_multichannel_ch2";
+    property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 300 MHz";
+    property.isInternal = false;
+    property.buildOptionCombos = buildOptionCombos;
+    property.pru_main_file = "main";
+    property.pru_linker_file = "hdsl_master_icssg_txpru";
+    property.isSkipTopLevelBuild = true;
+    property.skipUpdatingTirex = true;
+
+    return property;
+}
+
+function getComponentBuildProperty(buildOption) {
+    let build_property = {};
+
+    build_property.files = files;
+    build_property.filedirs = filedirs;
+    build_property.includes = includes;
+    build_property.defines = defines;
+    build_property.lflags = lflags;
+    build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
+    build_property.postBuildSteps = postBuildSteps;
+    build_property.projecspecFileAction = "copy";
+    build_property.skipMakefileCcsBootimageGen = true;
+
+    return build_property;
+}
+
+module.exports = {
+    getComponentProperty,
+    getComponentBuildProperty,
+};

source/position_sense/hdsl/firmware/multichannel_ch2/.project/project_am64x.js

@@ -0,0 +1,98 @@
+let path = require('path');
+
+let device = "am64x";
+
+const files = {
+    common: [
+        "main.asm",
+        "datalink.asm",
+        "datalink_init.asm",
+        "transport.asm",
+        "utils.asm",
+        "hdsl_master_icssg_txpru.cmd",
+    ],
+};
+
+/* Relative to where the makefile will be generated
+ * Typically at <example_folder>/<BOARD>/<core_os_combo>/<compiler>
+ */
+const filedirs = {
+    common: [
+        "..",       /* core_os_combo base */
+        "../../..", /* Example base */
+        "../../../..",
+    ],
+};
+
+const includes = {
+    common: [
+        "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware",
+    ],
+};
+
+const defines = {
+    common: [
+        "PRU1",
+        "CHANNEL_2",
+        "ICSS_G_V_1_0",
+        "FREERUN_300_MHZ",
+        "HDSL_MULTICHANNEL",
+    ],
+};
+
+const lflags = {
+    common: [
+        "--disable_auto_rts",
+        "--entry_point=main",
+    ],
+};
+
+let postBuildSteps = [
+    "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_TX_PRU -o hdsl_master_icssg_multichannel_ch2_bin.h hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out;  move  hdsl_master_icssg_multichannel_ch2_bin.h  ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_bin.h"
+];
+
+
+const readmeDoxygenPageTag = "HDSL_DESIGN";
+
+const buildOptionCombos = [
+    { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"},
+];
+
+function getComponentProperty() {
+    let property = {};
+
+    property.dirPath = path.resolve(__dirname, "..");
+    property.type = "executable";
+    property.makefile = "pru";
+    property.name = "hdsl_master_multichannel_ch2";
+    property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 300 MHz";
+    property.isInternal = false;
+    property.buildOptionCombos = buildOptionCombos;
+    property.pru_main_file = "main";
+    property.pru_linker_file = "hdsl_master_icssg_txpru";
+    property.isSkipTopLevelBuild = true;
+    property.skipUpdatingTirex = true;
+
+    return property;
+}
+
+function getComponentBuildProperty(buildOption) {
+    let build_property = {};
+
+    build_property.files = files;
+    build_property.filedirs = filedirs;
+    build_property.includes = includes;
+    build_property.defines = defines;
+    build_property.lflags = lflags;
+    build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
+    build_property.postBuildSteps = postBuildSteps;
+    build_property.projecspecFileAction = "copy";
+    build_property.skipMakefileCcsBootimageGen = true;
+
+    return build_property;
+}
+
+module.exports = {
+    getComponentProperty,
+    getComponentBuildProperty,
+};

source/position_sense/hdsl/firmware/multichannel_ch2/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -0,0 +1,84 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectSpec>
+    <applicability>
+        <when>
+            <context
+                deviceFamily="PRU"
+                deviceId="AM243x_GP_EVM"
+            />
+        </when>
+    </applicability>
+
+    <project
+        title="Hdsl Master Multichannel Ch2"
+        name = "hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt"
+        products="com.ti.MOTOR_CONTROL_SDK_AMXXX;"
+        configurations="
+                Release,
+                Debug,
+        "
+        connection="TIXDS110_Connection.xml"
+        toolChain="TI"
+        cgtVersion="2.3.3"
+        device="AM243x_GP_EVM"
+        deviceCore="ICSS_G0_PRU_1"
+        ignoreDefaultDeviceSettings="true"
+        ignoreDefaultCCSSettings="true"
+        endianness="little"
+        outputFormat="ELF"
+        outputType="executable"
+
+        compilerBuildOptions="
+            -I${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware
+            -DICSSG0
+            -DPRU1
+            -DSLICE1
+            -DSOC_AM243X
+            -DPRU1
+            -DCHANNEL_2
+            -DICSS_G_V_1_0
+            -DFREERUN_300_MHZ
+            -DHDSL_MULTICHANNEL
+        "
+        linkerBuildOptions="
+            -m=hdsl_master_multichannel_ch2.${ConfigName}.map
+            --disable_auto_rts
+            --entry_point=main
+        "
+
+        postBuildStep="
+            $(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_TX_PRU -o hdsl_master_icssg_multichannel_ch2_bin.h hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out;  move  hdsl_master_icssg_multichannel_ch2_bin.h  ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_bin.h
+        "
+
+        description="A Hdsl Master Multichannel Ch2 FW project">
+
+        <configuration name="Release"
+            compilerBuildOptions="
+            "
+            linkerBuildOptions="
+            "
+        ></configuration>
+        <configuration name="Debug"
+            compilerBuildOptions="
+            "
+            linkerBuildOptions="
+            "
+        ></configuration>
+        <pathVariable name="MOTOR_CONTROL_SDK_PATH" path="${COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR}" scope="project" />
+        <file path="../../../../main.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../datalink.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../datalink_init.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../transport.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../hdsl_master_icssg_txpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am243x/HDSL_DESIGN.html"
+                openOnCreation="false" excludeFromBuild="false" targetName="README.html" action="link">
+        </file>
+    </project>
+</projectSpec>

source/position_sense/hdsl/firmware/multichannel_ch2/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -0,0 +1,88 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+#   Required input arguments :
+#   CCS_PROJECT_DEBUG=${CWD}   Use this input argument to include files from external paths 
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg
+CG_TOOL_ROOT := $(CGT_TI_PRU_PATH)
+RM := DEL /F
+RMDIR := RMDIR /S/Q
+
+# Add inputs and outputs from these tool invocations to the build variables
+CMD_SRCS += \
+hdsl_master_icssg_txpru.cmd \
+
+ASM_SRCS += \
+main.asm
+
+OBJS += \
+main.obj
+
+ASM_DEPS += \
+main.d
+
+OBJDIR := .
+
+FILES_PATH_common = \
+	.. \
+	../../.. \
+	../../../.. \
+
+FILES_PATH := $(FILES_PATH_common)
+
+vpath %.asm $(FILES_PATH)
+vpath %.obj $(OBJDIR)
+vpath %.cmd $(FILES_PATH)
+
+
+# Add inputs and outputs from these tool invocations to the build variables
+EXE_OUTPUTS += \
+hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out \
+
+EXE_OUTPUTS__QUOTED += \
+"hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" \
+
+BIN_OUTPUTS += \
+hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.hex \
+
+BIN_OUTPUTS__QUOTED += \
+"hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.hex" \
+
+# All Target
+all: $(OBJS) $(CMD_SRCS)
+	@$(MAKE) --no-print-directory -Onone "hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out"
+
+# Each subdirectory must supply rules for building sources it contributes
+$(OBJDIR)/$(OBJS): $(ASM_SRCS) 
+	@echo 'Building file: "$<"'
+	@echo 'Invoking: PRU Compiler'
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_2 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	@echo 'Finished building: "$<"'
+	@echo ' '
+
+# Tool invocations
+hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
+	@echo 'Building target: "$@"'
+	@echo 'Invoking: PRU Linker'
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_2 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	@echo 'Finished building target: "$@"'
+	@echo ' '
+	@$(MAKE) --no-print-directory post-build
+
+# To clean generated files
+clean:
+	-$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED)
+	-$(RM) "main.obj"
+	-$(RM) "main.d"
+	-@echo 'Finished clean'
+	-@echo ' '
+
+post-build:
+		-$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_TX_PRU -o hdsl_master_icssg_multichannel_ch2_bin.h hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out
+		-  move  hdsl_master_icssg_multichannel_ch2_bin.h  ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_bin.h
+	-@echo ' '
+
+.PHONY: all clean

source/position_sense/hdsl/firmware/multichannel_ch2/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile_projectspec

@@ -0,0 +1,20 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=hdsl_master_multichannel_ch2_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
+
+all:
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+	$(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full

source/position_sense/hdsl/firmware/multichannel_ch2/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -0,0 +1,84 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectSpec>
+    <applicability>
+        <when>
+            <context
+                deviceFamily="PRU"
+                deviceId="AM64x_GP_EVM"
+            />
+        </when>
+    </applicability>
+
+    <project
+        title="Hdsl Master Multichannel Ch2"
+        name = "hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt"
+        products="com.ti.MOTOR_CONTROL_SDK_AMXXX;"
+        configurations="
+                Release,
+                Debug,
+        "
+        connection="TIXDS110_Connection.xml"
+        toolChain="TI"
+        cgtVersion="2.3.3"
+        device="AM64x_GP_EVM"
+        deviceCore="ICSS_G0_PRU_1"
+        ignoreDefaultDeviceSettings="true"
+        ignoreDefaultCCSSettings="true"
+        endianness="little"
+        outputFormat="ELF"
+        outputType="executable"
+
+        compilerBuildOptions="
+            -I${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware
+            -DICSSG0
+            -DPRU1
+            -DSLICE1
+            -DSOC_AM64X
+            -DPRU1
+            -DCHANNEL_2
+            -DICSS_G_V_1_0
+            -DFREERUN_300_MHZ
+            -DHDSL_MULTICHANNEL
+        "
+        linkerBuildOptions="
+            -m=hdsl_master_multichannel_ch2.${ConfigName}.map
+            --disable_auto_rts
+            --entry_point=main
+        "
+
+        postBuildStep="
+            $(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_TX_PRU -o hdsl_master_icssg_multichannel_ch2_bin.h hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out;  move  hdsl_master_icssg_multichannel_ch2_bin.h  ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_bin.h
+        "
+
+        description="A Hdsl Master Multichannel Ch2 FW project">
+
+        <configuration name="Release"
+            compilerBuildOptions="
+            "
+            linkerBuildOptions="
+            "
+        ></configuration>
+        <configuration name="Debug"
+            compilerBuildOptions="
+            "
+            linkerBuildOptions="
+            "
+        ></configuration>
+        <pathVariable name="MOTOR_CONTROL_SDK_PATH" path="${COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR}" scope="project" />
+        <file path="../../../../main.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../datalink.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../datalink_init.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../transport.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../hdsl_master_icssg_txpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am64x/HDSL_DESIGN.html"
+                openOnCreation="false" excludeFromBuild="false" targetName="README.html" action="link">
+        </file>
+    </project>
+</projectSpec>

source/position_sense/hdsl/firmware/multichannel_ch2/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -0,0 +1,88 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+#   Required input arguments :
+#   CCS_PROJECT_DEBUG=${CWD}   Use this input argument to include files from external paths 
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg
+CG_TOOL_ROOT := $(CGT_TI_PRU_PATH)
+RM := DEL /F
+RMDIR := RMDIR /S/Q
+
+# Add inputs and outputs from these tool invocations to the build variables
+CMD_SRCS += \
+hdsl_master_icssg_txpru.cmd \
+
+ASM_SRCS += \
+main.asm
+
+OBJS += \
+main.obj
+
+ASM_DEPS += \
+main.d
+
+OBJDIR := .
+
+FILES_PATH_common = \
+	.. \
+	../../.. \
+	../../../.. \
+
+FILES_PATH := $(FILES_PATH_common)
+
+vpath %.asm $(FILES_PATH)
+vpath %.obj $(OBJDIR)
+vpath %.cmd $(FILES_PATH)
+
+
+# Add inputs and outputs from these tool invocations to the build variables
+EXE_OUTPUTS += \
+hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out \
+
+EXE_OUTPUTS__QUOTED += \
+"hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" \
+
+BIN_OUTPUTS += \
+hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.hex \
+
+BIN_OUTPUTS__QUOTED += \
+"hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.hex" \
+
+# All Target
+all: $(OBJS) $(CMD_SRCS)
+	@$(MAKE) --no-print-directory -Onone "hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out"
+
+# Each subdirectory must supply rules for building sources it contributes
+$(OBJDIR)/$(OBJS): $(ASM_SRCS) 
+	@echo 'Building file: "$<"'
+	@echo 'Invoking: PRU Compiler'
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_2 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	@echo 'Finished building: "$<"'
+	@echo ' '
+
+# Tool invocations
+hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
+	@echo 'Building target: "$@"'
+	@echo 'Invoking: PRU Linker'
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_2 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	@echo 'Finished building target: "$@"'
+	@echo ' '
+	@$(MAKE) --no-print-directory post-build
+
+# To clean generated files
+clean:
+	-$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED)
+	-$(RM) "main.obj"
+	-$(RM) "main.d"
+	-@echo 'Finished clean'
+	-@echo ' '
+
+post-build:
+		-$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL2_0_TX_PRU -o hdsl_master_icssg_multichannel_ch2_bin.h hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out
+		-  move  hdsl_master_icssg_multichannel_ch2_bin.h  ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_bin.h
+	-@echo ' '
+
+.PHONY: all clean

source/position_sense/hdsl/firmware/multichannel_ch2/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile_projectspec

@@ -0,0 +1,20 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=hdsl_master_multichannel_ch2_am64x-evm_icssg0-pru1_fw_ti-pru-cgt
+
+all:
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+	$(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full

source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/.project/project.js

@@ -0,0 +1,14 @@
+function getComponentProperty(device)
+{
+    return require(`./project_${device}`).getComponentProperty();
+};
+
+function getComponentBuildProperty(buildOption)
+{
+    return require(`./project_${buildOption.device}`).getComponentBuildProperty(buildOption);
+};
+
+module.exports = {
+    getComponentProperty,
+    getComponentBuildProperty,
+};

source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/.project/project_am243x.js

@@ -0,0 +1,98 @@
+let path = require('path');
+
+let device = "am243x";
+
+const files = {
+    common: [
+        "main.asm",
+        "datalink.asm",
+        "datalink_init.asm",
+        "transport.asm",
+        "utils.asm",
+        "hdsl_master_icssg_txpru.cmd",
+    ],
+};
+
+/* Relative to where the makefile will be generated
+ * Typically at <example_folder>/<BOARD>/<core_os_combo>/<compiler>
+ */
+const filedirs = {
+    common: [
+        "..",       /* core_os_combo base */
+        "../../..", /* Example base */
+        "../../../..",
+    ],
+};
+
+const includes = {
+    common: [
+        "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware",
+    ],
+};
+
+const defines = {
+    common: [
+        "PRU1",
+        "CHANNEL_2",
+        "ICSS_G_V_1_0",
+        "SYNC_300_MHZ",
+        "HDSL_MULTICHANNEL",
+        "EXT_SYNC_ENABLE",
+    ],
+};
+
+const lflags = {
+    common: [
+        "--disable_auto_rts",
+        "--entry_point=main",
+    ],
+};
+
+let postBuildSteps = [
+    "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL_SYNC2_0_TX_PRU -o hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out;  move  hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h  ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h"
+];
+
+const readmeDoxygenPageTag = "HDSL_DESIGN";
+
+const buildOptionCombos = [
+    { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am243x-evm", os: "fw"},
+];
+
+function getComponentProperty() {
+    let property = {};
+
+    property.dirPath = path.resolve(__dirname, "..");
+    property.type = "executable";
+    property.makefile = "pru";
+    property.name = "hdsl_master_multichannel_ch2_sync_mode";
+    property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 300 MHz";
+    property.isInternal = false;
+    property.buildOptionCombos = buildOptionCombos;
+    property.pru_main_file = "main";
+    property.pru_linker_file = "hdsl_master_icssg_txpru";
+    property.isSkipTopLevelBuild = true;
+    property.skipUpdatingTirex = true;
+
+    return property;
+}
+
+function getComponentBuildProperty(buildOption) {
+    let build_property = {};
+
+    build_property.files = files;
+    build_property.filedirs = filedirs;
+    build_property.includes = includes;
+    build_property.defines = defines;
+    build_property.lflags = lflags;
+    build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
+    build_property.postBuildSteps = postBuildSteps;
+    build_property.projecspecFileAction = "copy";
+    build_property.skipMakefileCcsBootimageGen = true;
+
+    return build_property;
+}
+
+module.exports = {
+    getComponentProperty,
+    getComponentBuildProperty,
+};

source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/.project/project_am64x.js

@@ -0,0 +1,98 @@
+let path = require('path');
+
+let device = "am64x";
+
+const files = {
+    common: [
+        "main.asm",
+        "datalink.asm",
+        "datalink_init.asm",
+        "transport.asm",
+        "utils.asm",
+        "hdsl_master_icssg_txpru.cmd",
+    ],
+};
+
+/* Relative to where the makefile will be generated
+ * Typically at <example_folder>/<BOARD>/<core_os_combo>/<compiler>
+ */
+const filedirs = {
+    common: [
+        "..",       /* core_os_combo base */
+        "../../..", /* Example base */
+        "../../../..",
+    ],
+};
+
+const includes = {
+    common: [
+        "${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware",
+    ],
+};
+
+const defines = {
+    common: [
+        "PRU1",
+        "CHANNEL_2",
+        "ICSS_G_V_1_0",
+        "FREERUN_300_MHZ",
+        "HDSL_MULTICHANNEL",
+        "EXT_SYNC_ENABLE",
+    ],
+};
+
+const lflags = {
+    common: [
+        "--disable_auto_rts",
+        "--entry_point=main",
+    ],
+};
+
+let postBuildSteps = [
+    "$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL_SYNC2_0_TX_PRU -o hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out;  move  hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h  ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h"
+];
+
+const readmeDoxygenPageTag = "HDSL_DESIGN";
+
+const buildOptionCombos = [
+    { device: device, cpu: "icssg0-pru1", cgt: "ti-pru-cgt", board: "am64x-evm", os: "fw"},
+];
+
+function getComponentProperty() {
+    let property = {};
+
+    property.dirPath = path.resolve(__dirname, "..");
+    property.type = "executable";
+    property.makefile = "pru";
+    property.name = "hdsl_master_multichannel_ch2_sync_mode";
+    property.description = "HDSL Master Free Run Mode Firmware for PRU-ICSS running at 300 MHz";
+    property.isInternal = false;
+    property.buildOptionCombos = buildOptionCombos;
+    property.pru_main_file = "main";
+    property.pru_linker_file = "hdsl_master_icssg_txpru";
+    property.isSkipTopLevelBuild = true;
+    property.skipUpdatingTirex = true;
+
+    return property;
+}
+
+function getComponentBuildProperty(buildOption) {
+    let build_property = {};
+
+    build_property.files = files;
+    build_property.filedirs = filedirs;
+    build_property.includes = includes;
+    build_property.defines = defines;
+    build_property.lflags = lflags;
+    build_property.readmeDoxygenPageTag = readmeDoxygenPageTag;
+    build_property.postBuildSteps = postBuildSteps;
+    build_property.projecspecFileAction = "copy";
+    build_property.skipMakefileCcsBootimageGen = true;
+
+    return build_property;
+}
+
+module.exports = {
+    getComponentProperty,
+    getComponentBuildProperty,
+};

source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -0,0 +1,85 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectSpec>
+    <applicability>
+        <when>
+            <context
+                deviceFamily="PRU"
+                deviceId="AM243x_GP_EVM"
+            />
+        </when>
+    </applicability>
+
+    <project
+        title="Hdsl Master Multichannel Ch2 Sync Mode"
+        name = "hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt"
+        products="com.ti.MOTOR_CONTROL_SDK_AMXXX;"
+        configurations="
+                Release,
+                Debug,
+        "
+        connection="TIXDS110_Connection.xml"
+        toolChain="TI"
+        cgtVersion="2.3.3"
+        device="AM243x_GP_EVM"
+        deviceCore="ICSS_G0_PRU_1"
+        ignoreDefaultDeviceSettings="true"
+        ignoreDefaultCCSSettings="true"
+        endianness="little"
+        outputFormat="ELF"
+        outputType="executable"
+
+        compilerBuildOptions="
+            -I${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware
+            -DICSSG0
+            -DPRU1
+            -DSLICE1
+            -DSOC_AM243X
+            -DPRU1
+            -DCHANNEL_2
+            -DICSS_G_V_1_0
+            -DSYNC_300_MHZ
+            -DHDSL_MULTICHANNEL
+            -DEXT_SYNC_ENABLE
+        "
+        linkerBuildOptions="
+            -m=hdsl_master_multichannel_ch2_sync_mode.${ConfigName}.map
+            --disable_auto_rts
+            --entry_point=main
+        "
+
+        postBuildStep="
+            $(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL_SYNC2_0_TX_PRU -o hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out;  move  hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h  ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h
+        "
+
+        description="A Hdsl Master Multichannel Ch2 Sync Mode FW project">
+
+        <configuration name="Release"
+            compilerBuildOptions="
+            "
+            linkerBuildOptions="
+            "
+        ></configuration>
+        <configuration name="Debug"
+            compilerBuildOptions="
+            "
+            linkerBuildOptions="
+            "
+        ></configuration>
+        <pathVariable name="MOTOR_CONTROL_SDK_PATH" path="${COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR}" scope="project" />
+        <file path="../../../../main.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../datalink.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../datalink_init.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../transport.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../hdsl_master_icssg_txpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am243x/HDSL_DESIGN.html"
+                openOnCreation="false" excludeFromBuild="false" targetName="README.html" action="link">
+        </file>
+    </project>
+</projectSpec>

source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -0,0 +1,88 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+#   Required input arguments :
+#   CCS_PROJECT_DEBUG=${CWD}   Use this input argument to include files from external paths 
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg
+CG_TOOL_ROOT := $(CGT_TI_PRU_PATH)
+RM := DEL /F
+RMDIR := RMDIR /S/Q
+
+# Add inputs and outputs from these tool invocations to the build variables
+CMD_SRCS += \
+hdsl_master_icssg_txpru.cmd \
+
+ASM_SRCS += \
+main.asm
+
+OBJS += \
+main.obj
+
+ASM_DEPS += \
+main.d
+
+OBJDIR := .
+
+FILES_PATH_common = \
+	.. \
+	../../.. \
+	../../../.. \
+
+FILES_PATH := $(FILES_PATH_common)
+
+vpath %.asm $(FILES_PATH)
+vpath %.obj $(OBJDIR)
+vpath %.cmd $(FILES_PATH)
+
+
+# Add inputs and outputs from these tool invocations to the build variables
+EXE_OUTPUTS += \
+hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out \
+
+EXE_OUTPUTS__QUOTED += \
+"hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" \
+
+BIN_OUTPUTS += \
+hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.hex \
+
+BIN_OUTPUTS__QUOTED += \
+"hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.hex" \
+
+# All Target
+all: $(OBJS) $(CMD_SRCS)
+	@$(MAKE) --no-print-directory -Onone "hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out"
+
+# Each subdirectory must supply rules for building sources it contributes
+$(OBJDIR)/$(OBJS): $(ASM_SRCS) 
+	@echo 'Building file: "$<"'
+	@echo 'Invoking: PRU Compiler'
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_2 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	@echo 'Finished building: "$<"'
+	@echo ' '
+
+# Tool invocations
+hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
+	@echo 'Building target: "$@"'
+	@echo 'Invoking: PRU Linker'
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_2 --define=ICSS_G_V_1_0 --define=SYNC_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	@echo 'Finished building target: "$@"'
+	@echo ' '
+	@$(MAKE) --no-print-directory post-build
+
+# To clean generated files
+clean:
+	-$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED)
+	-$(RM) "main.obj"
+	-$(RM) "main.d"
+	-@echo 'Finished clean'
+	-@echo ' '
+
+post-build:
+		-$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL_SYNC2_0_TX_PRU -o hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out
+		-  move  hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h  ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h
+	-@echo ' '
+
+.PHONY: all clean

source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile_projectspec

@@ -0,0 +1,20 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=hdsl_master_multichannel_ch2_sync_mode_am243x-evm_icssg0-pru1_fw_ti-pru-cgt
+
+all:
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+	$(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full

source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -0,0 +1,85 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectSpec>
+    <applicability>
+        <when>
+            <context
+                deviceFamily="PRU"
+                deviceId="AM64x_GP_EVM"
+            />
+        </when>
+    </applicability>
+
+    <project
+        title="Hdsl Master Multichannel Ch2 Sync Mode"
+        name = "hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt"
+        products="com.ti.MOTOR_CONTROL_SDK_AMXXX;"
+        configurations="
+                Release,
+                Debug,
+        "
+        connection="TIXDS110_Connection.xml"
+        toolChain="TI"
+        cgtVersion="2.3.3"
+        device="AM64x_GP_EVM"
+        deviceCore="ICSS_G0_PRU_1"
+        ignoreDefaultDeviceSettings="true"
+        ignoreDefaultCCSSettings="true"
+        endianness="little"
+        outputFormat="ELF"
+        outputType="executable"
+
+        compilerBuildOptions="
+            -I${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware
+            -DICSSG0
+            -DPRU1
+            -DSLICE1
+            -DSOC_AM64X
+            -DPRU1
+            -DCHANNEL_2
+            -DICSS_G_V_1_0
+            -DFREERUN_300_MHZ
+            -DHDSL_MULTICHANNEL
+            -DEXT_SYNC_ENABLE
+        "
+        linkerBuildOptions="
+            -m=hdsl_master_multichannel_ch2_sync_mode.${ConfigName}.map
+            --disable_auto_rts
+            --entry_point=main
+        "
+
+        postBuildStep="
+            $(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL_SYNC2_0_TX_PRU -o hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out;  move  hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h  ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h
+        "
+
+        description="A Hdsl Master Multichannel Ch2 Sync Mode FW project">
+
+        <configuration name="Release"
+            compilerBuildOptions="
+            "
+            linkerBuildOptions="
+            "
+        ></configuration>
+        <configuration name="Debug"
+            compilerBuildOptions="
+            "
+            linkerBuildOptions="
+            "
+        ></configuration>
+        <pathVariable name="MOTOR_CONTROL_SDK_PATH" path="${COM_TI_MOTOR_CONTROL_SDK_AMXXX_INSTALL_DIR}" scope="project" />
+        <file path="../../../../main.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../datalink.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../datalink_init.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../transport.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="../../../../hdsl_master_icssg_txpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
+        </file>
+        <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am64x/HDSL_DESIGN.html"
+                openOnCreation="false" excludeFromBuild="false" targetName="README.html" action="link">
+        </file>
+    </project>
+</projectSpec>

source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -0,0 +1,88 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+#   Required input arguments :
+#   CCS_PROJECT_DEBUG=${CWD}   Use this input argument to include files from external paths 
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+SYSCFG_DIR := $(CCS_PROJECT_DEBUG)/syscfg
+CG_TOOL_ROOT := $(CGT_TI_PRU_PATH)
+RM := DEL /F
+RMDIR := RMDIR /S/Q
+
+# Add inputs and outputs from these tool invocations to the build variables
+CMD_SRCS += \
+hdsl_master_icssg_txpru.cmd \
+
+ASM_SRCS += \
+main.asm
+
+OBJS += \
+main.obj
+
+ASM_DEPS += \
+main.d
+
+OBJDIR := .
+
+FILES_PATH_common = \
+	.. \
+	../../.. \
+	../../../.. \
+
+FILES_PATH := $(FILES_PATH_common)
+
+vpath %.asm $(FILES_PATH)
+vpath %.obj $(OBJDIR)
+vpath %.cmd $(FILES_PATH)
+
+
+# Add inputs and outputs from these tool invocations to the build variables
+EXE_OUTPUTS += \
+hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out \
+
+EXE_OUTPUTS__QUOTED += \
+"hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" \
+
+BIN_OUTPUTS += \
+hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.hex \
+
+BIN_OUTPUTS__QUOTED += \
+"hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.hex" \
+
+# All Target
+all: $(OBJS) $(CMD_SRCS)
+	@$(MAKE) --no-print-directory -Onone "hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out"
+
+# Each subdirectory must supply rules for building sources it contributes
+$(OBJDIR)/$(OBJS): $(ASM_SRCS) 
+	@echo 'Building file: "$<"'
+	@echo 'Invoking: PRU Compiler'
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_2 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	@echo 'Finished building: "$<"'
+	@echo ' '
+
+# Tool invocations
+hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
+	@echo 'Building target: "$@"'
+	@echo 'Invoking: PRU Linker'
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_2 --define=ICSS_G_V_1_0 --define=FREERUN_300_MHZ --define=HDSL_MULTICHANNEL --define=EXT_SYNC_ENABLE  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	@echo 'Finished building target: "$@"'
+	@echo ' '
+	@$(MAKE) --no-print-directory post-build
+
+# To clean generated files
+clean:
+	-$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED)
+	-$(RM) "main.obj"
+	-$(RM) "main.d"
+	-@echo 'Finished clean'
+	-@echo ' '
+
+post-build:
+		-$(CG_TOOL_ROOT)/bin/hexpru.exe --diag_wrap=off --array --array:name_prefix=Hiperface_DSL_SYNC2_0_TX_PRU -o hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out
+		-  move  hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h  ${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware/hdsl_master_icssg_multichannel_ch2_sync_mode_bin.h
+	-@echo ' '
+
+.PHONY: all clean

source/position_sense/hdsl/firmware/multichannel_ch2_sync_mode/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile_projectspec

@@ -0,0 +1,20 @@
+#
+# Auto generated makefile
+#
+
+export MOTOR_CONTROL_SDK_PATH?=$(abspath ../../../../../../../..)
+include $(MOTOR_CONTROL_SDK_PATH)/imports.mak
+
+PROFILE?=Release
+
+PROJECT_NAME=hdsl_master_multichannel_ch2_sync_mode_am64x-evm_icssg0-pru1_fw_ti-pru-cgt
+
+all:
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE)
+
+clean:
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectBuild -ccs.projects $(PROJECT_NAME) -ccs.configuration $(PROFILE) -ccs.clean
+
+export:
+	$(MKDIR) $(MOTOR_CONTROL_SDK_PATH)/ccs_projects
+	$(CCS_ECLIPSE) -noSplash -data $(MOTOR_CONTROL_SDK_PATH)/ccs_projects -application com.ti.ccstudio.apps.projectCreate -ccs.projectSpec example.projectspec -ccs.overwrite full

source/position_sense/hdsl/firmware/sync_225_mhz/.project/project_am243x.js

@@ -9,7 +9,6 @@ const files = {
         "datalink_init.asm",
         "transport.asm",
         "utils.asm",
-        "hdsl_master_icssg_hexpru.cmd",
         "hdsl_master_icssg.cmd",
     ],
 };
@@ -33,7 +32,6 @@ const includes = {
 
 const defines = {
     common: [
-        "icss1",
         "PRU1",
         "CHANNEL_0",
         "EXT_SYNC_ENABLE",

source/position_sense/hdsl/firmware/sync_225_mhz/.project/project_am64x.js

@@ -9,7 +9,6 @@ const files = {
         "datalink_init.asm",
         "transport.asm",
         "utils.asm",
-        "hdsl_master_icssg_hexpru.cmd",
         "hdsl_master_icssg.cmd",
     ],
 };
@@ -33,7 +32,6 @@ const includes = {
 
 const defines = {
     common: [
-        "icss1",
         "PRU1",
         "CHANNEL_0",
         "EXT_SYNC_ENABLE",

source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -34,7 +34,6 @@
             -DPRU1
             -DSLICE1
             -DSOC_AM243X
-            -Dicss1
             -DPRU1
             -DCHANNEL_0
             -DEXT_SYNC_ENABLE
@@ -75,8 +74,6 @@
         </file>
         <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
-        <file path="../../../../hdsl_master_icssg_hexpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
-        </file>
         <file path="../../../../hdsl_master_icssg.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
         <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am243x/HDSL_DESIGN.html"

source/position_sense/hdsl/firmware/sync_225_mhz/am243x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -59,7 +59,7 @@ all: $(OBJS) $(CMD_SRCS)
 $(OBJDIR)/$(OBJS): $(ASM_SRCS) 
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: PRU Compiler'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=EXT_SYNC_ENABLE --define=ICSS_G_V_1_0 --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_0 --define=EXT_SYNC_ENABLE --define=ICSS_G_V_1_0 --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
@@ -67,7 +67,7 @@ $(OBJDIR)/$(OBJS): $(ASM_SRCS)
 hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
 	@echo 'Building target: "$@"'
 	@echo 'Invoking: PRU Linker'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=EXT_SYNC_ENABLE --define=ICSS_G_V_1_0  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM243X --define=PRU1 --define=CHANNEL_0 --define=EXT_SYNC_ENABLE --define=ICSS_G_V_1_0  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_sync_225_mhz_am243x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
 	@echo 'Finished building target: "$@"'
 	@echo ' '
 	@$(MAKE) --no-print-directory post-build

source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/example.projectspec

@@ -34,7 +34,6 @@
             -DPRU1
             -DSLICE1
             -DSOC_AM64X
-            -Dicss1
             -DPRU1
             -DCHANNEL_0
             -DEXT_SYNC_ENABLE
@@ -75,8 +74,6 @@
         </file>
         <file path="../../../../utils.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
-        <file path="../../../../hdsl_master_icssg_hexpru.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
-        </file>
         <file path="../../../../hdsl_master_icssg.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
         </file>
         <file path="${MOTOR_CONTROL_SDK_PATH}/docs/api_guide_am64x/HDSL_DESIGN.html"

source/position_sense/hdsl/firmware/sync_225_mhz/am64x-evm/icssg0-pru1_fw/ti-pru-cgt/makefile

@@ -59,7 +59,7 @@ all: $(OBJS) $(CMD_SRCS)
 $(OBJDIR)/$(OBJS): $(ASM_SRCS) 
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: PRU Compiler'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=EXT_SYNC_ENABLE --define=ICSS_G_V_1_0 --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_0 --define=EXT_SYNC_ENABLE --define=ICSS_G_V_1_0 --include_path="$(SYSCFG_DIR)" --include_path="${MOTOR_CONTROL_SDK_PATH}/source/position_sense/hdsl/firmware"  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little --preproc_with_compile --preproc_dependency="$(basename $(<F)).d_raw" "$<"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
@@ -67,7 +67,7 @@ $(OBJDIR)/$(OBJS): $(ASM_SRCS)
 hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out: $(OBJS) $(CMD_SRCS)
 	@echo 'Building target: "$@"'
 	@echo 'Invoking: PRU Linker'
-	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=icss1 --define=PRU1 --define=CHANNEL_0 --define=EXT_SYNC_ENABLE --define=ICSS_G_V_1_0  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
+	"$(CGT_TI_PRU_PATH)/bin/clpru" -DICSSG0 -DPRU1 -DSLICE1 --define=SOC_AM64X --define=PRU1 --define=CHANNEL_0 --define=EXT_SYNC_ENABLE --define=ICSS_G_V_1_0  --define=_DEBUG_=1 -g --diag_warning=225 --diag_wrap=off --display_error_number --endian=little -z -m"hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.map" --disable_auto_rts   --diag_wrap=off --display_error_number --warn_sections --xml_link_info="hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt_linkInfo.xml" --rom_model -o "hdsl_master_sync_225_mhz_am64x-evm_icssg0-pru1_fw_ti-pru-cgt.out" $^
 	@echo 'Finished building target: "$@"'
 	@echo ' '
 	@$(MAKE) --no-print-directory post-build

source/position_sense/hdsl/firmware/transport.asm

@@ -52,7 +52,6 @@
 	.global transport_layer_send_msg
 	;.global transport_layer_assemble_msg
 	.global transport_layer_recv_msg
-	.global transport_init
 	.global transport_on_h_frame
 	.global transport_on_v_frame
 	.global transport_on_v_frame_2
@@ -63,207 +62,9 @@
 	.global calc_16bit_crc
 	.global calc_fastpos
 
+	; part 2 code starts here
 
-	.sect ".text"
+	.sect	".text:part2"
-;Initialize transport layer here
-transport_init:
-;initialize velocity to 0
-;initializing fasp pos as (need to be replaced with first vertical position)
-	zero		&SPEED, (4*2)
-;resert short msg ctrl
-	ldi		REG_TMP0.b0, 0x3f
-	sbco		&REG_TMP0.b0, MASTER_REGS_CONST, SLAVE_REG_CTRL, 1
-;initialize NUM_VERT_FRAMES, MEAN_MISMTACH, MISMATCH, NUM_VERT_ERR
-	;sbco		&SPEED, MASTER_REGS_CONST, MISMATCH0, 4
-;initialize acc_err_cnt to 0
-	sbco		&SPEED.b0, MASTER_REGS_CONST, ACC_ERR_CNT, 1
-	sbco		&SPEED.b0, MASTER_REGS_CONST, POS4, 8
-;reset rel. pos
-	sbco		&SPEED, MASTER_REGS_CONST, REL_POS0, 4
-transport_init_abs_err_loop:
-	zero		&DELTA_ACC0, 12
-	ldi 	REG_TMP0.b0, 0
-	sbco 	&REG_TMP0.b0, MASTER_REGS_CONST, ALIGN_PH, 1
-exit_transport_init:
-;return back to datalink
-	RET
-;--------------------------------------------------
-;v_frame calculations
-;102+20=122 cycles
-;extracts safe position
-;verifies fast position
-;NOT allowed to use REG_TMP11
-;--------------------------------------------------
-transport_on_v_frame:
-;save REG_FNC.w0 content
-	mov		REG_TMP11.w1, REG_FNC.w0
-;inc NUM_VERT_FRAMES -> could be replaced with PA STATS on ICSS_G
-;Not required as it's not part of SICK IP requirement.
-    .if 0
-	lbco	&REG_TMP1, MASTER_REGS_CONST, NUM_VERT_FRAMES0, 4
-	add		REG_TMP1, REG_TMP1, 1
-	sbco	&REG_TMP1, MASTER_REGS_CONST, NUM_VERT_FRAMES0, 4
-    .endif
-; clear VPOS_VALID
-    zero    &REG_TMP0.b0, 1
-	sbco	&REG_TMP0.b0, MASTER_REGS_CONST, VPOS_VALID, 1
-
-;store CRC in Master  Registers
-	mov		REG_TMP1.b0, VERT_L.b1
-	mov		REG_TMP1.b1, VERT_L.b0
-; Store the required data for vertical channel in temporary memory.
-; It will be stored to DMEM in transport_on_v_frame_2
-	sbco		&REG_TMP1, MASTER_REGS_CONST, VPOSCRC_TEMP, 2
-;transmission error?
-	qbbs		transport_on_v_frame_dont_update_qm, H_FRAME.flags, FLAG_ERR_VERT
-    lbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
-    and         REG_TMP2.b0, REG_TMP2.b0, (~((1<<ONLINE_STATUS_1_SCE) | (1<<ONLINE_STATUS_1_VPOS)) & 0xFF)
-;checking for crc error
-	qbeq		check_for_slave_error_on_v_frame, CRC_VERT, 0
-; Set EVENT_S_SCE in EVENT register
-	lbco		&REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
-	set		REG_TMP0.b0, REG_TMP0.b0, EVENT_S_SCE
-;save events
-	sbco		&REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1
-	qbbc		update_events_no_int4, REG_TMP0.b1, EVENT_S_SCE
-; generate interrupt_s
-	ldi		r31.w0, PRU0_ARM_IRQ4
-update_events_no_int4:
-; Set ONLINE_STATUS_1_SCE in ONLINE_STATUS_1 register
-    set         REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_1_SCE
-    sbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
-	QM_SUB		6
-transport_on_v_frame_dont_update_qm:
-;update CRC error count
-	.if 0
-	lbco		&REG_TMP1, MASTER_REGS_CONST, NUM_VERT_ERR0, 4
-	add		REG_TMP1, REG_TMP1, 1
-	sbco		&REG_TMP1, MASTER_REGS_CONST, NUM_VERT_ERR0, 4
-	.endif
-	qba		transport_on_v_frame_exit
-check_for_slave_error_on_v_frame:
-
-;CRC was correct -> add 1 to QM
-;Note: QM_ADD uses REG_TMP1
-	QM_ADD		1
-;check for special character: K29.7 is sent in first byte of vertical channel if slave error occured
-	qbne		transport_on_v_frame_check_pos, VERT_H.b3, K29_7
-; Set EVENT_S_VPOS in EVENT register, due to encoder internal error
-	lbco		&REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
-	set		REG_TMP0.b0, REG_TMP0.b0, EVENT_S_VPOS
-;save events
-	sbco		&REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1
-	qbbc		update_events_no_int5, REG_TMP0.b1, EVENT_S_VPOS
-; generate interrupt_s
-	ldi		r31.w0, PRU0_ARM_IRQ4
-update_events_no_int5:
-; Set ONLINE_STATUS_1_VPOS in ONLINE_STATUS_1 register
-    set         REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_1_VPOS
-    sbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
-	qba		transport_on_v_frame_exit
-transport_on_v_frame_check_pos:
-
-    .if $defined("HDSL_MULTICHANNEL")
-    CALL2 WAIT_TX_FIFO_FREE
-    LOOP push_1B,3
-	PUSH_FIFO_CONST  0xff
-push_1B:
-    .endif
-
-	sbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
-	lsl		REG_TMP2, CHANNEL.ch_verth, 8
-	mov		REG_TMP2.b0, VERT_L.b3
-;first V-Frame? -> update FAST POS with SAFE POS
-transport_on_v_frame_not_first:
-;check for LAST FAST POS and SAFE POS mismatch
-
-	lbco		&REG_TMP0.b0, MASTER_REGS_CONST, LAST_FAST_POS0, SIZE_FAST_POS
-	sub		REG_TMP1.w0, VERT_L.w2, REG_TMP0.w0
-	sub		REG_TMP1.w2, VERT_H.w0, REG_TMP0.w2
-	qble 	no_sub_carry, VERT_L.w2, REG_TMP0.w0
-; if carry is needed, subtract 1 separately
-	sub		REG_TMP1.w2, REG_TMP1.w2, 1
-no_sub_carry:
-	mov		REG_TMP2, REG_TMP1
-;check if diff is neg,
-	qbbc		transport_on_v_frame_diff_pos, REG_TMP2, 31
-	not		REG_TMP2, REG_TMP2
-	add		REG_TMP2, REG_TMP2, 1
-transport_on_v_frame_diff_pos:
-
-
-
-;check for diff. is 0 -> estimate if not
-	qbne		transport_on_v_frame_estimate, REG_TMP1, 0
-	qbne		transport_on_v_frame_estimate, VERT_H.b2, FAST_POSL
-
-;reset ALIGN_PH
-	ldi 	REG_TMP2.b0, 0
-	sbco 	&REG_TMP2.b0, MASTER_REGS_CONST, ALIGN_PH, 1
-	qba		transport_on_v_frame_no_pos_mismatch
-; estimate/correct
-transport_on_v_frame_estimate:
-	CALL1		estimator_fpos
-transport_on_v_frame_no_pos_mismatch:
-;store SAFE POS
-
-	mov		REG_TMP0.b0, VERT_H.b2
-	mov		REG_TMP0.b1, VERT_H.b1
-	mov		REG_TMP0.b2, VERT_H.b0
-	mov		REG_TMP0.b3, VERT_L.b3
-	mov		REG_TMP1.b0, VERT_L.b2
-
-; Store the required data for vertical channel in temporary memory.
-; It will be stored to DMEM in transport_on_v_frame_2
-	sbco		&REG_TMP0.b0, MASTER_REGS_CONST, VPOS_TEMP, 5
-
-; set VPOS_VALID
-    ldi    REG_TMP0.b0, 0x1
-	sbco	&REG_TMP0.b0, MASTER_REGS_CONST, VPOS_VALID, 1
-
-; Store the required data for secondary channel in temporary memory.
-; It will be processed in transport_on_v_frame_2
-
-; store H_FRAME.flags
-	sbco	&H_FRAME.flags, MASTER_REGS_CONST, H_FRAME_FLAGS_TEMP, 2
-; store CRC_SEC
-	sbco	&CRC_SEC, MASTER_REGS_CONST, CRC_SEC_TEMP, 2
-; store the 8 bytes from secondary channel
-	sbco	&R20, MASTER_REGS_CONST, VPOS2_TEMP, 8
-	jmp no_first_push_for_exit
-transport_on_v_frame_exit:
-;we are in RX0
-;reset rel. pos
-	loop Wait_and_Push_2_byte,2
-   	CALL2 WAIT_TX_FIFO_FREE
-	PUSH_FIFO_CONST  0xff
-Wait_and_Push_2_byte:
-
-	PUSH_FIFO_CONST  0xff
-
-no_first_push_for_exit:
-    .if $defined("HDSL_MULTICHANNEL")
-	qbeq			free_run_mode1, EXTRA_SIZE, 0
-	CALL2 WAIT_TX_FIFO_FREE
-	PUSH_FIFO_CONST		0xff
-	RESET_CYCLCNT
-free_run_mode1:
-	.endif
-	ldi		REG_TMP0, 0
-	sbco		&REG_TMP0, MASTER_REGS_CONST, REL_POS0, 4
-;store last FAST_POS
-	sbco		&FAST_POSL, MASTER_REGS_CONST, LAST_FAST_POS0, SIZE_FAST_POS
-
-; Store summary
-    sbco    &VERT_H.b3, MASTER_REGS_CONST, SAFE_SUM_TEMP, 1
-
-;restore REG_FNC.w0 content
-	mov		REG_FNC.w0, REG_TMP11.w1
-;reset vertical/secondary channel crc
-	ldi		CRC, 0
-;reset flags
-	and		H_FRAME_flags_l, H_FRAME_flags_l, FLAG_ERRORS
-	jmp		datalink_transport_on_v_frame_done
 
 ;----------------------------------------------------
 ;transport_on_v_frame_2
@@ -411,6 +212,293 @@ online_status_sum_save:
 	mov		REG_FNC.w0, REG_TMP11.w1
 
 	jmp		datalink_transport_on_v_frame_done_2
+
+;----------------------------------------------------
+;Function: transport_on_h_frame (RET_ADDR)
+;calculates the acceleration, velocity and fast position
+; 38+9+52 = 99 cycles
+;input:
+;output:
+;modifies:
+;----------------------------------------------------
+;TODO: reduce processing time by 24 cycles
+transport_on_h_frame:
+
+; Set POSTX to 0
+    ldi         REG_TMP0.b0, 0x0
+    sbco		&REG_TMP0.b0, MASTER_REGS_CONST, POSTX, 1
+
+;check for byte error in acceleration channel
+
+	qbbs		transport_acc_err_inc, H_FRAME.flags, FLAG_ERR_ACC
+;crc error verification
+	;CALL1		calc_acc_crc
+;5 bits CRC of acceleration channel are flipped -> flip back
+	xor		H_FRAME.acc, H_FRAME.acc, 0x1f
+	ldi		REG_TMP2, (LUT_CRC5+PDMEM00)
+	lbbo		&REG_TMP0.b1, REG_TMP2, H_FRAME_acc1, 1
+	lsl		REG_TMP0.b1, REG_TMP0.b1, 3
+	xor		REG_TMP0.b1, REG_TMP0.b1, H_FRAME_acc0
+	lbbo		&REG_FNC.b0, REG_TMP2, REG_TMP0.b1, 1
+	qbne		transport_acc_err_inc, REG_FNC.b0, 0
+;check for special character: K29.7 is sent two times if slave error occured
+	ldi		REG_TMP0.w0, DOUBLE_K29_7
+    qbne		delta_delta_position, H_FRAME.acc, REG_TMP0.w0
+transport_acc_err_inc:
+
+;update the acc_err_cnt register
+	lbco		&REG_TMP0.b0, MASTER_REGS_CONST, ACC_ERR_CNT, 1
+	add		REG_TMP0.b0, REG_TMP0.b0, 1
+	sbco		&REG_TMP0.b0, MASTER_REGS_CONST, ACC_ERR_CNT, 1
+;reset if it is too large
+	lbco		&REG_TMP0.b1, MASTER_REGS_CONST, ACC_ERR_CNT_THRESH, 1
+	qbgt		transport_on_h_frame_no_reset, REG_TMP0.b0, REG_TMP0.b1
+	jmp		datalink_abort
+transport_on_h_frame_no_reset:
+;save return addr
+
+	mov		REG_TMP11.w0, RET_ADDR0
+	;CALL		estimator_acc; Instead of calling the API, copy the code here to save PRU cycles.
+;----------------------------------------------------
+;Function: estimator_acc (RET_ADDR)
+;This function estimates the FPOS and VEL
+;15+15+22=52 cycles
+;input:
+;
+;output:
+;	FAST_POSH, FAST_POSL, SPEED
+;modifies:
+;	FAST_POSH, FAST_POSL, SPEED, REG_TMP1, REG_TMP0
+;----------------------------------------------------
+;Estimating the acceleration
+;ith acc = (delta_a4* 1 + delta_a3 * 2 + delta_a2 * 4 + delta_a1 * 8 + delta_a0 * 16) / 32
+	lsl	  	REG_TMP0.w0, DELTA_ACC3, 1
+	lsl		REG_TMP0.w2, DELTA_ACC2, 2
+	lsl		REG_TMP1.w0, DELTA_ACC1, 3
+	lsl		REG_TMP1.w2, DELTA_ACC0, 4
+	add		REG_TMP0.w0, REG_TMP0.w0, REG_TMP0.w2
+	add		REG_TMP1.w0, REG_TMP1.w2, REG_TMP1.w0
+	add		REG_TMP0.w0, REG_TMP0.w0, REG_TMP1.w0
+	add		REG_TMP0.w0, REG_TMP0.w0, DELTA_ACC4
+;divide with 32
+	lsr		REG_TMP0.w0, REG_TMP0.w0, 5
+;sign extend delta acceleration to 16 bit -> acc size
+	qbbc		estimator_acc_sign_extend_dacc1, REG_TMP0.w0, 10
+	or		REG_TMP0.b1, REG_TMP0.b1, 0xf8
+estimator_acc_sign_extend_dacc1:
+; TODO: calcuate MAXACC, cap acc
+;add estimated delta acc to LAST_ACC
+	add		REG_FNC.w0, LAST_ACC, REG_TMP0.w0
+;check if estimated acc is neg. or pos.
+	;CALL1		calc_speed; Instead of calling the API, copy the code here to save PRU cycles.
+;sign extend acceleration to  24 bit -> speed size
+	xor		REG_TMP0, REG_TMP0, REG_TMP0
+	qbbc		calc_speed_extend_acc1, REG_FNC.w0, 10
+	ldi		REG_TMP0.w1, 0xfff8
+calc_speed_extend_acc1:
+	or		REG_TMP0.w0, REG_TMP0.w0, REG_FNC.w0
+	add		SPEED.w0, SPEED.w0, REG_TMP0.w0
+	adc		SPEED.b2, SPEED.b2, REG_TMP0.b2
+;updating the delta acceleration regs
+	.if $defined("HDSL_MULTICHANNEL")
+	CALL2 WAIT_TX_FIFO_FREE
+	PUSH_FIFO_CONST  0x00
+	PUSH_FIFO_CONST  0x00
+	.endif
+	mov		DELTA_ACC4, DELTA_ACC3
+	mov		DELTA_ACC3, DELTA_ACC2
+	mov		DELTA_ACC2, DELTA_ACC1
+	mov		DELTA_ACC1, DELTA_ACC0
+	sub		DELTA_ACC0, REG_TMP0.w0, LAST_ACC
+	mov		LAST_ACC, REG_TMP0.w0
+
+    CALL1		calc_fastpos
+;restore return addr
+	mov		RET_ADDR0, REG_TMP11.w0
+; Moving the event and online register update during stuffing
+; Set EVENT_UPDATE_PENDING_POS to indicate a fast position data consistency error
+	lbco		&REG_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1
+	set         REG_TMP0.b0, REG_TMP0.w0, EVENT_UPDATE_PENDING_POS
+	sbco		&REG_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1
+	qba		transport_on_h_frame_exit
+delta_delta_position:
+
+;reset ACC_ERR_CNT
+	sbco		&REG_FNC.b0, MASTER_REGS_CONST, ACC_ERR_CNT, 1
+;shift out crc bits
+	lsr		REG_FNC.w0, H_FRAME.acc, 5
+; learn highest abs. acc
+	;CALL1		calc_speed; Instead of calling the API, copy the code here to save PRU cycles.
+;sign extend acceleration to  24 bit -> speed size
+	xor		REG_TMP0, REG_TMP0, REG_TMP0
+	qbbc		calc_speed_extend_acc0, REG_FNC.w0, 10
+	ldi		REG_TMP0.w1, 0xfff8
+calc_speed_extend_acc0:
+	or		REG_TMP0.w0, REG_TMP0.w0, REG_FNC.w0
+	add		SPEED.w0, SPEED.w0, REG_TMP0.w0
+	adc		SPEED.b2, SPEED.b2, REG_TMP0.b2
+;updating the delta acceleration regs
+	.if $defined("HDSL_MULTICHANNEL")
+	CALL2 WAIT_TX_FIFO_FREE
+	PUSH_FIFO_CONST  0x00
+	PUSH_FIFO_CONST  0x00
+	.endif
+	mov		DELTA_ACC4, DELTA_ACC3
+	mov		DELTA_ACC3, DELTA_ACC2
+	mov		DELTA_ACC2, DELTA_ACC1
+	mov		DELTA_ACC1, DELTA_ACC0
+	sub		DELTA_ACC0, REG_TMP0.w0, LAST_ACC
+	mov		LAST_ACC, REG_TMP0.w0
+
+	CALL1		calc_fastpos
+transport_on_h_frame_exit:
+;calculate rel. pos and store
+	lbco		&REG_TMP0, MASTER_REGS_CONST, REL_POS0, 4
+;sign extend speed to 32 bits and add it to REL_POS
+	mov		REG_TMP1, SPEED
+    ldi     REG_TMP1.b3, 0
+	qbbc	calc_relpos_extend_vel, SPEED, 23
+	ldi		REG_TMP1.b3, 0xff
+calc_relpos_extend_vel:
+	add		REG_TMP0.w0, REG_TMP0.w0, REG_TMP1.w0
+	adc		REG_TMP0.w2, REG_TMP0.w2, REG_TMP1.w2
+	sbco		&REG_TMP0, MASTER_REGS_CONST, REL_POS0, 4
+;store fast pos. and velocity
+    mov     REG_TMP0, FAST_POSH
+    mov     REG_TMP1, SPEED
+    xin     160, &REG_TMP0, 8
+	sbco	&REG_TMP0, MASTER_REGS_CONST, POS4, SIZE_FAST_POS+3
+; Set POSTX to 2
+    ldi         REG_TMP0.b0, 0x2
+    sbco		&REG_TMP0.b0, MASTER_REGS_CONST, POSTX, 1
+
+; Store PIPE data
+	sbco	&H_FRAME.pipe, MASTER_REGS_CONST, PIPE_D, 1
+
+; signal event mst_intr[0] and PRU0_ARM_IRQ3
+	ldi     r31.w0, 32+0
+	ldi     r31.w0, PRU0_ARM_IRQ3
+	RET
+
+;--------------------------------------------------------------------------------------------------
+;Function: calc_fastpos (RET_ADDR1)
+;This function sign extends speed and adds it to fast position
+;22 cycles
+;input:SPEED, FAST_POSH, FAST_POSL
+;
+;output: FAST_POSH, FAST_POSL
+;
+;modifies:FAST_POSH, FAST_POSL
+;
+;--------------------------------------------------------------------------------------------------
+calc_fastpos:
+;sign extend speed to NUM_POS_BITS=NUM_MT_BITS+NUM_ST_BITS and add it to FAST_POS
+	ldi		REG_TMP1.b0, 0
+	qbbc		calc_fastpos_extend_vel, SPEED, 23
+	ldi		REG_TMP1.b0, 0xff
+calc_fastpos_extend_vel:
+	mov		REG_TMP0, SPEED
+	mov		REG_TMP0.b3, REG_TMP1.b0
+;calculating fast position
+	add		FAST_POSL, FAST_POSL, REG_TMP0.b0
+	lsr		REG_TMP0, REG_TMP0, 8
+	mov		REG_TMP0.b3, REG_TMP1.b0
+	adc		FAST_POSH, FAST_POSH, REG_TMP0
+;load mask for fast position
+	lbco		&REG_TMP1, MASTER_REGS_CONST, MASK_POS, 4
+	and		FAST_POSH, FAST_POSH, REG_TMP1
+	RET1
+;--------------------------------------------------------------------------------------------------
+;Function: calc_speed (RET_ADDR1)
+;This function sign extends acceleration and adds it to speed
+;15 cycles
+;input:
+;	SPEED
+;	REG_FNC.w0: acceleration
+;
+;output: SPEED
+;
+;modifies: SPEED
+;
+;--------------------------------------------------------------------------------------------------
+calc_speed:
+;sign extend acceleration to  24 bit -> speed size
+	xor		REG_TMP0, REG_TMP0, REG_TMP0
+	qbbc		calc_speed_extend_acc, REG_FNC.w0, 10
+	ldi		REG_TMP0.w1, 0xfff8
+calc_speed_extend_acc:
+	or		REG_TMP0.w0, REG_TMP0.w0, REG_FNC.w0
+	add		SPEED.w0, SPEED.w0, REG_TMP0.w0
+	adc		SPEED.b2, SPEED.b2, REG_TMP0.b2
+;updating the delta acceleration regs
+	mov		DELTA_ACC4, DELTA_ACC3
+	mov		DELTA_ACC3, DELTA_ACC2
+	mov		DELTA_ACC2, DELTA_ACC1
+	mov		DELTA_ACC1, DELTA_ACC0
+	sub		DELTA_ACC0, REG_TMP0.w0, LAST_ACC
+	mov		LAST_ACC, REG_TMP0.w0
+	RET1
+
+;--------------------------------------------------------------------------------------------------
+;Function: store_error (RET_ADDR1)
+;Stores error in ring buffer
+;15 cycles
+;input:
+;	REG_FNC: error
+;output:
+;modifies:
+;--------------------------------------------------------------------------------------------------
+store_error:
+;load abs error ring buffer ptr.
+	;ldi		REG_TMP1, (PDMEM00+ABS_ERR_PTR)
+	;xor		REG_TMP0, REG_TMP0, REG_TMP0
+	;lbbo		&REG_TMP0, REG_TMP1, 0x00, ABS_ERR_PTR_SIZE
+;store error
+	;sbbo		&REG_FNC, REG_TMP0, 0x00, 4
+;update and store ptr
+	;add		REG_TMP0.w0, REG_TMP0.w0, 4
+	;ldi		REG_TMP0.w2, (PDMEM00+ABS_ERR_BUF+ABS_ERR_BUF_SIZE)
+	;qbgt		store_error_dont_reset_abs_err_ptr, REG_TMP0.w0, REG_TMP0.w2
+	;ldi		REG_TMP0.w0, (PDMEM00+ABS_ERR_BUF)
+store_error_dont_reset_abs_err_ptr:
+	;sbbo		&REG_TMP0.w0, REG_TMP1, 0x00, ABS_ERR_PTR_SIZE
+	;RET1
+;--------------------------------------------------------------------------------------------------
+;Function: calc_acc_crc (RET_ADD1)
+;This function checks the crc for the acceleration channel
+;11 cycles
+;input:
+;	H_frame.acc
+;output:
+;	REG_FNC.b0: 0 indicates that crc check was successfully
+;modifies:
+;	REG_TMP0, REG_FNC
+;--------------------------------------------------------------------------------------------------
+calc_acc_crc:
+;5 bits CRC of acceleration channel are flipped -> flip back
+	xor		H_FRAME.acc, H_FRAME.acc, 0x1f
+	ldi		REG_TMP2, (LUT_CRC5+PDMEM00)
+	lbbo		&REG_TMP0.b1, REG_TMP2, H_FRAME_acc1, 1
+	lsl		REG_TMP0.b1, REG_TMP0.b1, 3
+	xor		REG_TMP0.b1, REG_TMP0.b1, H_FRAME_acc0
+	lbbo		&REG_FNC.b0, REG_TMP2, REG_TMP0.b1, 1
+	RET1
+;--------------------------------------------------------------------------------------------------
+;Function: demp_data_symbols (RET_ADDR1)
+;Demaps data symbols (5bits) and converts them to data nibbles (4bits)
+;input:
+;	REG_FNC.b0: Number of data symbols
+;	r1.b1: source
+;	r1.b0: destination
+;output:
+;	*r1.b0[0:REG_FNC.b0]: demapped data
+;modifies:
+;--------------------------------------------------------------------------------------------------
+demap_data_symbols:
+
+; common code starts here
+	.sect ".text"
+
 ;----------------------------------------------------
 ;transport_layer_recv_msg
 ;Handles Hiperface DSL messages receiving
@@ -999,232 +1087,186 @@ transport_layer_pos_update_done:
     sbco        &REG_TMP1.b0, MASTER_REGS_CONST, ONLINE_STATUS_D_H, 1
 	jmp		transport_layer_send_msg_done
 
-;----------------------------------------------------
-;Function: transport_on_h_frame (RET_ADDR)
-;calculates the acceleration, velocity and fast position
-; 38+9+52 = 99 cycles
-;input:
-;output:
-;modifies:
-;----------------------------------------------------
-;TODO: reduce processing time by 24 cycles
-transport_on_h_frame:
 
-; Set POSTX to 0
-    ldi         REG_TMP0.b0, 0x0
-    sbco		&REG_TMP0.b0, MASTER_REGS_CONST, POSTX, 1
 
-;check for byte error in acceleration channel
+;--------------------------------------------------
+;v_frame calculations
+;102+20=122 cycles
+;extracts safe position
+;verifies fast position
+;NOT allowed to use REG_TMP11
+;--------------------------------------------------
+transport_on_v_frame:
+;save REG_FNC.w0 content
+	mov		REG_TMP11.w1, REG_FNC.w0
+;inc NUM_VERT_FRAMES -> could be replaced with PA STATS on ICSS_G
+    .if 0
+	lbco	&REG_TMP1, MASTER_REGS_CONST, NUM_VERT_FRAMES0, 4
+	add		REG_TMP1, REG_TMP1, 1
+	sbco	&REG_TMP1, MASTER_REGS_CONST, NUM_VERT_FRAMES0, 4
+    .endif
+; clear VPOS_VALID
+    zero    &REG_TMP0.b0, 1
+	sbco	&REG_TMP0.b0, MASTER_REGS_CONST, VPOS_VALID, 1
 
-	qbbs		transport_acc_err_inc, H_FRAME.flags, FLAG_ERR_ACC
+;store CRC in Master  Registers
-;crc error verification
+	mov		REG_TMP1.b0, VERT_L.b1
-	;CALL1		calc_acc_crc
+	mov		REG_TMP1.b1, VERT_L.b0
-;5 bits CRC of acceleration channel are flipped -> flip back
+; Store the required data for vertical channel in temporary memory.
-	xor		H_FRAME.acc, H_FRAME.acc, 0x1f
+; It will be stored to DMEM in transport_on_v_frame_2
-	ldi		REG_TMP2, (LUT_CRC5+PDMEM00)
+	sbco		&REG_TMP1, MASTER_REGS_CONST, VPOSCRC_TEMP, 2
-	lbbo		&REG_TMP0.b1, REG_TMP2, H_FRAME_acc1, 1
+;transmission error?
-	lsl		REG_TMP0.b1, REG_TMP0.b1, 3
+	qbbs		transport_on_v_frame_dont_update_qm, H_FRAME.flags, FLAG_ERR_VERT
-	xor		REG_TMP0.b1, REG_TMP0.b1, H_FRAME_acc0
+    lbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
-	lbbo		&REG_FNC.b0, REG_TMP2, REG_TMP0.b1, 1
+    and         REG_TMP2.b0, REG_TMP2.b0, (~((1<<ONLINE_STATUS_1_SCE) | (1<<ONLINE_STATUS_1_VPOS)) & 0xFF)
-	qbne		transport_acc_err_inc, REG_FNC.b0, 0
+;checking for crc error
-;check for special character: K29.7 is sent two times if slave error occured
+	qbeq		check_for_slave_error_on_v_frame, CRC_VERT, 0
-	ldi		REG_TMP0.w0, DOUBLE_K29_7
+; Set EVENT_S_SCE in EVENT register
-    qbne		delta_delta_position, H_FRAME.acc, REG_TMP0.w0
+	lbco		&REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
-transport_acc_err_inc:
+	set		REG_TMP0.b0, REG_TMP0.b0, EVENT_S_SCE
-
+;save events
-;update the acc_err_cnt register
+	sbco		&REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1
-	lbco		&REG_TMP0.b0, MASTER_REGS_CONST, ACC_ERR_CNT, 1
+	qbbc		update_events_no_int4, REG_TMP0.b1, EVENT_S_SCE
-	add		REG_TMP0.b0, REG_TMP0.b0, 1
+; generate interrupt_s
-	sbco		&REG_TMP0.b0, MASTER_REGS_CONST, ACC_ERR_CNT, 1
+	ldi		r31.w0, PRU0_ARM_IRQ4
-;reset if it is too large
+update_events_no_int4:
-	lbco		&REG_TMP0.b1, MASTER_REGS_CONST, ACC_ERR_CNT_THRESH, 1
+; Set ONLINE_STATUS_1_SCE in ONLINE_STATUS_1 register
-	qbgt		transport_on_h_frame_no_reset, REG_TMP0.b0, REG_TMP0.b1
+    set         REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_1_SCE
-	jmp		datalink_abort
+    sbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
-transport_on_h_frame_no_reset:
+	QM_SUB		6
-;save return addr
+transport_on_v_frame_dont_update_qm:
-
+;update CRC error count
-	mov		REG_TMP11.w0, RET_ADDR0
+	.if 0
-	;CALL		estimator_acc; Instead of calling the API, copy the code here to save PRU cycles.
+	lbco		&REG_TMP1, MASTER_REGS_CONST, NUM_VERT_ERR0, 4
-;----------------------------------------------------
+	add		REG_TMP1, REG_TMP1, 1
-;Function: estimator_acc (RET_ADDR)
+	sbco		&REG_TMP1, MASTER_REGS_CONST, NUM_VERT_ERR0, 4
-;This function estimates the FPOS and VEL
-;15+15+22=52 cycles
-;input:
-;
-;output:
-;	FAST_POSH, FAST_POSL, SPEED
-;modifies:
-;	FAST_POSH, FAST_POSL, SPEED, REG_TMP1, REG_TMP0
-;----------------------------------------------------
-;Estimating the acceleration
-;ith acc = (delta_a4* 1 + delta_a3 * 2 + delta_a2 * 4 + delta_a1 * 8 + delta_a0 * 16) / 32
-	lsl	  	REG_TMP0.w0, DELTA_ACC3, 1
-	lsl		REG_TMP0.w2, DELTA_ACC2, 2
-	lsl		REG_TMP1.w0, DELTA_ACC1, 3
-	lsl		REG_TMP1.w2, DELTA_ACC0, 4
-	add		REG_TMP0.w0, REG_TMP0.w0, REG_TMP0.w2
-	add		REG_TMP1.w0, REG_TMP1.w2, REG_TMP1.w0
-	add		REG_TMP0.w0, REG_TMP0.w0, REG_TMP1.w0
-	add		REG_TMP0.w0, REG_TMP0.w0, DELTA_ACC4
-;divide with 32
-	lsr		REG_TMP0.w0, REG_TMP0.w0, 5
-;sign extend delta acceleration to 16 bit -> acc size
-	qbbc		estimator_acc_sign_extend_dacc1, REG_TMP0.w0, 10
-	or		REG_TMP0.b1, REG_TMP0.b1, 0xf8
-estimator_acc_sign_extend_dacc1:
-; TODO: calcuate MAXACC, cap acc
-;add estimated delta acc to LAST_ACC
-	add		REG_FNC.w0, LAST_ACC, REG_TMP0.w0
-;check if estimated acc is neg. or pos.
-	;CALL1		calc_speed; Instead of calling the API, copy the code here to save PRU cycles.
-;sign extend acceleration to  24 bit -> speed size
-	xor		REG_TMP0, REG_TMP0, REG_TMP0
-	qbbc		calc_speed_extend_acc1, REG_FNC.w0, 10
-	ldi		REG_TMP0.w1, 0xfff8
-calc_speed_extend_acc1:
-	or		REG_TMP0.w0, REG_TMP0.w0, REG_FNC.w0
-	add		SPEED.w0, SPEED.w0, REG_TMP0.w0
-	adc		SPEED.b2, SPEED.b2, REG_TMP0.b2
-;updating the delta acceleration regs
-	.if $defined("HDSL_MULTICHANNEL")
-	CALL2 WAIT_TX_FIFO_FREE
-	PUSH_FIFO_CONST  0x00
-	PUSH_FIFO_CONST  0x00
 	.endif
-	mov		DELTA_ACC4, DELTA_ACC3
+	qba		transport_on_v_frame_exit
-	mov		DELTA_ACC3, DELTA_ACC2
+check_for_slave_error_on_v_frame:
-	mov		DELTA_ACC2, DELTA_ACC1
-	mov		DELTA_ACC1, DELTA_ACC0
-	sub		DELTA_ACC0, REG_TMP0.w0, LAST_ACC
-	mov		LAST_ACC, REG_TMP0.w0
 
-    CALL1		calc_fastpos
+;CRC was correct -> add 1 to QM
-;restore return addr
+;Note: QM_ADD uses REG_TMP1
-	mov		RET_ADDR0, REG_TMP11.w0
+	QM_ADD		1
-; Moving the event and online register update during stuffing
+;check for special character: K29.7 is sent in first byte of vertical channel if slave error occured
-; Set EVENT_UPDATE_PENDING_POS to indicate a fast position data consistency error
+	qbne		transport_on_v_frame_check_pos, VERT_H.b3, K29_7
-	lbco		&REG_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1
+; Set EVENT_S_VPOS in EVENT register, due to encoder internal error
-	set         REG_TMP0.b0, REG_TMP0.w0, EVENT_UPDATE_PENDING_POS
+	lbco		&REG_TMP0, MASTER_REGS_CONST, EVENT_S, 2
-	sbco		&REG_TMP0.b0, MASTER_REGS_CONST, EVENT_UPDATE_PENDING, 1
+	set		REG_TMP0.b0, REG_TMP0.b0, EVENT_S_VPOS
-	qba		transport_on_h_frame_exit
+;save events
-delta_delta_position:
+	sbco		&REG_TMP0.b0, MASTER_REGS_CONST, EVENT_S, 1
+	qbbc		update_events_no_int5, REG_TMP0.b1, EVENT_S_VPOS
+; generate interrupt_s
+	ldi		r31.w0, PRU0_ARM_IRQ4
+update_events_no_int5:
+; Set ONLINE_STATUS_1_VPOS in ONLINE_STATUS_1 register
+    set         REG_TMP2.b0, REG_TMP2.b0, ONLINE_STATUS_1_VPOS
+    sbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
+	qba		transport_on_v_frame_exit
+transport_on_v_frame_check_pos:
 
-;reset ACC_ERR_CNT
+    .if $defined("HDSL_MULTICHANNEL")
-	sbco		&REG_FNC.b0, MASTER_REGS_CONST, ACC_ERR_CNT, 1
+    CALL2 WAIT_TX_FIFO_FREE
-;shift out crc bits
+    LOOP push_1B,3
-	lsr		REG_FNC.w0, H_FRAME.acc, 5
+	PUSH_FIFO_CONST  0xff
-; learn highest abs. acc
+push_1B:
-	;CALL1		calc_speed; Instead of calling the API, copy the code here to save PRU cycles.
+    .endif
-;sign extend acceleration to  24 bit -> speed size
+
-	xor		REG_TMP0, REG_TMP0, REG_TMP0
+	sbco		&REG_TMP2.b0, MASTER_REGS_CONST, ONLINE_STATUS_1_H, 1
-	qbbc		calc_speed_extend_acc0, REG_FNC.w0, 10
+	lsl		REG_TMP2, CHANNEL.ch_verth, 8
-	ldi		REG_TMP0.w1, 0xfff8
+	mov		REG_TMP2.b0, VERT_L.b3
-calc_speed_extend_acc0:
+;first V-Frame? -> update FAST POS with SAFE POS
-	or		REG_TMP0.w0, REG_TMP0.w0, REG_FNC.w0
+transport_on_v_frame_not_first:
-	add		SPEED.w0, SPEED.w0, REG_TMP0.w0
+;check for LAST FAST POS and SAFE POS mismatch
-	adc		SPEED.b2, SPEED.b2, REG_TMP0.b2
+
-;updating the delta acceleration regs
+	lbco		&REG_TMP0.b0, MASTER_REGS_CONST, LAST_FAST_POS0, SIZE_FAST_POS
-	.if $defined("HDSL_MULTICHANNEL")
+	sub		REG_TMP1.w0, VERT_L.w2, REG_TMP0.w0
+	sub		REG_TMP1.w2, VERT_H.w0, REG_TMP0.w2
+	qble 	no_sub_carry, VERT_L.w2, REG_TMP0.w0
+; if carry is needed, subtract 1 separately
+	sub		REG_TMP1.w2, REG_TMP1.w2, 1
+no_sub_carry:
+	mov		REG_TMP2, REG_TMP1
+;check if diff is neg,
+	qbbc		transport_on_v_frame_diff_pos, REG_TMP2, 31
+	not		REG_TMP2, REG_TMP2
+	add		REG_TMP2, REG_TMP2, 1
+transport_on_v_frame_diff_pos:
+
+
+
+;check for diff. is 0 -> estimate if not
+	qbne		transport_on_v_frame_estimate, REG_TMP1, 0
+	qbne		transport_on_v_frame_estimate, VERT_H.b2, FAST_POSL
+
+;reset ALIGN_PH
+	ldi 	REG_TMP2.b0, 0
+	sbco 	&REG_TMP2.b0, MASTER_REGS_CONST, ALIGN_PH, 1
+	qba		transport_on_v_frame_no_pos_mismatch
+; estimate/correct
+transport_on_v_frame_estimate:
+	CALL1		estimator_fpos
+transport_on_v_frame_no_pos_mismatch:
+;store SAFE POS
+
+	mov		REG_TMP0.b0, VERT_H.b2
+	mov		REG_TMP0.b1, VERT_H.b1
+	mov		REG_TMP0.b2, VERT_H.b0
+	mov		REG_TMP0.b3, VERT_L.b3
+	mov		REG_TMP1.b0, VERT_L.b2
+
+; Store the required data for vertical channel in temporary memory.
+; It will be stored to DMEM in transport_on_v_frame_2
+	sbco		&REG_TMP0.b0, MASTER_REGS_CONST, VPOS_TEMP, 5
+
+; set VPOS_VALID
+    ldi    REG_TMP0.b0, 0x1
+	sbco	&REG_TMP0.b0, MASTER_REGS_CONST, VPOS_VALID, 1
+
+; Store the required data for secondary channel in temporary memory.
+; It will be processed in transport_on_v_frame_2
+
+; store H_FRAME.flags
+	sbco	&H_FRAME.flags, MASTER_REGS_CONST, H_FRAME_FLAGS_TEMP, 2
+; store CRC_SEC
+	sbco	&CRC_SEC, MASTER_REGS_CONST, CRC_SEC_TEMP, 2
+; store the 8 bytes from secondary channel
+	sbco	&R20, MASTER_REGS_CONST, VPOS2_TEMP, 8
+	jmp no_first_push_for_exit
+transport_on_v_frame_exit:
+;we are in RX0
+;reset rel. pos
+	loop Wait_and_Push_2_byte,2
+   	CALL2 WAIT_TX_FIFO_FREE
+	PUSH_FIFO_CONST  0xff
+Wait_and_Push_2_byte:
+
+	PUSH_FIFO_CONST  0xff
+
+no_first_push_for_exit:
+    .if $defined("HDSL_MULTICHANNEL")
+	qbeq			free_run_mode1, EXTRA_SIZE, 0
 	CALL2 WAIT_TX_FIFO_FREE
-	PUSH_FIFO_CONST  0x00
+	PUSH_FIFO_CONST		0xff
-	PUSH_FIFO_CONST  0x00
+	RESET_CYCLCNT
+free_run_mode1:
 	.endif
-	mov		DELTA_ACC4, DELTA_ACC3
+	ldi		REG_TMP0, 0
-	mov		DELTA_ACC3, DELTA_ACC2
-	mov		DELTA_ACC2, DELTA_ACC1
-	mov		DELTA_ACC1, DELTA_ACC0
-	sub		DELTA_ACC0, REG_TMP0.w0, LAST_ACC
-	mov		LAST_ACC, REG_TMP0.w0
-
-	CALL1		calc_fastpos
-transport_on_h_frame_exit:
-;calculate rel. pos and store
-	lbco		&REG_TMP0, MASTER_REGS_CONST, REL_POS0, 4
-;sign extend speed to 32 bits and add it to REL_POS
-	mov		REG_TMP1, SPEED
-    ldi     REG_TMP1.b3, 0
-	qbbc	calc_relpos_extend_vel, SPEED, 23
-	ldi		REG_TMP1.b3, 0xff
-calc_relpos_extend_vel:
-	add		REG_TMP0.w0, REG_TMP0.w0, REG_TMP1.w0
-	adc		REG_TMP0.w2, REG_TMP0.w2, REG_TMP1.w2
 	sbco		&REG_TMP0, MASTER_REGS_CONST, REL_POS0, 4
-;store fast pos. and velocity
+;store last FAST_POS
-    mov     REG_TMP0, FAST_POSH
+	sbco		&FAST_POSL, MASTER_REGS_CONST, LAST_FAST_POS0, SIZE_FAST_POS
-    mov     REG_TMP1, SPEED
-    xin     160, &REG_TMP0, 8
-	sbco	&REG_TMP0, MASTER_REGS_CONST, POS4, SIZE_FAST_POS+3
-; Set POSTX to 2
-    ldi         REG_TMP0.b0, 0x2
-    sbco		&REG_TMP0.b0, MASTER_REGS_CONST, POSTX, 1
 
-; Store PIPE data
+; Store summary
-	sbco	&H_FRAME.pipe, MASTER_REGS_CONST, PIPE_D, 1
+    sbco    &VERT_H.b3, MASTER_REGS_CONST, SAFE_SUM_TEMP, 1
 
-; signal event mst_intr[0] and PRU0_ARM_IRQ3
+;restore REG_FNC.w0 content
-	ldi     r31.w0, 32+0
+	mov		REG_FNC.w0, REG_TMP11.w1
-	ldi     r31.w0, PRU0_ARM_IRQ3
+;reset vertical/secondary channel crc
-	RET
+	ldi		CRC, 0
+;reset flags
+	and		H_FRAME_flags_l, H_FRAME_flags_l, FLAG_ERRORS
+	jmp		datalink_transport_on_v_frame_done
 
 ;--------------------------------------------------------------------------------------------------
-;Function: calc_fastpos (RET_ADDR1)
-;This function sign extends speed and adds it to fast position
-;22 cycles
-;input:SPEED, FAST_POSH, FAST_POSL
-;
-;output: FAST_POSH, FAST_POSL
-;
-;modifies:FAST_POSH, FAST_POSL
-;
-;--------------------------------------------------------------------------------------------------
-calc_fastpos:
-;sign extend speed to NUM_POS_BITS=NUM_MT_BITS+NUM_ST_BITS and add it to FAST_POS
-	ldi		REG_TMP1.b0, 0
-	qbbc		calc_fastpos_extend_vel, SPEED, 23
-	ldi		REG_TMP1.b0, 0xff
-calc_fastpos_extend_vel:
-	mov		REG_TMP0, SPEED
-	mov		REG_TMP0.b3, REG_TMP1.b0
-;calculating fast position
-	add		FAST_POSL, FAST_POSL, REG_TMP0.b0
-	lsr		REG_TMP0, REG_TMP0, 8
-	mov		REG_TMP0.b3, REG_TMP1.b0
-	adc		FAST_POSH, FAST_POSH, REG_TMP0
-;load mask for fast position
-	lbco		&REG_TMP1, MASTER_REGS_CONST, MASK_POS, 4
-	and		FAST_POSH, FAST_POSH, REG_TMP1
-	RET1
-;--------------------------------------------------------------------------------------------------
-;Function: calc_speed (RET_ADDR1)
-;This function sign extends acceleration and adds it to speed
-;15 cycles
-;input:
-;	SPEED
-;	REG_FNC.w0: acceleration
-;
-;output: SPEED
-;
-;modifies: SPEED
-;
-;--------------------------------------------------------------------------------------------------
-calc_speed:
-;sign extend acceleration to  24 bit -> speed size
-	xor		REG_TMP0, REG_TMP0, REG_TMP0
-	qbbc		calc_speed_extend_acc, REG_FNC.w0, 10
-	ldi		REG_TMP0.w1, 0xfff8
-calc_speed_extend_acc:
-	or		REG_TMP0.w0, REG_TMP0.w0, REG_FNC.w0
-	add		SPEED.w0, SPEED.w0, REG_TMP0.w0
-	adc		SPEED.b2, SPEED.b2, REG_TMP0.b2
-;updating the delta acceleration regs
-	mov		DELTA_ACC4, DELTA_ACC3
-	mov		DELTA_ACC3, DELTA_ACC2
-	mov		DELTA_ACC2, DELTA_ACC1
-	mov		DELTA_ACC1, DELTA_ACC0
-	sub		DELTA_ACC0, REG_TMP0.w0, LAST_ACC
-	mov		LAST_ACC, REG_TMP0.w0
-	RET1
-;--------------------------------------------------------------------------------------------------
 ;Function: estimator_fpos (RET_ADDR1)
 ;This function estimates fpos when vpos and fpos mismatch
 ;The FAST_POS will oscillate with a small error around the SAFE_POS
@@ -1277,59 +1319,3 @@ estimator_fpos_acc_sing_check_end:
 estimator_fpos_align_ph_not_2:
 	sbco 	&REG_TMP2.b0, MASTER_REGS_CONST, ALIGN_PH, 1
 	RET1
-;--------------------------------------------------------------------------------------------------
-;Function: store_error (RET_ADDR1)
-;Stores error in ring buffer
-;15 cycles
-;input:
-;	REG_FNC: error
-;output:
-;modifies:
-;--------------------------------------------------------------------------------------------------
-store_error:
-;load abs error ring buffer ptr.
-	;ldi		REG_TMP1, (PDMEM00+ABS_ERR_PTR)
-	;xor		REG_TMP0, REG_TMP0, REG_TMP0
-	;lbbo		&REG_TMP0, REG_TMP1, 0x00, ABS_ERR_PTR_SIZE
-;store error
-	;sbbo		&REG_FNC, REG_TMP0, 0x00, 4
-;update and store ptr
-	;add		REG_TMP0.w0, REG_TMP0.w0, 4
-	;ldi		REG_TMP0.w2, (PDMEM00+ABS_ERR_BUF+ABS_ERR_BUF_SIZE)
-	;qbgt		store_error_dont_reset_abs_err_ptr, REG_TMP0.w0, REG_TMP0.w2
-	;ldi		REG_TMP0.w0, (PDMEM00+ABS_ERR_BUF)
-store_error_dont_reset_abs_err_ptr:
-	;sbbo		&REG_TMP0.w0, REG_TMP1, 0x00, ABS_ERR_PTR_SIZE
-	;RET1
-;--------------------------------------------------------------------------------------------------
-;Function: calc_acc_crc (RET_ADD1)
-;This function checks the crc for the acceleration channel
-;11 cycles
-;input:
-;	H_frame.acc
-;output:
-;	REG_FNC.b0: 0 indicates that crc check was successfully
-;modifies:
-;	REG_TMP0, REG_FNC
-;--------------------------------------------------------------------------------------------------
-calc_acc_crc:
-;5 bits CRC of acceleration channel are flipped -> flip back
-	xor		H_FRAME.acc, H_FRAME.acc, 0x1f
-	ldi		REG_TMP2, (LUT_CRC5+PDMEM00)
-	lbbo		&REG_TMP0.b1, REG_TMP2, H_FRAME_acc1, 1
-	lsl		REG_TMP0.b1, REG_TMP0.b1, 3
-	xor		REG_TMP0.b1, REG_TMP0.b1, H_FRAME_acc0
-	lbbo		&REG_FNC.b0, REG_TMP2, REG_TMP0.b1, 1
-	RET1
-;--------------------------------------------------------------------------------------------------
-;Function: demp_data_symbols (RET_ADDR1)
-;Demaps data symbols (5bits) and converts them to data nibbles (4bits)
-;input:
-;	REG_FNC.b0: Number of data symbols
-;	r1.b1: source
-;	r1.b0: destination
-;output:
-;	*r1.b0[0:REG_FNC.b0]: demapped data
-;modifies:
-;--------------------------------------------------------------------------------------------------
-demap_data_symbols:

source/position_sense/hdsl/include/hdsl_drv.h

@@ -63,6 +63,12 @@ extern "C" {
 /*                           Macros & Typedefs                                */
 /* ========================================================================== */
 
+
+#define HDSL_MAX_CHANNELS           (3U)
+#define CHANNEL_0_ENABLED           (1<<0)
+#define CHANNEL_1_ENABLED           (1<<1)
+#define CHANNEL_2_ENABLED           (1<<2)
+
 /**
  *  \anchor HDSL_LongMessageAddrTypes
  *  \name HDSL Long Message Addressing Types
@@ -286,29 +292,47 @@ typedef struct HDSL_Config_s {
 } HDSL_Config;
 /** @} */
 
+/**
+ * \anchor  HDSL_CopyTable
+ * \name    HDSL Copy Table for overlay scheme used when channel 2 is enabled.
+ * @{
+ */
+
+typedef struct HDSL_CopyTable_s {
+    uint32_t reserved1;
+    uint32_t loadAddr1; /**< Load Address of Part 1 of firmware */
+    uint32_t runAddr1;  /**< Run Address of Part 1 of firmware */
+    uint32_t size1;     /**< Size of Part 1 of firmware */
+    uint32_t reserved2;
+    uint32_t loadAddr2; /**< Load Address of Part 2 of firmware */
+    uint32_t runAddr2;  /**< Run Address of Part 2 of firmware */
+    uint32_t size2;     /**< Size of Part 2 of firmware */
+} HDSL_CopyTable;
+/** @} */
+
 /* ========================================================================== */
 /*                       Function Declarations                                */
 /* ========================================================================== */
 /**
  *  \brief     enable load share mode for multi-channel HDSL
  *
- *  \param[in]  gPru_cfg    Cfg base register address
+ *  \param[in]  pruCfg    Cfg base register address
- *  \param[in]  PRU_SLICE   PRU slice, 1 for PRU1 and 0 for PRU0
+ *  \param[in]  pruSlice   PRU slice, 1 for PRU1 and 0 for PRU0
  *
  */
-void hdsl_enable_load_share_mode(void *gPru_cfg ,uint32_t  PRU_SLICE);
+void hdsl_enable_load_share_mode(void *pruCfg ,uint32_t pruSlice);
+
 /**
  *  \brief      Open HDSL handle for the specified core
  *              (interrupt mapping should already be completed)
  *
  *  \param[in]  icssgHandle PRUICSS_Handle for the ICSS instance
  *  \param[in]  icssCore    Core to map in ICSSG instance
- *  \param[in]  PRU_mode    0 for dissabled load share mode, 1 for enabled load share mode
+ *  \param[in]  pruMode    0 for load share mode disabled, 1 for load share mode enabled
  *  \retval     HDSL_Handle
  *
  */
-// HDSL_ICSSG0_INST, HDSL_ICSSG1_INST
+HDSL_Handle HDSL_open(PRUICSS_Handle icssgHandle, uint32_t icssCore, uint8_t pruMode);
-HDSL_Handle HDSL_open(PRUICSS_Handle icssgHandle, uint32_t icssCore,uint8_t PRU_mode);
 
 /**
  *  \brief      Initialize IEP and Use OCP as IEP CLK src
@@ -588,6 +612,29 @@ void* HDSL_get_src_loc(HDSL_Handle hdslHandle);
  */
 uint32_t HDSL_get_length(HDSL_Handle hdslHandle);
 
+/**
+ *  \brief      Configure the copy table entries for two overlayed firmware parts for channel 2
+ *
+ *  \param[in]  hdslHandle
+ *  \param[in]  copyTable
+ *
+ *  \return     SystemP_SUCCESS in case of success, SystemP_FAILURE in case of error
+ *
+ */
+int32_t HDSL_config_copy_table(HDSL_Handle hdslHandle, HDSL_CopyTable *copyTable);
+
+
+/**
+ *  \brief      Configure the channel mask
+ *
+ *  \param[in]  hdslHandle
+ *  \param[in]  channelMask
+ *
+ *  \return     SystemP_SUCCESS in case of success, SystemP_FAILURE in case of error
+ *
+ */
+int32_t HDSL_config_channel_mask(HDSL_Handle hdslHandle, uint8_t channelMask);
+
 #ifdef __cplusplus
 }
 #endif