643 lines
24 KiB
C
643 lines
24 KiB
C
//###########################################################################
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//
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// FILE: mpu.h
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//
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// TITLE: Driver for the memory protection unit (MPU).
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef MPU_H
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#define MPU_H
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//*****************************************************************************
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//
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// If building with a C++ compiler, make all of the definitions in this header
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// have a C binding.
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//
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//*****************************************************************************
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//*****************************************************************************
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//
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//! \addtogroup mpu_api MPU
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//! @{
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//
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//*****************************************************************************
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#include <stdbool.h>
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#include <stdint.h>
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#include "debug.h"
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#include "interrupt.h"
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#include "inc/hw_ints.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_nvic.h"
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#include "inc/hw_types.h"
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//*****************************************************************************
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//
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// Defines for the API.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Values that can be passed to MPU_enable() as config parameter.
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//
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//*****************************************************************************
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#define MPU_CONFIG_PRIV_DEFAULT 0x4U //!< Enable default memory map as bg
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//!< region for priv sw access.
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#define MPU_CONFIG_HARDFLT_NMI 0x2U //!< MPU is enabled during hard fault,
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//!< NMI and FAULTMASK handlers.
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#define MPU_CONFIG_NONE 0x0U //!< None of the above configurations.
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//*****************************************************************************
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//
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// Values that can be passed to MPU_setRegionAttributes() and
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// MPU_getRegionAttributes() as regionNum parameter.
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//
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//*****************************************************************************
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#define MPU_RGN_0 0x0U
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#define MPU_RGN_1 0x1U
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#define MPU_RGN_2 0x2U
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#define MPU_RGN_3 0x3U
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#define MPU_RGN_4 0x4U
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#define MPU_RGN_5 0x5U
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#define MPU_RGN_6 0x6U
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#define MPU_RGN_7 0x7U
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//*****************************************************************************
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//
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// Flags for the region size to be passed to MPU_setRegionAttributes().
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//
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//*****************************************************************************
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#define MPU_RGN_SIZE_32B (4U << 1U) //!< Region Size is 32-bytes
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#define MPU_RGN_SIZE_64B (5U << 1U) //!< Region Size is 64-bytes
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#define MPU_RGN_SIZE_128B (6U << 1U) //!< Region Size is 128-bytes
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#define MPU_RGN_SIZE_256B (7U << 1U) //!< Region Size is 256-bytes
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#define MPU_RGN_SIZE_512B (8U << 1U) //!< Region Size is 512-bytes
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#define MPU_RGN_SIZE_1K (9U << 1U) //!< Region Size is 1K-bytes
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#define MPU_RGN_SIZE_2K (10U << 1U) //!< Region Size is 2K-bytes
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#define MPU_RGN_SIZE_4K (11U << 1U) //!< Region Size is 4K-bytes
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#define MPU_RGN_SIZE_8K (12U << 1U) //!< Region Size is 8K-bytes
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#define MPU_RGN_SIZE_16K (13U << 1U) //!< Region Size is 16K-bytes
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#define MPU_RGN_SIZE_32K (14U << 1U) //!< Region Size is 32K-bytes
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#define MPU_RGN_SIZE_64K (15U << 1U) //!< Region Size is 64K-bytes
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#define MPU_RGN_SIZE_128K (16U << 1U) //!< Region Size is 128K-bytes
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#define MPU_RGN_SIZE_256K (17U << 1U) //!< Region Size is 256K-bytes
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#define MPU_RGN_SIZE_512K (18U << 1U) //!< Region Size is 512K-bytes
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#define MPU_RGN_SIZE_1M (19U << 1U) //!< Region Size is 1M-bytes
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#define MPU_RGN_SIZE_2M (20U << 1U) //!< Region Size is 2M-bytes
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#define MPU_RGN_SIZE_4M (21U << 1U) //!< Region Size is 4M-bytes
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#define MPU_RGN_SIZE_8M (22U << 1U) //!< Region Size is 8M-bytes
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#define MPU_RGN_SIZE_16M (23U << 1U) //!< Region Size is 16M-bytes
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#define MPU_RGN_SIZE_32M (24U << 1U) //!< Region Size is 32M-bytes
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#define MPU_RGN_SIZE_64M (25U << 1U) //!< Region Size is 64M-bytes
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#define MPU_RGN_SIZE_128M (26U << 1U) //!< Region Size is 128M-bytes
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#define MPU_RGN_SIZE_256M (27U << 1U) //!< Region Size is 256M-bytes
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#define MPU_RGN_SIZE_512M (28U << 1U) //!< Region Size is 512M-bytes
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#define MPU_RGN_SIZE_1G (29U << 1U) //!< Region Size is 1G-bytes
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#define MPU_RGN_SIZE_2G (30U << 1U) //!< Region Size is 2G-bytes
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#define MPU_RGN_SIZE_4G (31U << 1U) //!< Region Size is 4G-bytes
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//*****************************************************************************
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//
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// Flags for the permissions to be passed to MPU_setRegionAttributes().
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//
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//*****************************************************************************
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#define MPU_RGN_PERM_EXEC 0x00000000U //!< Inst. fetches are enabled
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#define MPU_RGN_PERM_NOEXEC 0x10000000U //!< Inst. fetches are disabled
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#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000U //!< No access to privileged &
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//!< unprivileged access
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#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000U //!< R/W to privileged sw, no
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//!< access to unprivileged sw
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#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000U //!< R/W access to priv sw, no
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//!< access to unpriv sw
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#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000U //!< R/W access to priv sw, R/W
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//!< access to unpriv sw
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#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000U //!< RO access to priv sw, no
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//!< access to unpriv sw
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#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000U //!< RO access to priv sw, RO
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//!< access to unpriv sw
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//*****************************************************************************
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//
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// Flags for the sub-region to be passed to MPU_setRegionAttributes().
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//
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//*****************************************************************************
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#define MPU_SUB_RGN_DISABLE_0 0x00000100U //!< Disable sub-region 0
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#define MPU_SUB_RGN_DISABLE_1 0x00000200U //!< Disable sub-region 1
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#define MPU_SUB_RGN_DISABLE_2 0x00000400U //!< Disable sub-region 2
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#define MPU_SUB_RGN_DISABLE_3 0x00000800U //!< Disable sub-region 3
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#define MPU_SUB_RGN_DISABLE_4 0x00001000U //!< Disable sub-region 4
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#define MPU_SUB_RGN_DISABLE_5 0x00002000U //!< Disable sub-region 5
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#define MPU_SUB_RGN_DISABLE_6 0x00004000U //!< Disable sub-region 6
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#define MPU_SUB_RGN_DISABLE_7 0x00008000U //!< Disable sub-region 7
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//*****************************************************************************
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//
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// Flags to enable or disable a region, to be passed to
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// MPU_setRegionAttributes().
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//
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//*****************************************************************************
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#define MPU_RGN_ENABLE 1U //!< Enable MPU Region
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#define MPU_RGN_DISABLE 0U //!< Disable MPU Region
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//*****************************************************************************
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//
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// Mask for MPU region attributes to be used by MPU_setRegionAttributes().
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//
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//*****************************************************************************
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#define MPU_RGN_CONFIG_M ((uint32_t)NVIC_MPU_RASR_ENABLE | \
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(uint32_t)NVIC_MPU_RASR_SIZE_M | \
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(uint32_t)NVIC_MPU_RASR_SRD_M | \
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(uint32_t)NVIC_MPU_RASR_B | \
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(uint32_t)NVIC_MPU_RASR_C | \
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(uint32_t)NVIC_MPU_RASR_S | \
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(uint32_t)NVIC_MPU_RASR_TEX_M | \
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(uint32_t)NVIC_MPU_RASR_AP_M | \
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(uint32_t)NVIC_MPU_RASR_XN)
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//*****************************************************************************
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//
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// API Function prototypes
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! Enables and configures the MPU for use.
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//!
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//! \param config is the logical OR of the possible configurations.
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//!
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//! This function enables the Cortex-M memory protection unit. It also
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//! configures the default behavior when in privileged mode and while handling
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//! a hard fault or NMI. Prior to enabling the MPU, at least one region must
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//! be set by calling MPU_setRegionAttributes() or else by enabling the default
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//! region for privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag
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//! to MPU_enable(). Once the MPU is enabled, a memory management fault is
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//! generated for memory access violations.
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//!
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//! The \e config parameter should be the logical OR of any of the
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//! following:
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//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in
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//! privileged mode and when no other regions are defined. If this option
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//! is not enabled, then there must be at least one valid region already
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//! defined when the MPU is enabled.
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//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI
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//! exception handler. If this option is not enabled, then the MPU is
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//! disabled while in one of these exception handlers and the default
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//! memory map is applied.
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//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case,
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//! no default memory map is provided in privileged mode, and the MPU is not
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//! enabled in the fault handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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MPU_enable(uint32_t config)
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{
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//
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// Check the arguments.
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//
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ASSERT((config & ~(MPU_CONFIG_PRIV_DEFAULT |
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MPU_CONFIG_HARDFLT_NMI)) == 0U);
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//
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// Set the MPU control bits according to the flags passed by the user,
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// and also set the enable bit.
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//
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HWREG(NVIC_BASE + NVIC_O_MPU_CTRL) |= (config | NVIC_MPU_CTRL_ENABLE);
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}
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//*****************************************************************************
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//
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//! Disables the MPU for use.
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//!
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//! \param None
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//!
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//! This function disables the Cortex-M memory protection unit. When the
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//! MPU is disabled, the default memory map is used and memory management
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//! faults are not generated.
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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MPU_disable(void)
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{
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//
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// Turn off the MPU enable bit.
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//
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HWREG(NVIC_BASE + NVIC_O_MPU_CTRL) &= ~NVIC_MPU_CTRL_ENABLE;
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}
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//*****************************************************************************
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//
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//! Gets the count of regions supported by the MPU.
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//!
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//! \param None
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//!
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//! This function is used to get the total number of regions that are supported
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//! by the MPU, including regions that are already programmed.
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//!
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//! \return The number of memory protection regions that are available
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//! for programming using MPU_setRegionAttributes().
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//
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//*****************************************************************************
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static inline uint32_t
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MPU_getRegionCount(void)
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{
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//
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// Read the DREGION field of the MPU type register and mask off
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// the bits of interest to get the count of regions.
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//
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return((HWREG(NVIC_BASE + NVIC_O_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M) >>
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NVIC_MPU_TYPE_DREGION_S);
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}
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//*****************************************************************************
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//
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//! Enables a specific region.
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//!
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//! \param regionNum is the region number to enable.
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//!
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//! This function is used to enable a memory protection region. The region
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//! should already be configured with the MPU_setRegionAttributes() function.
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//! Once enabled, the memory protection rules of the region are applied and
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//! access violations cause a memory management fault.
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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MPU_enableRegion(uint32_t regionNum)
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{
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//
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// Check the arguments.
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//
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ASSERT(regionNum < 8U);
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//
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// Select the region to modify.
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//
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HWREG(NVIC_BASE + NVIC_O_MPU_RNR) = (HWREG(NVIC_BASE + NVIC_O_MPU_RNR) &
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~NVIC_MPU_RNR_REGION_M) | regionNum;
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//
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// Modify the enable bit in the region attributes.
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//
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HWREG(NVIC_BASE + NVIC_O_MPU_RASR) |= NVIC_MPU_RASR_ENABLE;
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}
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//*****************************************************************************
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//
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//! Disables a specific region.
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//!
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//! \param regionNum is the region number to disable.
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//!
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//! This function is used to disable a previously enabled memory protection
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//! region. The region remains configured if it is not overwritten with
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//! another call to MPU_setRegionAttributes(), and can be enabled again by
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//! calling MPU_enableRegion().
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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MPU_disableRegion(uint32_t regionNum)
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{
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//
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// Check the arguments.
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//
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ASSERT(regionNum < 8U);
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//
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// Select the region to modify.
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//
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HWREG(NVIC_BASE + NVIC_O_MPU_RNR) = (HWREG(NVIC_BASE + NVIC_O_MPU_RNR) &
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~NVIC_MPU_RNR_REGION_M) | regionNum;
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//
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// Modify the enable bit in the region attributes.
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//
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HWREG(NVIC_BASE + NVIC_O_MPU_RASR) &= ~NVIC_MPU_RASR_ENABLE;
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}
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//*****************************************************************************
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//
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//! Sets up the access rules for a specific region.
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//!
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//! \param regionNum is the region number to set up.
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//! \param baseAddr is the base address of the region. It must be aligned
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//! according to the size of the region specified in attrFlags.
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//! \param attrFlags is a set of flags to define the attributes of the region.
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//!
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//! This function sets up the protection rules for a region. The region has
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//! a base address and a set of attributes including the size.
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//!
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//! The region number parameter, \e regionNum specifies the region number to be
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//! setup. Valid values for \e regionNum parameter are:
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//! - \b MPU_RGN_0
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//! - \b MPU_RGN_1
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//! - \b MPU_RGN_2
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//! - \b MPU_RGN_3
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//! - \b MPU_RGN_4
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//! - \b MPU_RGN_5
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//! - \b MPU_RGN_6
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//! - \b MPU_RGN_7
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//!
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//! The base address parameter, \e baseAddr, must be aligned according to the
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//! size, and the size must be a power of 2.
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//!
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//! The \e attrFlags parameter is the logical OR of all of the attributes
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//! of the region. It is a combination of choices for region size,
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//! execute permission, read/write permissions, disabled sub-regions,
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//! and a flag to determine if the region is enabled.
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//!
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//! The size flag determines the size of a region and must be one of the
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//! following:
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//! - \b MPU_RGN_SIZE_32B
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//! - \b MPU_RGN_SIZE_64B
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//! - \b MPU_RGN_SIZE_128B
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//! - \b MPU_RGN_SIZE_256B
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//! - \b MPU_RGN_SIZE_512B
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//! - \b MPU_RGN_SIZE_1K
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//! - \b MPU_RGN_SIZE_2K
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//! - \b MPU_RGN_SIZE_4K
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//! - \b MPU_RGN_SIZE_8K
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//! - \b MPU_RGN_SIZE_16K
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//! - \b MPU_RGN_SIZE_32K
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//! - \b MPU_RGN_SIZE_64K
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//! - \b MPU_RGN_SIZE_128K
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//! - \b MPU_RGN_SIZE_256K
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//! - \b MPU_RGN_SIZE_512K
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//! - \b MPU_RGN_SIZE_1M
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//! - \b MPU_RGN_SIZE_2M
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//! - \b MPU_RGN_SIZE_4M
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//! - \b MPU_RGN_SIZE_8M
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//! - \b MPU_RGN_SIZE_16M
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//! - \b MPU_RGN_SIZE_32M
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//! - \b MPU_RGN_SIZE_64M
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//! - \b MPU_RGN_SIZE_128M
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//! - \b MPU_RGN_SIZE_256M
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//! - \b MPU_RGN_SIZE_512M
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//! - \b MPU_RGN_SIZE_1G
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//! - \b MPU_RGN_SIZE_2G
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//! - \b MPU_RGN_SIZE_4G
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//!
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//! The execute permission flag must be one of the following:
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//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code
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//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code
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//!
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//! The read/write access permissions are applied separately for the
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//! privileged and user modes. The read/write access flags must be one
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//! of the following:
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//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode
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//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access
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//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only
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//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write
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//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access
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//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only
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//!
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//! The region is automatically divided into 8 equally-sized sub-regions by
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//! the MPU. Sub-regions can only be used in regions of size 256 bytes
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//! or larger. Any of these 8 sub-regions can be disabled, allowing for
|
|
//! creation of ``holes'' in a region which can be left open, or overlaid
|
|
//! by another region with different attributes. Any of the 8 sub-regions
|
|
//! can be disabled with a logical OR of any of the following flags:
|
|
//! - \b MPU_SUB_RGN_DISABLE_0
|
|
//! - \b MPU_SUB_RGN_DISABLE_1
|
|
//! - \b MPU_SUB_RGN_DISABLE_2
|
|
//! - \b MPU_SUB_RGN_DISABLE_3
|
|
//! - \b MPU_SUB_RGN_DISABLE_4
|
|
//! - \b MPU_SUB_RGN_DISABLE_5
|
|
//! - \b MPU_SUB_RGN_DISABLE_6
|
|
//! - \b MPU_SUB_RGN_DISABLE_7
|
|
//!
|
|
//! Finally, the region can be initially enabled or disabled with one of
|
|
//! the following flags:
|
|
//! - \b MPU_RGN_ENABLE
|
|
//! - \b MPU_RGN_DISABLE
|
|
//!
|
|
//! As an example, to set a region with the following attributes: size of
|
|
//! 32 KB, execution enabled, read-only for both privileged and user, one
|
|
//! sub-region disabled, and initially enabled; the \e attrFlags parameter
|
|
//! would have the following value:
|
|
//!
|
|
//! <code>
|
|
//! (MPU_RGN_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO |
|
|
//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE)
|
|
//! </code>
|
|
//!
|
|
//! \note This function writes to multiple registers and is not protected
|
|
//! from interrupts. It is possible that an interrupt which accesses a
|
|
//! region may occur while that region is in the process of being changed.
|
|
//! The safest way to handle this is to disable a region before changing it.
|
|
//! Refer to the discussion of this in the API Detailed Description section.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
MPU_setRegionAttributes(uint32_t regionNum, uint32_t baseAddr,
|
|
uint32_t attrFlags)
|
|
{
|
|
uint32_t temp;
|
|
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(regionNum < 8U);
|
|
|
|
//
|
|
// Checking whether the region base address is aligned according to the
|
|
// desired region size.
|
|
//
|
|
ASSERT(baseAddr == (baseAddr & (~(uint32_t)0U <<
|
|
(((attrFlags & NVIC_MPU_RASR_SIZE_M) >>
|
|
NVIC_MPU_RASR_SIZE_S) + 1U))));
|
|
|
|
//
|
|
// Select region to be configured.
|
|
//
|
|
HWREG(NVIC_BASE + NVIC_O_MPU_RNR) = (regionNum & NVIC_MPU_RNR_REGION_M) >>
|
|
NVIC_MPU_RNR_REGION_S;
|
|
|
|
//
|
|
// Program the region attributes.
|
|
//
|
|
temp = MPU_RGN_CONFIG_M;
|
|
HWREG(NVIC_BASE + NVIC_O_MPU_RASR) = (HWREG(NVIC_BASE + NVIC_O_MPU_RASR) &
|
|
~(temp)) | attrFlags;
|
|
|
|
//
|
|
// Program the base address of the region.
|
|
//
|
|
HWREG(NVIC_BASE + NVIC_O_MPU_RBAR) = baseAddr;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Gets the current settings for a specific region.
|
|
//!
|
|
//! \param regionNum is the region number to get.
|
|
//! \param baseAddr points to storage for the base address of the region.
|
|
//! \param attrFlags points to the attribute flags for the region.
|
|
//!
|
|
//! This function retrieves the configuration of a specific region. The
|
|
//! meanings and format of the parameters is the same as that of the
|
|
//! MPU_setRegionAttributes() function.
|
|
//!
|
|
//! This function can be used to save the configuration of a region for later
|
|
//! use with the MPU_setRegionAttributes() function. The region's enable state
|
|
//! is preserved in the attributes that are saved.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
MPU_getRegionAttributes(uint32_t regionNum, uint32_t *baseAddr,
|
|
uint32_t *attrFlags)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(regionNum < 8U);
|
|
ASSERT(baseAddr != 0U);
|
|
ASSERT(attrFlags != 0U);
|
|
|
|
//
|
|
// Select the region to get.
|
|
//
|
|
HWREG(NVIC_BASE + NVIC_O_MPU_RNR) = regionNum;
|
|
|
|
//
|
|
// Read and store the base address for the region.
|
|
//
|
|
*baseAddr = HWREG(NVIC_BASE + NVIC_O_MPU_RBAR) & NVIC_MPU_RBAR_ADDR_M;
|
|
|
|
//
|
|
// Read and store the region attributes.
|
|
//
|
|
*attrFlags = HWREG(NVIC_BASE + NVIC_O_MPU_RASR);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Registers an interrupt handler for the memory management fault.
|
|
//!
|
|
//! \param intNum is the interrupt number to be registered.
|
|
//! \param fnHandler is a pointer to the function to be called when the
|
|
//! memory management fault occurs.
|
|
//!
|
|
//! This function sets and enables the handler to be called when the MPU
|
|
//! generates a memory management fault due to a protection region access
|
|
//! violation. The param intNum can take value FAULT_MPU.
|
|
//!
|
|
//! \sa Interrupt_registerHandler() for important information about registering
|
|
//! interrupt handlers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
MPU_registerHandler(uint32_t intNum, void (*fnHandler)(void))
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT(fnHandler);
|
|
|
|
//
|
|
// Register the interrupt handler.
|
|
//
|
|
Interrupt_registerHandler(intNum, fnHandler);
|
|
|
|
//
|
|
// Enable the memory management fault.
|
|
//
|
|
Interrupt_enable(intNum);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! Unregisters an interrupt handler for the memory management fault.
|
|
//!
|
|
//! \param intNum is the interrupt number to be unregistered.
|
|
//!
|
|
//! This function disables and clears the handler to be called when a
|
|
//! memory management fault occurs. The param intNum can take value FAULT_MPU.
|
|
//!
|
|
//! \sa Interrupt_registerHandler() for important information about registering
|
|
//! interrupt handlers.
|
|
//!
|
|
//! \return None.
|
|
//
|
|
//*****************************************************************************
|
|
static inline void
|
|
MPU_unregisterHandler(uint32_t intNum)
|
|
{
|
|
//
|
|
// Disable the interrupt.
|
|
//
|
|
Interrupt_disable(intNum);
|
|
|
|
//
|
|
// Unregister the interrupt handler.
|
|
//
|
|
Interrupt_unregisterHandler(intNum);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Close the Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// Mark the end of the C bindings section for C++ compilers.
|
|
//
|
|
//*****************************************************************************
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif // MPU_H
|