121 lines
5.5 KiB
C
121 lines
5.5 KiB
C
//###########################################################################
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//
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// FILE: hw_wwd.h
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//
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// TITLE: Definitions for the WWD registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_WWD_H
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#define HW_WWD_H
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//*************************************************************************************************
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//
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// The following are defines for the WWD register offsets
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//
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//*************************************************************************************************
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#define WWD_O_SCSR 0x0U // System Control & Status Register
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#define WWD_O_WDCNTR 0x4U // Watchdog Counter Register
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#define WWD_O_WDKEY 0x8U // Watchdog Reset Key Register
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#define WWD_O_WDCR 0xCU // Watchdog Control Register
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#define WWD_O_WDWCR 0x10U // Watchdog Windowed Control Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SCSR register
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//
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//*************************************************************************************************
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#define WWD_SCSR_WDOVERRIDE 0x1U // WD Override for WDDIS bit
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#define WWD_SCSR_WDENINT 0x2U // WD Interrupt Enable
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#define WWD_SCSR_RSVD_S 3U
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#define WWD_SCSR_RSVD_M 0xFFF8U // Reserved
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#define WWD_SCSR_KEY_S 16U
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#define WWD_SCSR_KEY_M 0xFFFF0000U // KEY field
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the WDCNTR register
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//
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//*************************************************************************************************
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#define WWD_WDCNTR_WDCNTR_S 0U
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#define WWD_WDCNTR_WDCNTR_M 0xFFU // WD Counter
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#define WWD_WDCNTR_RSVD_S 8U
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#define WWD_WDCNTR_RSVD_M 0xFFFFFF00U // Reserved
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the WDKEY register
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//
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//*************************************************************************************************
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#define WWD_WDKEY_WDKEY_S 0U
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#define WWD_WDKEY_WDKEY_M 0xFFU // WD KEY
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#define WWD_WDKEY_RSVD_S 8U
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#define WWD_WDKEY_RSVD_M 0xFFFFFF00U // Reserved
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the WDCR register
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//
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//*************************************************************************************************
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#define WWD_WDCR_WDPS_S 0U
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#define WWD_WDCR_WDPS_M 0x7U // WD Clock Prescalar
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#define WWD_WDCR_WDCHK_S 3U
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#define WWD_WDCR_WDCHK_M 0x38U // WD Check Bits
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#define WWD_WDCR_WDDIS 0x40U // WD Disable
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#define WWD_WDCR_WDFLG 0x80U // WD Reset Status Flag
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#define WWD_WDCR_WDPRECLKDIV_S 8U
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#define WWD_WDCR_WDPRECLKDIV_M 0xF00U // WD Pre Clock Divider
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#define WWD_WDCR_RSVD_S 12U
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#define WWD_WDCR_RSVD_M 0xFFFFF000U // Reserved
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the WDWCR register
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//
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//*************************************************************************************************
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#define WWD_WDWCR_MIN_S 0U
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#define WWD_WDWCR_MIN_M 0xFFU // WD Min Threshold setting for Windowed Watchdog
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// functionality
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#define WWD_WDWCR_FIRSTKEY 0x100U // First Key Detect Flag
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#define WWD_WDWCR_RSVD_S 9U
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#define WWD_WDWCR_RSVD_M 0xFE00U // Reserved
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#define WWD_WDWCR_KEY_S 16U
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#define WWD_WDWCR_KEY_M 0xFFFF0000U // KEY field
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#endif
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