306 lines
15 KiB
C
306 lines
15 KiB
C
//###########################################################################
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//
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// FILE: hw_ssi.h
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//
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// TITLE: Definitions for the SSI registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_SSI_H
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#define HW_SSI_H
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//*************************************************************************************************
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//
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// The following are defines for the SSI register offsets
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//
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//*************************************************************************************************
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#define SSI_O_CR0 0x0U // SSI Control 0
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#define SSI_O_CR1 0x4U // SSI Control 1
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#define SSI_O_DR 0x8U // SSI Data
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#define SSI_O_SR 0xCU // SSI Status
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#define SSI_O_CPSR 0x10U // SSI Clock Prescale
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#define SSI_O_IM 0x14U // SSI Interrupt Mask
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#define SSI_O_RIS 0x18U // SSI Raw Interrupt Status
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#define SSI_O_MIS 0x1CU // SSI Masked Interrupt Status
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#define SSI_O_ICR 0x20U // SSI Interrupt Clear
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#define SSI_O_DMACTL 0x24U // SSI DMA Control
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#define SSI_O_PV 0xFB0U // SSI Peripheral Version
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#define SSI_O_PP 0xFC0U // SSI Peripheral Properties
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#define SSI_O_PERIPHID4 0xFD0U // SSI Peripheral Identification 4
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#define SSI_O_PERIPHID5 0xFD4U // SSI Peripheral Identification 5
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#define SSI_O_PERIPHID6 0xFD8U // SSI Peripheral Identification 6
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#define SSI_O_PERIPHID7 0xFDCU // SSI Peripheral Identification 7
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#define SSI_O_PERIPHID0 0xFE0U // SSI Peripheral Identification 0
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#define SSI_O_PERIPHID1 0xFE4U // SSI Peripheral Identification 1
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#define SSI_O_PERIPHID2 0xFE8U // SSI Peripheral Identification 2
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#define SSI_O_PERIPHID3 0xFECU // SSI Peripheral Identification 3
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#define SSI_O_PCELLID0 0xFF0U // SSI PrimeCell Identification 0
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#define SSI_O_PCELLID1 0xFF4U // SSI PrimeCell Identification 1
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#define SSI_O_PCELLID2 0xFF8U // SSI PrimeCell Identification 2
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#define SSI_O_PCELLID3 0xFFCU // SSI PrimeCell Identification 3
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSICR0 register
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//
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//*************************************************************************************************
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#define SSI_CR0_DSS_S 0U
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#define SSI_CR0_DSS_M 0xFU // SSI Data Size Select
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#define SSI_CR0_FRF_S 4U
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#define SSI_CR0_FRF_M 0x30U // SSI FRame Format Select
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#define SSI_CR0_SPO 0x40U // SSI Serial clock POlarity
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#define SSI_CR0_SPH 0x80U // SSI Serial clock PHase
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#define SSI_CR0_SCR_S 8U
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#define SSI_CR0_SCR_M 0xFF00U // SSI Serial Clock Rate
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSICR1 register
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//
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//*************************************************************************************************
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#define SSI_CR1_LBM 0x1U // SSI Loopback Mode
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#define SSI_CR1_SSE 0x2U // SSI Synchronous Serial Port Enable
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#define SSI_CR1_MS 0x4U // SSI Master/Slave Select
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#define SSI_CR1_EOT 0x10U // End of Transmission
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#define SSI_CR1_DIR 0x100U // SSI Direction of Operation
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#define SSI_CR1_HSCLKEN 0x200U // High Speed Clock Enable
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#define SSI_CR1_FSSHLDFRM 0x400U // FSS Hold Frame
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIDR register
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//
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//*************************************************************************************************
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#define SSI_DR_DATA_S 0U
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#define SSI_DR_DATA_M 0xFFFFU // SSI Receive/Transmit Data
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSISR register
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//
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//*************************************************************************************************
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#define SSI_SR_TFE 0x1U // SSI Transmit FIFO Empty
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#define SSI_SR_TNF 0x2U // SSI Transmit FIFO Not Full
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#define SSI_SR_RNE 0x4U // SSI Receive FIFO Not Empty
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#define SSI_SR_RFF 0x8U // SSI Receive FIFO Full
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#define SSI_SR_BSY 0x10U // SSI Busy Bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSICPSR register
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//
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//*************************************************************************************************
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#define SSI_CPSR_CPSDVSR_S 0U
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#define SSI_CPSR_CPSDVSR_M 0xFFU // SSI Clock Prescale Divisor
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIIM register
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//
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//*************************************************************************************************
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#define SSI_IM_RORIM 0x1U // SSI Receive Overrun Interrupt Mask
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#define SSI_IM_RTIM 0x2U // SSI Receive Time-Out Interrupt Mask
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#define SSI_IM_RXIM 0x4U // SSI Receive FIFO Interrupt Mask
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#define SSI_IM_TXIM 0x8U // SSI Transmit FIFO Interrupt Mask
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#define SSI_IM_DMARXIM 0x10U // SSI Receive DMA Interrupt Mask
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#define SSI_IM_DMATXIM 0x20U // SSI Transmit DMA Interrupt Mask
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#define SSI_IM_EOTIM 0x40U // End of Transmit Interrupt Mask
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIRIS register
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//
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//*************************************************************************************************
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#define SSI_RIS_RORRIS 0x1U // SSI Receive Overrun Raw Interrupt Status
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#define SSI_RIS_RTRIS 0x2U // SSI Receive Time-Out Raw Interrupt Status
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#define SSI_RIS_RXRIS 0x4U // SSI Receive FIFO Raw Interrupt Status
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#define SSI_RIS_TXRIS 0x8U // SSI Transmit FIFO Raw Interrupt Status
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#define SSI_RIS_DMARXRIS 0x10U // SSI Receive DMA Raw Interrupt Status
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#define SSI_RIS_DMATXRIS 0x20U // SSI Transmit DMA Raw Interrupt Status
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#define SSI_RIS_EOTRIS 0x40U // End of Transmit Raw Interrupt Status
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIMIS register
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//
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//*************************************************************************************************
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#define SSI_MIS_RORMIS 0x1U // SSI Receive Overrun Masked Interrupt Status
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#define SSI_MIS_RTMIS 0x2U // SSI Receive Time-Out Masked Interrupt Status
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#define SSI_MIS_RXMIS 0x4U // SSI Receive FIFO Masked Interrupt Status
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#define SSI_MIS_TXMIS 0x8U // SSI Transmit FIFO Masked Interrupt Status
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#define SSI_MIS_DMARXMIS 0x10U // SSI Receive DMA Masked Interrupt Status
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#define SSI_MIS_DMATXMIS 0x20U // SSI Transmit DMA Masked Interrupt Status
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#define SSI_MIS_EOTMIS 0x40U // End of Transmit Masked Interrupt Status
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIICR register
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//
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//*************************************************************************************************
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#define SSI_ICR_RORIC 0x1U // SSI Receive Overrun Interrupt Clear
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#define SSI_ICR_RTIC 0x2U // SSI Receive Time-Out Interrupt Clear
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#define SSI_ICR_DMARXIC 0x10U // SSI Receive DMA Interrupt Clear
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#define SSI_ICR_DMATXIC 0x20U // SSI Transmit DMA Interrupt Clear
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#define SSI_ICR_EOTIC 0x40U // End of Transmit Interrupt Clear
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIDMACTL register
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//
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//*************************************************************************************************
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#define SSI_DMACTL_RXDMAE 0x1U // Receive DMA Enable
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#define SSI_DMACTL_TXDMAE 0x2U // Transmit DMA Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIPV register
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//
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//*************************************************************************************************
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#define SSI_PV_MINOR_S 0U
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#define SSI_PV_MINOR_M 0xFFU // Minor Revision
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#define SSI_PV_MAJOR_S 8U
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#define SSI_PV_MAJOR_M 0xFF00U // Major Revision
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIPP register
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//
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//*************************************************************************************************
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#define SSI_PP_HSCLK 0x1U // High Speed Capability
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#define SSI_PP_MODE_S 1U
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#define SSI_PP_MODE_M 0x6U // Mode of Operation
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#define SSI_PP_FSSHLDFRM 0x8U // SSInFss Hold Frame Capability
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIPeriphID4 register
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//
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//*************************************************************************************************
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#define SSI_PERIPHID4_PID4_S 0U
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#define SSI_PERIPHID4_PID4_M 0xFFU // SSI Peripheral ID Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIPeriphID5 register
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//
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//*************************************************************************************************
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#define SSI_PERIPHID5_PID5_S 0U
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#define SSI_PERIPHID5_PID5_M 0xFFU // SSI Peripheral ID Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIPeriphID6 register
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//
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//*************************************************************************************************
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#define SSI_PERIPHID6_PID6_S 0U
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#define SSI_PERIPHID6_PID6_M 0xFFU // SSI Peripheral ID Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIPeriphID7 register
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//
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//*************************************************************************************************
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#define SSI_PERIPHID7_PID7_S 0U
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#define SSI_PERIPHID7_PID7_M 0xFFU // SSI Peripheral ID Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIPeriphID0 register
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//
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//*************************************************************************************************
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#define SSI_PERIPHID0_PID0_S 0U
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#define SSI_PERIPHID0_PID0_M 0xFFU // SSI Peripheral ID Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIPeriphID1 register
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//
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//*************************************************************************************************
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#define SSI_PERIPHID1_PID1_S 0U
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#define SSI_PERIPHID1_PID1_M 0xFFU // SSI Peripheral ID Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIPeriphID2 register
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//
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//*************************************************************************************************
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#define SSI_PERIPHID2_PID2_S 0U
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#define SSI_PERIPHID2_PID2_M 0xFFU // SSI Peripheral ID Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIPeriphID3 register
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//
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//*************************************************************************************************
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#define SSI_PERIPHID3_PID3_S 0U
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#define SSI_PERIPHID3_PID3_M 0xFFU // SSI Peripheral ID Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIPCellID0 register
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//
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//*************************************************************************************************
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#define SSI_PCELLID0_CID0_S 0U
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#define SSI_PCELLID0_CID0_M 0xFFU // SSI PrimeCell ID Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIPCellID1 register
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//
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//*************************************************************************************************
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#define SSI_PCELLID1_CID1_S 0U
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#define SSI_PCELLID1_CID1_M 0xFFU // SSI PrimeCell ID Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIPCellID2 register
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//
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//*************************************************************************************************
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#define SSI_PCELLID2_CID2_S 0U
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#define SSI_PCELLID2_CID2_M 0xFFU // SSI PrimeCell ID Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SSIPCellID3 register
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//
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//*************************************************************************************************
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#define SSI_PCELLID3_CID3_S 0U
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#define SSI_PCELLID3_CID3_M 0xFFU // SSI PrimeCell ID Register
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#endif
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