142 lines
7.2 KiB
C
142 lines
7.2 KiB
C
//###########################################################################
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//
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// FILE: hw_nmi.h
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//
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// TITLE: Definitions for the NMI registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_NMI_H
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#define HW_NMI_H
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//*************************************************************************************************
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//
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// The following are defines for the NMI register offsets
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//
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//*************************************************************************************************
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#define NMI_O_CMNMICFG 0x0U // CM NMI Configuration Register
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#define NMI_O_CMNMIFLG 0x4U // CM NMI Flag Register
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#define NMI_O_CMNMIFLGCLR 0x8U // CMNMI Flag Clear Register
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#define NMI_O_CMNMIFLGFRC 0xCU // CMNMI Flag Force Register
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#define NMI_O_CMNMIWDCNT 0x10U // CMNMI Watchdog Counter Register
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#define NMI_O_CMNMIWDPRD 0x14U // CMNMI Watchdog Period Register
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#define NMI_O_CMNMISHDWFLG 0x18U // CMNMI Shadow Flag Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMNMICFG register
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//
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//*************************************************************************************************
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#define NMI_CMNMICFG_NMIE 0x1U // Global NMI Enable
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#define NMI_CMNMICFG_KEY_S 16U
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#define NMI_CMNMICFG_KEY_M 0xFFFF0000U // Key protection
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMNMIFLG register
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//
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//*************************************************************************************************
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#define NMI_CMNMIFLG_NMIINT 0x1U // NMI Interrupt Flag
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#define NMI_CMNMIFLG_CLOCKFAIL 0x2U // Clock Fail Interrupt Flag
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#define NMI_CMNMIFLG_MEMUNCERR 0x4U // RAM, ROM Uncorrectable Error NMI Flag
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#define NMI_CMNMIFLG_FLUNCERR 0x8U // Flash Uncorrectable Error NMI Flag
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#define NMI_CMNMIFLG_MCANUNCERR 0x10U // MCAN Uncorrectable Error NMI Flag
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#define NMI_CMNMIFLG_WWDNMI 0x20U // CM WWD NMI flag
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#define NMI_CMNMIFLG_ECATNMI 0x40U // NMI from EtherCAT reset out
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMNMIFLGCLR register
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//
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//*************************************************************************************************
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#define NMI_CMNMIFLGCLR_NMIINT 0x1U // NMIINT Flag Clear
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#define NMI_CMNMIFLGCLR_CLOCKFAIL 0x2U // CLOCKFAIL Flag Clear
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#define NMI_CMNMIFLGCLR_MEMUNCERR 0x4U // MEMUNCERR Flag Clear
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#define NMI_CMNMIFLGCLR_FLUNCERR 0x8U // FLUNCERR Flag Clear
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#define NMI_CMNMIFLGCLR_MCANUNCERR 0x10U // MCANUNCERR Flag Clear
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#define NMI_CMNMIFLGCLR_WWDNMI 0x20U // WWDNMI Flag Clear
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#define NMI_CMNMIFLGCLR_ECATNMI 0x40U // ECATNMI Flag Clear
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#define NMI_CMNMIFLGCLR_KEY_S 16U
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#define NMI_CMNMIFLGCLR_KEY_M 0xFFFF0000U // Key protection
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMNMIFLGFRC register
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//
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//*************************************************************************************************
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#define NMI_CMNMIFLGFRC_CLOCKFAIL 0x2U // CLOCKFAIL Flag Force
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#define NMI_CMNMIFLGFRC_MEMUNCERR 0x4U // MEMUNCERR Flag Force
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#define NMI_CMNMIFLGFRC_FLUNCERR 0x8U // FLUNCERR Flag Force
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#define NMI_CMNMIFLGFRC_MCANUNCERR 0x10U // MCANUNCERR Flag Force
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#define NMI_CMNMIFLGFRC_WWDNMI 0x20U // WWDNMI Flag Force
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#define NMI_CMNMIFLGFRC_ECATNMI 0x40U // ECATNMI Flag Force
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#define NMI_CMNMIFLGFRC_KEY_S 16U
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#define NMI_CMNMIFLGFRC_KEY_M 0xFFFF0000U // Key protection
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMNMIWDCNT register
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//
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//*************************************************************************************************
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#define NMI_CMNMIWDCNT_NMIWDCNT_S 0U
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#define NMI_CMNMIWDCNT_NMIWDCNT_M 0xFFFFU // NMI Watchdog Counter
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMNMIWDPRD register
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//
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//*************************************************************************************************
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#define NMI_CMNMIWDPRD_NMIWDPRD_S 0U
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#define NMI_CMNMIWDPRD_NMIWDPRD_M 0xFFFFU // NMI Watchdog Period
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#define NMI_CMNMIWDPRD_KEY_S 16U
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#define NMI_CMNMIWDPRD_KEY_M 0xFFFF0000U // Key protection
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMNMISHDWFLG register
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//
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//*************************************************************************************************
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#define NMI_CMNMISHDWFLG_CLOCKFAIL 0x2U // CLOCKFAIL Shadow flag
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#define NMI_CMNMISHDWFLG_MEMUNCERR 0x4U // MEMUNCERR Shadow flag
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#define NMI_CMNMISHDWFLG_FLUNCERR 0x8U // FLUNCERR Shadow flag
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#define NMI_CMNMISHDWFLG_MCANUNCERR 0x10U // MCANUNCERR Shadow flag
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#define NMI_CMNMISHDWFLG_WWDNMI 0x20U // WWDNMI Shadow flag
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#define NMI_CMNMISHDWFLG_ECATNMI 0x40U // ECATNMI Shadow flag
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#endif
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