251 lines
14 KiB
C
251 lines
14 KiB
C
//###########################################################################
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//
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// FILE: hw_sysctl.h
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//
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// TITLE: Definitions for the SYSCTL registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_SYSCTL_H
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#define HW_SYSCTL_H
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//*************************************************************************************************
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//
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// The following are defines for the SYSCTL register offsets
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//
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//*************************************************************************************************
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#define SYSCTL_O_CMPCLKCR0 0x0U // CM Peripheral clock gating register 0.
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#define SYSCTL_O_CMPCLKCR1 0x4U // CM Peripheral clock gating register 1.
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#define SYSCTL_O_CMPCLKCR2 0x8U // CM Peripheral clock gating register 2.
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#define SYSCTL_O_CMSOFTPRESET0 0x20U // CM Software Peripheral Reset register 0
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#define SYSCTL_O_CMSOFTPRESET1 0x24U // CM Software Peripheral Reset register 1
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#define SYSCTL_O_CMSOFTPRESET2 0x28U // CM Software Peripheral Reset register 2
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#define SYSCTL_O_CMCLKSTOPREQ0 0x40U // Peripheral Clock Stop Request Register 0
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#define SYSCTL_O_CMCLKSTOPREQ1 0x44U // Peripheral Clock Stop Request Register 1
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#define SYSCTL_O_CMCLKSTOPREQ2 0x48U // Peripheral Clock Stop Request Register 2
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#define SYSCTL_O_CMCLKSTOPACK1 0x64U // Peripheral Clock Stop Ackonwledge Register 1
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#define SYSCTL_O_MCANWAKESTATUS 0xE0U // MCAN Wake Status Register
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#define SYSCTL_O_MCANWAKESTATUSCLR 0xE4U // MCAN Wake Status Clear Register
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#define SYSCTL_O_PALLOCATESTS 0x1F4U // Status of PALLOCATE register.
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#define SYSCTL_O_CMRESCCLR 0x1F8U // CM Reset Cause Status Clear Register
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#define SYSCTL_O_CMRESC 0x1FCU // CM Reset Cause Status Register
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#define SYSCTL_O_CMSYSCTLLOCK 0x200U // Locks the configuration registers of CM System
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// control
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMPCLKCR0 register
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//
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//*************************************************************************************************
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#define SYSCTL_CMPCLKCR0_UART0 0x1U // UART0 Clock gating Bit
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#define SYSCTL_CMPCLKCR0_SSI0 0x10U // SSI0 Clock gating Bit
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#define SYSCTL_CMPCLKCR0_I2C0 0x100U // I2C0 Clock gating Bit
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#define SYSCTL_CMPCLKCR0_USB 0x1000U // USB Clock gating Bit
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#define SYSCTL_CMPCLKCR0_KEY_S 16U
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#define SYSCTL_CMPCLKCR0_KEY_M 0xFFFF0000U // Key field
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMPCLKCR1 register
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//
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//*************************************************************************************************
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#define SYSCTL_CMPCLKCR1_ETHERNET 0x1U // ETHERNET Clock gating Bit
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#define SYSCTL_CMPCLKCR1_ETHERCAT 0x4U // ETHERCAT Clock gating Bit
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#define SYSCTL_CMPCLKCR1_CAN_A 0x10U // CAN_A Clock gating Bit
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#define SYSCTL_CMPCLKCR1_CAN_B 0x20U // CAN_B Clock gating Bit
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#define SYSCTL_CMPCLKCR1_MCAN_A 0x100U // MCAN_A Clock gating Bit
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#define SYSCTL_CMPCLKCR1_KEY_S 16U
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#define SYSCTL_CMPCLKCR1_KEY_M 0xFFFF0000U // Key field
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMPCLKCR2 register
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//
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//*************************************************************************************************
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#define SYSCTL_CMPCLKCR2_CPUTIMER0 0x1U // CPUTIMER0 Clock gating Bit
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#define SYSCTL_CMPCLKCR2_CPUTIMER1 0x2U // CPUTIMER1 Clock gating Bit
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#define SYSCTL_CMPCLKCR2_CPUTIMER2 0x4U // CPUTIMER2 Clock gating Bit
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#define SYSCTL_CMPCLKCR2_UDMA 0x10U // UDMA Clock gating Bit
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#define SYSCTL_CMPCLKCR2_AESIP 0x40U // AESIP Clock gating Bit
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#define SYSCTL_CMPCLKCR2_GCRC 0x100U // GCRC Clock gating Bit
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#define SYSCTL_CMPCLKCR2_KEY_S 16U
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#define SYSCTL_CMPCLKCR2_KEY_M 0xFFFF0000U // Key field
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMSOFTPRESET0 register
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//
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//*************************************************************************************************
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#define SYSCTL_CMSOFTPRESET0_UART0 0x1U // UART0 Soft reset bit
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#define SYSCTL_CMSOFTPRESET0_SSI0 0x10U // SSI0 Soft reset bit
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#define SYSCTL_CMSOFTPRESET0_I2C0 0x100U // I2C0 Soft reset bit
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#define SYSCTL_CMSOFTPRESET0_USB 0x1000U // USB Soft reset bit
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#define SYSCTL_CMSOFTPRESET0_KEY_S 16U
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#define SYSCTL_CMSOFTPRESET0_KEY_M 0xFFFF0000U // Key field
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMSOFTPRESET1 register
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//
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//*************************************************************************************************
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#define SYSCTL_CMSOFTPRESET1_ETHERNET 0x1U // ETHERNET Soft reset bit
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#define SYSCTL_CMSOFTPRESET1_ETHERCAT 0x4U // ETHERCAT Soft reset bit
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#define SYSCTL_CMSOFTPRESET1_CAN_A 0x10U // CAN_A Soft reset bit
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#define SYSCTL_CMSOFTPRESET1_CAN_B 0x20U // CAN_B Soft reset bit
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#define SYSCTL_CMSOFTPRESET1_MCAN_A 0x100U // MCAN_A Soft reset bit
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#define SYSCTL_CMSOFTPRESET1_KEY_S 16U
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#define SYSCTL_CMSOFTPRESET1_KEY_M 0xFFFF0000U // Key field
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMSOFTPRESET2 register
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//
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//*************************************************************************************************
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#define SYSCTL_CMSOFTPRESET2_AESIP 0x40U // AESIP Soft reset bit
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#define SYSCTL_CMSOFTPRESET2_GCRC 0x100U // GCRC Soft reset bit
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#define SYSCTL_CMSOFTPRESET2_KEY_S 16U
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#define SYSCTL_CMSOFTPRESET2_KEY_M 0xFFFF0000U // Key field
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMCLKSTOPREQ0 register
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//
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//*************************************************************************************************
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#define SYSCTL_CMCLKSTOPREQ0_KEY_S 16U
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#define SYSCTL_CMCLKSTOPREQ0_KEY_M 0xFFFF0000U // Key field
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMCLKSTOPREQ1 register
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//
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//*************************************************************************************************
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#define SYSCTL_CMCLKSTOPREQ1_MCAN_A 0x100U // MCAN_A Clock Stop Request Bit
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#define SYSCTL_CMCLKSTOPREQ1_KEY_S 16U
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#define SYSCTL_CMCLKSTOPREQ1_KEY_M 0xFFFF0000U // Key field
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMCLKSTOPREQ2 register
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//
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//*************************************************************************************************
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#define SYSCTL_CMCLKSTOPREQ2_KEY_S 16U
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#define SYSCTL_CMCLKSTOPREQ2_KEY_M 0xFFFF0000U // Key field
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMCLKSTOPACK1 register
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//
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//*************************************************************************************************
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#define SYSCTL_CMCLKSTOPACK1_MCAN_A 0x100U // MCAN_A Clock Stop Ack Bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MCANWAKESTATUS register
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//
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//*************************************************************************************************
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#define SYSCTL_MCANWAKESTATUS_WAKE 0x1U // MCAN Wake Status
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MCANWAKESTATUSCLR register
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//
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//*************************************************************************************************
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#define SYSCTL_MCANWAKESTATUSCLR_WAKE 0x1U // Cear bit for MCANWAKESTATUS.WAKE bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the PALLOCATESTS register
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//
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//*************************************************************************************************
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#define SYSCTL_PALLOCATESTS_USB 0x1U // Status of PALLOCATE.USB bit
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#define SYSCTL_PALLOCATESTS_ETHERCAT 0x2U // Status of PALLOCATE.ETHERCAT bit
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#define SYSCTL_PALLOCATESTS_CAN_A 0x4U // Status of PALLOCATE.CAN_A bit
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#define SYSCTL_PALLOCATESTS_CAN_B 0x8U // Status of PALLOCATE.CAN_B bit
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#define SYSCTL_PALLOCATESTS_MCAN_A 0x10U // Status of PALLOCATE.MCAN_A bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMRESCCLR register
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//
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//*************************************************************************************************
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#define SYSCTL_CMRESCCLR_PORESETN 0x1U // PORESETn status flag clear
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#define SYSCTL_CMRESCCLR_XRSN 0x2U // XRSn status flag clear
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#define SYSCTL_CMRESCCLR_CPU1WDRSN 0x4U // CPU1WDRSn status flag clear
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#define SYSCTL_CMRESCCLR_CPU1NMIWDRSN 0x8U // CPU1NMIWDRSn status flag clear
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#define SYSCTL_CMRESCCLR_CPU1SYSRSN 0x10U // CPU1SYSRSN status flag clear
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#define SYSCTL_CMRESCCLR_CPU1SCCRESETN 0x20U // CPU1SCCRESETn status flag clear
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#define SYSCTL_CMRESCCLR_ECAT_RESET_OUT 0x40U // ECAT_RESET_OUT status flag clear
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#define SYSCTL_CMRESCCLR_CPU1SIMRESET_CPURSN 0x80U // CPU1SIMRESET_CPURSn status flag clear
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#define SYSCTL_CMRESCCLR_CMRSTCTLRESETREQ 0x100U // CMRSTCTLRESETREQ status flag clear
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#define SYSCTL_CMRESCCLR_CPU1_SIMRESET_XRSN 0x200U // CPU1_SIMRESET_XRSn status flag clear
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#define SYSCTL_CMRESCCLR_CMVECTRESETN 0x10000U // CMVECTRESETn status flag clear
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#define SYSCTL_CMRESCCLR_CMSYSRESETREQ 0x20000U // CMSYSRESETREQ status flag clear
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#define SYSCTL_CMRESCCLR_CMNMIWDRSTN 0x40000U // CMNMIWDRSTn status flag clear
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#define SYSCTL_CMRESCCLR_CMEOLRESETN 0x80000U // CMEOLRESETn status flag clear
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMRESC register
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//
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//*************************************************************************************************
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#define SYSCTL_CMRESC_PORESETN 0x1U // PORESETn caused the reset of CM
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#define SYSCTL_CMRESC_XRSN 0x2U // XRSn caused the reset of CM
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#define SYSCTL_CMRESC_CPU1_WDRSN 0x4U // CPU1_WDRSn caused the reset of CM
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#define SYSCTL_CMRESC_CPU1_NMIWDRSN 0x8U // CPU1_NMIWDRSn caused the reset of CM
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#define SYSCTL_CMRESC_CPU1_SYSRSN 0x10U // CPU1_SYSRSN caused the reset of CM
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#define SYSCTL_CMRESC_CPU1_SCCRESETN 0x20U // CPU1_SCCRESETn caused the reset of CM
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#define SYSCTL_CMRESC_ECAT_RESET_OUT 0x40U // ECAT_RESET_OUT caused the reset of CM
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#define SYSCTL_CMRESC_CPU1_SIMRESET_CPURSN 0x80U // CPU1_SIMRESET_CPURSn caused the reset of
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// CM
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#define SYSCTL_CMRESC_CMRSTCTL_RESETREQ 0x100U // CMRSTCTL_RESETREQ caused the reset of CM
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#define SYSCTL_CMRESC_CPU1_SIMRESET_XRSN 0x200U // CPU1_SIMRESET_XRSn caused the reset of
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// CM
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#define SYSCTL_CMRESC_CMVECTRESETN 0x10000U // CMVECTRESETn caused the reset of CM
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#define SYSCTL_CMRESC_CMSYSRESETREQ 0x20000U // CMSYSRESETREQ caused the reset of CM
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#define SYSCTL_CMRESC_CMNMIWDRSTN 0x40000U // CMNMIWDRSTn caused the reset of CM
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#define SYSCTL_CMRESC_CMEOLRESETN 0x80000U // CMEOLRESETn caused the reset of CM
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMSYSCTLLOCK register
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//
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//*************************************************************************************************
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#define SYSCTL_CMSYSCTLLOCK_LOCK 0x1U // Locks the configuration registers of CM System Control
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#endif
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