448 lines
27 KiB
C
448 lines
27 KiB
C
//###########################################################################
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//
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// FILE: hw_memcfg.h
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//
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// TITLE: Definitions for the MEMCFG registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_MEMCFG_H
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#define HW_MEMCFG_H
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//*************************************************************************************************
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//
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// The following are defines for the MEMCFG register offsets
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//
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//*************************************************************************************************
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#define MEMCFG_O_CXLOCK 0x0U // C RAM Config Lock Register
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#define MEMCFG_O_CXTEST 0x4U // C RAM TEST Register
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#define MEMCFG_O_CXINIT 0x8U // C RAM Init Register
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#define MEMCFG_O_CXINITDONE 0xCU // C RAM Initialization Status Register
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#define MEMCFG_O_CMMSGXLOCK 0x20U // CM Messae RAM Config Lock Register
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#define MEMCFG_O_CMMSGXTEST 0x24U // CM Messae RAM TEST Register
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#define MEMCFG_O_CMMSGXINIT 0x28U // CM Messae RAM Init Register
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#define MEMCFG_O_CMMSGXINITDONE 0x2CU // CM Messae RAM Initialization Status Register
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#define MEMCFG_O_SXGROUP1_LOCK 0x40U // Group1 S and E RAM Config Lock Register
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#define MEMCFG_O_SXGROUP1_TEST 0x44U // Group1 S and E RAM TEST Register
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#define MEMCFG_O_SXGROUP1_INIT 0x48U // Group1 S and E RAM Init Register
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#define MEMCFG_O_SXGROUP1_INITDONE 0x4CU // Group1 S and E RAM Initialization Status
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// Register
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#define MEMCFG_O_ROM_LOCK 0x80U // ROM Config Lock Register
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#define MEMCFG_O_ROM_TEST 0x84U // ROM TEST Register
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#define MEMCFG_O_ROM_FORCE_ERROR 0x88U // ROM Force Error register
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#define MEMCFG_O_PERI_MEM_TEST_LOCK 0xA0U // Peripheral Memory Test Lock Register
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#define MEMCFG_O_PERI_MEM_TEST_CONTROL 0xA4U // Peripheral Memory Test control Register
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#define MEMCFG_O_UCERRFLG 0x0U // Uncorrectable Error Flag Register
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#define MEMCFG_O_UCERRSET 0x4U // Uncorrectable Error Flag Set Register
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#define MEMCFG_O_UCERRCLR 0x8U // Uncorrectable Error Flag Clear Register
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#define MEMCFG_O_UCM4EADDR 0xCU // Uncorrectable M4 Error Address
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#define MEMCFG_O_UCEMACEADDR 0x10U // Uncorrectable EMAC Error Address
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#define MEMCFG_O_UCUDMAEADDR 0x14U // Uncorrectable uDMA Error Address
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#define MEMCFG_O_UCETHERCATMEMREADDR 0x18U // Uncorrectable EtherCAT IP RAM Read Error Address
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#define MEMCFG_O_UCEMACMEMREADDR 0x1CU // Uncorrectable EMAC IP RAM Read Error Address
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#define MEMCFG_O_BUSFAULTFLG 0x50U // BusFault Flag register
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#define MEMCFG_O_BUSFAULTCLR 0x54U // BusFault Flag clear register
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#define MEMCFG_O_M4BUSFAULTADDR 0x58U // M4 busfault address
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#define MEMCFG_O_UDMABUSFAULTADDR 0x5CU // uDMA busfault address
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#define MEMCFG_O_EMACBUSFAULTADDR 0x60U // EMAC busfault address
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#define MEMCFG_O_CERRFLG 0x80U // Correctable Error Flag Register
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#define MEMCFG_O_CERRSET 0x84U // Correctable Error Flag Set Register
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#define MEMCFG_O_CERRCLR 0x88U // Correctable Error Flag Clear Register
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#define MEMCFG_O_CM4EADDR 0x8CU // Correctable M4 Error Address
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#define MEMCFG_O_CEMACEADDR 0x90U // Correctable EMAC Error Address
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#define MEMCFG_O_CUDMAEADDR 0x94U // Correctable uDMA Error Address
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#define MEMCFG_O_CERRCNT 0xC0U // Correctable Error Count Register
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#define MEMCFG_O_CERRTHRES 0xC4U // Correctable Error Threshold Value Register
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#define MEMCFG_O_CEINTFLG 0xC8U // Correctable Error Interrupt Flag Status Register
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#define MEMCFG_O_CEINTSET 0xCCU // Correctable Error Interrupt Flag Set Register
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#define MEMCFG_O_CEINTCLR 0xD0U // Correctable Error Interrupt Flag Clear Register
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#define MEMCFG_O_CEINTEN 0xD4U // Correctable Error Interrupt Enable Register
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#define MEMCFG_O_DIAGERRFLG 0x0U // Error Flag Register
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#define MEMCFG_O_DIAGERRCLR 0x8U // Error Flag Clear Register
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#define MEMCFG_O_DIAGERRADDR 0xCU // Read Error Address
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CxLOCK register
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//
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//*************************************************************************************************
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#define MEMCFG_CXLOCK_LOCK_C0 0x1U // C0 RAM Lock bits
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#define MEMCFG_CXLOCK_LOCK_C1 0x2U // C1 RAM Lock bits
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CxTEST register
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//
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//*************************************************************************************************
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#define MEMCFG_CXTEST_TEST_C0_S 0U
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#define MEMCFG_CXTEST_TEST_C0_M 0x3U // Selects the different modes for C0 RAM
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#define MEMCFG_CXTEST_TEST_C1_S 2U
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#define MEMCFG_CXTEST_TEST_C1_M 0xCU // Selects the different modes for C1 RAM
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CxINIT register
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//
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//*************************************************************************************************
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#define MEMCFG_CXINIT_INIT_C0 0x1U // RAM Initialization control for C0 RAM.
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#define MEMCFG_CXINIT_INIT_C1 0x2U // RAM Initialization control for C1 RAM.
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CxINITDONE register
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//
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//*************************************************************************************************
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#define MEMCFG_CXINITDONE_INITDONE_C0 0x1U // RAM Initialization status for C0 RAM.
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#define MEMCFG_CXINITDONE_INITDONE_C1 0x2U // RAM Initialization status for C1 RAM.
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMMSGxLOCK register
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//
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//*************************************************************************************************
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#define MEMCFG_CMMSGXLOCK_LOCK_CMTOCPU1MSGRAM0 0x1U // Message RAM CMTOCPU1MSGRAM0 Lock bits
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#define MEMCFG_CMMSGXLOCK_LOCK_CMTOCPU1MSGRAM1 0x2U // Message RAM CMTOCPU1MSGRAM1 Lock bits
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#define MEMCFG_CMMSGXLOCK_LOCK_CMTOCPU2MSGRAM0 0x4U // Message RAM CMTOCPU2MSGRAM0 Lock bits
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#define MEMCFG_CMMSGXLOCK_LOCK_CMTOCPU2MSGRAM1 0x8U // Message RAM CMTOCPU2MSGRAM1 Lock bits
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMMSGxTEST register
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//
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//*************************************************************************************************
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#define MEMCFG_CMMSGXTEST_TEST_CMTOCPU1MSGRAM0_S 0U
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#define MEMCFG_CMMSGXTEST_TEST_CMTOCPU1MSGRAM0_M 0x3U // Selects the different modes for
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// Message RAM CMTOCPU1MSGRAM0
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#define MEMCFG_CMMSGXTEST_TEST_CMTOCPU1MSGRAM1_S 2U
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#define MEMCFG_CMMSGXTEST_TEST_CMTOCPU1MSGRAM1_M 0xCU // Selects the different modes for
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// Message RAM CMTOCPU1MSGRAM1
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#define MEMCFG_CMMSGXTEST_TEST_CMTOCPU2MSGRAM0_S 4U
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#define MEMCFG_CMMSGXTEST_TEST_CMTOCPU2MSGRAM0_M 0x30U // Selects the different modes for
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// Message RAM CMTOCPU2MSGRAM0
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#define MEMCFG_CMMSGXTEST_TEST_CMTOCPU2MSGRAM1_S 6U
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#define MEMCFG_CMMSGXTEST_TEST_CMTOCPU2MSGRAM1_M 0xC0U // Selects the different modes for
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// Message RAM CMTOCPU2MSGRAM1
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMMSGxINIT register
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//
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//*************************************************************************************************
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#define MEMCFG_CMMSGXINIT_INIT_CMTOCPU1MSGRAM0 0x1U // RAM Initialization control for Message
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// RAM CMTOCPU1MSGRAM0
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#define MEMCFG_CMMSGXINIT_INIT_CMTOCPU1MSGRAM1 0x2U // RAM Initialization control for Message
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// RAM CMTOCPU1MSGRAM1
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#define MEMCFG_CMMSGXINIT_INIT_CMTOCPU2MSGRAM0 0x4U // RAM Initialization control for Message
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// RAM CMTOCPU2MSGRAM0
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#define MEMCFG_CMMSGXINIT_INIT_CMTOCPU2MSGRAM1 0x8U // RAM Initialization control for Message
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// RAM CMTOCPU2MSGRAM1
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CMMSGxINITDONE register
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//
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//*************************************************************************************************
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#define MEMCFG_CMMSGXINITDONE_INITDONE_CMTOCPU1MSGRAM0 0x1U // RAM Initialization status for
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// Message RAM CMTOCPU1MSGRAM0
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#define MEMCFG_CMMSGXINITDONE_INITDONE_CMTOCPU1MSGRAM1 0x2U // RAM Initialization status for
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// Message RAM CMTOCPU1MSGRAM1
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#define MEMCFG_CMMSGXINITDONE_INITDONE_CMTOCPU2MSGRAM0 0x4U // RAM Initialization status for
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// Message RAM CMTOCPU2MSGRAM0
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#define MEMCFG_CMMSGXINITDONE_INITDONE_CMTOCPU2MSGRAM1 0x8U // RAM Initialization status for
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// Message RAM CMTOCPU2MSGRAM1
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SxGROUP1_LOCK register
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//
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//*************************************************************************************************
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#define MEMCFG_SXGROUP1_LOCK_LOCK_S0 0x1U // S0 RAM Lock bits
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#define MEMCFG_SXGROUP1_LOCK_LOCK_S1 0x2U // S1 RAM Lock bits
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#define MEMCFG_SXGROUP1_LOCK_LOCK_S2 0x4U // S2 RAM Lock bits
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#define MEMCFG_SXGROUP1_LOCK_LOCK_S3 0x8U // S3 RAM Lock bits
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#define MEMCFG_SXGROUP1_LOCK_LOCK_E0 0x10U // E0 RAM Lock bits
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SxGROUP1_TEST register
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//
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//*************************************************************************************************
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#define MEMCFG_SXGROUP1_TEST_TEST_S0_S 0U
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#define MEMCFG_SXGROUP1_TEST_TEST_S0_M 0x3U // Selects the different modes for S0 RAM
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#define MEMCFG_SXGROUP1_TEST_TEST_S1_S 2U
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#define MEMCFG_SXGROUP1_TEST_TEST_S1_M 0xCU // Selects the different modes for S1 RAM
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#define MEMCFG_SXGROUP1_TEST_TEST_S2_S 4U
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#define MEMCFG_SXGROUP1_TEST_TEST_S2_M 0x30U // Selects the different modes for S2 RAM
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#define MEMCFG_SXGROUP1_TEST_TEST_S3_S 6U
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#define MEMCFG_SXGROUP1_TEST_TEST_S3_M 0xC0U // Selects the different modes for S3 RAM
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#define MEMCFG_SXGROUP1_TEST_TEST_E0_S 8U
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#define MEMCFG_SXGROUP1_TEST_TEST_E0_M 0x300U // Selects the different modes for E0 RAM
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SxGROUP1_INIT register
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//
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//*************************************************************************************************
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#define MEMCFG_SXGROUP1_INIT_INIT_S0 0x1U // RAM Initialization control for S0 RAM.
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#define MEMCFG_SXGROUP1_INIT_INIT_S1 0x2U // RAM Initialization control for S1 RAM.
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#define MEMCFG_SXGROUP1_INIT_INIT_S2 0x4U // RAM Initialization control for S2 RAM.
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#define MEMCFG_SXGROUP1_INIT_INIT_S3 0x8U // RAM Initialization control for S3 RAM.
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#define MEMCFG_SXGROUP1_INIT_INIT_E0 0x10U // RAM Initialization control for E0 RAM.
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the SxGROUP1_INITDONE register
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//
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//*************************************************************************************************
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#define MEMCFG_SXGROUP1_INITDONE_INITDONE_S0 0x1U // RAM Initialization status for S0 RAM.
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#define MEMCFG_SXGROUP1_INITDONE_INITDONE_S1 0x2U // RAM Initialization status for S1 RAM.
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#define MEMCFG_SXGROUP1_INITDONE_INITDONE_S2 0x4U // RAM Initialization status for S2 RAM.
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#define MEMCFG_SXGROUP1_INITDONE_INITDONE_S3 0x8U // RAM Initialization status for S3 RAM.
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#define MEMCFG_SXGROUP1_INITDONE_INITDONE_E0 0x10U // RAM Initialization status for E0 RAM.
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ROM_LOCK register
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//
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//*************************************************************************************************
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#define MEMCFG_ROM_LOCK_LOCK_BOOTROM 0x1U // BOOTROM Lock bits
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ROM_TEST register
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//
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//*************************************************************************************************
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#define MEMCFG_ROM_TEST_TEST_BOOTROM_S 0U
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#define MEMCFG_ROM_TEST_TEST_BOOTROM_M 0x3U // Selects the different modes for BOOTROM
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ROM_FORCE_ERROR register
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//
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//*************************************************************************************************
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#define MEMCFG_ROM_FORCE_ERROR_FORCE_BOOTROM_ERROR 0x1U // Force Bootrom Parity Error
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the PERI_MEM_TEST_LOCK register
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//
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//*************************************************************************************************
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#define MEMCFG_PERI_MEM_TEST_LOCK_LOCK_PERI_MEM_TEST_CONTROL 0x1U // PERI_MEM_TEST_CONTROL Lock
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// bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the PERI_MEM_TEST_CONTROL register
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//
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//*************************************************************************************************
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#define MEMCFG_PERI_MEM_TEST_CONTROL_EMAC_TEST_ENABLE 0x1U // EMAC Test mode enable
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#define MEMCFG_PERI_MEM_TEST_CONTROL_EMAC_MEM_FORCE_ERROR 0x2U // Force Parity Error on
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// EMAC RAM
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#define MEMCFG_PERI_MEM_TEST_CONTROL_ETHERCAT_TEST_ENABLE 0x10U // EtherCAT Test mode
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// enable
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#define MEMCFG_PERI_MEM_TEST_CONTROL_ETHERCAT_MEM_FORCE_ERROR 0x20U // Force Parity Error on
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// EtherCAT RAM
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the UCERRFLG register
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//
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//*************************************************************************************************
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#define MEMCFG_UCERRFLG_M4RDERR 0x1U // M4 Uncorrectable Read Error Flag
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#define MEMCFG_UCERRFLG_M4WRERR 0x2U // M4 Uncorrectable Write Error Flag
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#define MEMCFG_UCERRFLG_EMACRDERR 0x4U // EMAC Uncorrectable Read Error Flag
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#define MEMCFG_UCERRFLG_UDMARDERR 0x10U // uDMA Uncorrectable Read Error Flag
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#define MEMCFG_UCERRFLG_UDMAWRERR 0x20U // uDMA Uncorrectable Write Error Flag
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#define MEMCFG_UCERRFLG_ETHERCATMEMRDERR 0x40U // EtherCAT IP RAM Uncorrectable Read Error Flag
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#define MEMCFG_UCERRFLG_EMACMEMRDERR 0x80U // EMAC IP RAM Uncorrectable Read Error Flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the UCERRSET register
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//
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//*************************************************************************************************
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#define MEMCFG_UCERRSET_M4RDERR 0x1U // M4 Uncorrectable Read Error Flag Set
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#define MEMCFG_UCERRSET_M4WRERR 0x2U // M4 Uncorrectable Write Error Flag Set
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#define MEMCFG_UCERRSET_EMACRDERR 0x4U // EMAC Uncorrectable Read Error Flag Set
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#define MEMCFG_UCERRSET_UDMARDERR 0x10U // uDMA Uncorrectable Read Error Flag Set
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#define MEMCFG_UCERRSET_UDMAWRERR 0x20U // uDMA Uncorrectable Write Error Flag Set
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#define MEMCFG_UCERRSET_ETHERCATMEMRDERR 0x40U // EtherCAT IP RAM Uncorrectable Read
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// Error Flag set
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#define MEMCFG_UCERRSET_EMACMEMRDERR 0x80U // EMAC IP RAM Uncorrectable Read Error
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// Flag set
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#define MEMCFG_UCERRSET_KEY_S 16U
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#define MEMCFG_UCERRSET_KEY_M 0xFFFF0000U // KEY to allow write access
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the UCERRCLR register
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//
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//*************************************************************************************************
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#define MEMCFG_UCERRCLR_M4RDERR 0x1U // M4 Uncorrectable Read Error Flag Clear
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#define MEMCFG_UCERRCLR_M4WRERR 0x2U // M4 Uncorrectable Write Error Flag Clear
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#define MEMCFG_UCERRCLR_EMACRDERR 0x4U // EMAC Uncorrectable Read Error Flag
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// Clear
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#define MEMCFG_UCERRCLR_UDMARDERR 0x10U // uDMA Uncorrectable Read Error Flag
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// Clear
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#define MEMCFG_UCERRCLR_UDMAWRERR 0x20U // uDMA Uncorrectable Write Error Flag
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// Clear
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#define MEMCFG_UCERRCLR_ETHERCATMEMRDERR 0x40U // EtherCAT IP RAM Uncorrectable Read
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// Error Flag Clear
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#define MEMCFG_UCERRCLR_EMACMEMRDERR 0x80U // EMAC IP RAM Uncorrectable Read Error
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// Flag Clear
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#define MEMCFG_UCERRCLR_KEY_S 16U
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#define MEMCFG_UCERRCLR_KEY_M 0xFFFF0000U // KEY to allow write access
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the BUSFAULTFLG register
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//
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//*************************************************************************************************
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#define MEMCFG_BUSFAULTFLG_M4BUSFAULT 0x1U // M4 busfault Flag
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#define MEMCFG_BUSFAULTFLG_UDMABUSFAULT 0x2U // UDMA busfault Flag
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#define MEMCFG_BUSFAULTFLG_EMACBUSFAULT 0x4U // EMAC busfault Flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the BUSFAULTCLR register
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//
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//*************************************************************************************************
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#define MEMCFG_BUSFAULTCLR_M4BUSFAULT 0x1U // M4 busfault Flag Clear
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#define MEMCFG_BUSFAULTCLR_UDMABUSFAULT 0x2U // UDMA busfault Flag Clear
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#define MEMCFG_BUSFAULTCLR_EMACBUSFAULT 0x4U // EMAC busfault Flag Clear
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#define MEMCFG_BUSFAULTCLR_KEY_S 16U
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#define MEMCFG_BUSFAULTCLR_KEY_M 0xFFFF0000U // KEY to allow write access
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CERRFLG register
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//
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//*************************************************************************************************
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#define MEMCFG_CERRFLG_M4RDERR 0x1U // M4 Correctable Read Error Flag
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#define MEMCFG_CERRFLG_M4WRERR 0x2U // M4 Correctable Write Error Flag
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#define MEMCFG_CERRFLG_EMACRDERR 0x4U // EMAC Correctable Read Error Flag
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#define MEMCFG_CERRFLG_UDMARDERR 0x10U // uDMA Correctable Read Error Flag
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#define MEMCFG_CERRFLG_UDMAWRERR 0x20U // uDMA Correctable Write Error Flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CERRSET register
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//
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//*************************************************************************************************
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#define MEMCFG_CERRSET_M4RDERR 0x1U // M4 Correctable Read Error Flag Set
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#define MEMCFG_CERRSET_M4WRERR 0x2U // M4 Correctable Write Error Flag Set
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#define MEMCFG_CERRSET_EMACRDERR 0x4U // EMAC Correctable Read Error Flag Set
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#define MEMCFG_CERRSET_UDMARDERR 0x10U // uDMA Correctable Read Error Flag Set
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#define MEMCFG_CERRSET_UDMAWRERR 0x20U // uDMA Correctable Write Error Flag Set
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#define MEMCFG_CERRSET_KEY_S 16U
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#define MEMCFG_CERRSET_KEY_M 0xFFFF0000U // KEY to allow write access
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CERRCLR register
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//
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//*************************************************************************************************
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#define MEMCFG_CERRCLR_M4RDERR 0x1U // M4 Correctable Read Error Flag Clear
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#define MEMCFG_CERRCLR_M4WRERR 0x2U // M4 Correctable Write Error Flag Clear
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#define MEMCFG_CERRCLR_EMACRDERR 0x4U // EMAC Correctable Read Error Flag Clear
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#define MEMCFG_CERRCLR_UDMARDERR 0x10U // uDMA Correctable Read Error Flag Clear
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#define MEMCFG_CERRCLR_UDMAWRERR 0x20U // uDMA Correctable Write Error Flag Clear
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#define MEMCFG_CERRCLR_KEY_S 16U
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#define MEMCFG_CERRCLR_KEY_M 0xFFFF0000U // KEY to allow write access
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CEINTFLG register
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//
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//*************************************************************************************************
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#define MEMCFG_CEINTFLG_CEINTFLAG 0x1U // Total corrected error count exceeded threshold flag.
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CEINTSET register
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//
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//*************************************************************************************************
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#define MEMCFG_CEINTSET_CEINTSET 0x1U // Total corrected error count exceeded flag set.
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#define MEMCFG_CEINTSET_KEY_S 16U
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#define MEMCFG_CEINTSET_KEY_M 0xFFFF0000U // KEY to allow write access
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CEINTCLR register
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//
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//*************************************************************************************************
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#define MEMCFG_CEINTCLR_CEINTCLR 0x1U // M4 Corrected Error Threshold Exceeded Error
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// Clear.
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#define MEMCFG_CEINTCLR_KEY_S 16U
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#define MEMCFG_CEINTCLR_KEY_M 0xFFFF0000U // KEY to allow write access
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the CEINTEN register
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//
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//*************************************************************************************************
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#define MEMCFG_CEINTEN_CEINTEN 0x1U // M4 Correctable Error Interrupt Enable.
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#define MEMCFG_CEINTEN_KEY_S 16U
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#define MEMCFG_CEINTEN_KEY_M 0xFFFF0000U // KEY to allow write access
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DIAGERRFLG register
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//
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//*************************************************************************************************
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#define MEMCFG_DIAGERRFLG_UCRDERROR 0x1U // Diagnostics Uncorrectable Read Error Flag
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#define MEMCFG_DIAGERRFLG_UCWRERROR 0x2U // Diagnostics Uncorrectable Write Error Flag
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#define MEMCFG_DIAGERRFLG_CRDERROR 0x4U // Diagnostics Correctable Read Error Flag
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#define MEMCFG_DIAGERRFLG_CWRERROR 0x8U // Diagnostics Correctable Write Error Flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DIAGERRCLR register
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//
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//*************************************************************************************************
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#define MEMCFG_DIAGERRCLR_UCRDERROR 0x1U // Clear diagnostics uncorrectable Read Error Flag
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#define MEMCFG_DIAGERRCLR_UCWRERROR 0x2U // Clear diagnostics uncorrectable Write Error Flag
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#define MEMCFG_DIAGERRCLR_CRDERROR 0x4U // Clear diagnostics correctable Read Error Flag
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#define MEMCFG_DIAGERRCLR_CWRERROR 0x8U // Clear diagnostics correctable Write Error Flag
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#endif
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