176 lines
9.4 KiB
C
176 lines
9.4 KiB
C
//###########################################################################
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//
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// FILE: hw_aes.h
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//
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// TITLE: Definitions for the AES registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_AES_H
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#define HW_AES_H
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//*************************************************************************************************
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//
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// The following are defines for the AES register offsets
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//
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//*************************************************************************************************
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#define AES_O_KEY2_6 0x0U // XTS Second Key or CBC-MAC Third Key
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#define AES_O_KEY2_7 0x4U // XTS Second Key or CBC-MAC Third Key
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#define AES_O_KEY2_4 0x8U // XTS/CCM Second Key or CBC-MAC Third Key
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#define AES_O_KEY2_5 0xCU // XTS Second Key or CBC-MAC Third Key
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#define AES_O_KEY2_2 0x10U // XTS/CCM/CBC-MAC Second Key or Hash Key Input
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#define AES_O_KEY2_3 0x14U // XTS/CCM/CBC-MAC Second Key or Hash Key Input
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#define AES_O_KEY2_0 0x18U // XTS/CCM/CBC-MAC Second Key or Hash Key Input
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#define AES_O_KEY2_1 0x1CU // XTS/CCM/CBC-MAC Second Key or Hash Key Input
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#define AES_O_KEY1_6 0x20U // Key
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#define AES_O_KEY1_7 0x24U // Key
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#define AES_O_KEY1_4 0x28U // Key
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#define AES_O_KEY1_5 0x2CU // Key
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#define AES_O_KEY1_2 0x30U // Key
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#define AES_O_KEY1_3 0x34U // Key
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#define AES_O_KEY1_0 0x38U // Key
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#define AES_O_KEY1_1 0x3CU // Key
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#define AES_O_IV_IN_OUT_0 0x40U // Initialization Vector 0
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#define AES_O_IV_IN_OUT_1 0x44U // Initialization Vector 1
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#define AES_O_IV_IN_OUT_2 0x48U // Initialization Vector 2
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#define AES_O_IV_IN_OUT_3 0x4CU // Initialization Vector 3
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#define AES_O_CTRL 0x50U // Input/Output Buffer Control and Mode Selection
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#define AES_O_C_LENGTH_0 0x54U // Crypto Data Length 0
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#define AES_O_C_LENGTH_1 0x58U // Crypto Data Length 1
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#define AES_O_AUTH_LENGTH 0x5CU // AAD Data Length
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#define AES_O_DATA_IN_OUT_0 0x60U // Data Word 0
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#define AES_O_DATA_IN_OUT_1 0x64U // Data Word 1
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#define AES_O_DATA_IN_OUT_2 0x68U // Data Word 2
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#define AES_O_DATA_IN_OUT_3 0x6CU // Data Word 3
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#define AES_O_TAG_OUT_0 0x70U // Hash Result 0
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#define AES_O_TAG_OUT_1 0x74U // Hash Result 1
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#define AES_O_TAG_OUT_2 0x78U // Hash Result 2
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#define AES_O_TAG_OUT_3 0x7CU // Hash Result 3
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#define AES_O_REV 0x80U // Module Revision Number
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#define AES_O_SYSCONFIG 0x84U // System Configuration
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#define AES_O_SYSSTATUS 0x88U // Reset Status
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#define AES_O_IRQSTATUS 0x8CU // Interrupt Status
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#define AES_O_IRQENABLE 0x90U // Interrupt Enable
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#define AES_O_DIRTY_BITS 0x94U // Accessed / Dirty Bits
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the AES_CTRL register
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//
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//*************************************************************************************************
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#define AES_CTRL_OUTPUT_READY 0x1U // Output Ready Status
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#define AES_CTRL_INPUT_READY 0x2U // Input Ready Status
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#define AES_CTRL_DIRECTION 0x4U // Encryption/Decryption Selection
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#define AES_CTRL_KEY_SIZE_S 3U
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#define AES_CTRL_KEY_SIZE_M 0x18U // Key Size
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#define AES_CTRL_MODE 0x20U // ECB/CBC Mode
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#define AES_CTRL_CTR 0x40U // Counter Mode
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#define AES_CTRL_CTR_WIDTH_S 7U
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#define AES_CTRL_CTR_WIDTH_M 0x180U // AES-CTR Mode Counter Width
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#define AES_CTRL_ICM 0x200U // AES Integer Counter Mode (ICM) Enable
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#define AES_CTRL_CFB 0x400U // Full block AES cipher feedback mode (CFB128)
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// Enable
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#define AES_CTRL_XTS_S 11U
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#define AES_CTRL_XTS_M 0x1800U // AES-XTS Operation Enable
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#define AES_CTRL_F8 0x2000U // AES f8 Mode Enable
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#define AES_CTRL_F9 0x4000U // AES f9 Mode Enable
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#define AES_CTRL_CBCMAC 0x8000U // AES-CBC MAC Enable
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#define AES_CTRL_GCM_S 16U
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#define AES_CTRL_GCM_M 0x30000U // AES-GCM Mode Enable
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#define AES_CTRL_CCM 0x40000U // AES-CCM Mode Enable
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#define AES_CTRL_CCM_L_S 19U
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#define AES_CTRL_CCM_L_M 0x380000U // Width of the length field for CCM operations
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#define AES_CTRL_CCM_M_S 22U
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#define AES_CTRL_CCM_M_M 0x1C00000U // Length of the authentication field for CCM
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// operations
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#define AES_CTRL_SAVE_CONTEXT 0x20000000U // TAG or Result IV Save
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#define AES_CTRL_SVCTXTRDY 0x40000000U // AES TAG/IV Block(s) Ready
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#define AES_CTRL_CTXTRDY 0x80000000U // Context Data Registers Ready
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the AES_SYSCONFIG register
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//
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//*************************************************************************************************
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#define AES_SYSCONFIG_AUTOIDLE 0x1U // autoidle
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#define AES_SYSCONFIG_SOFTRESET 0x2U // Soft Reset
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#define AES_SYSCONFIG_SIDLE_S 2U
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#define AES_SYSCONFIG_SIDLE_M 0xCU // Slave Idle Mode
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#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN 0x20U // DMA Request Data In Enable
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#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN 0x40U // DMA Request Data Out Enable
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#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN 0x80U // DMA Request Context In Enable
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#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN 0x100U // DMA Request Context Out Enable
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#define AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT 0x200U // Map Context Out on Data Out Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the AES_SYSSTATUS register
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//
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//*************************************************************************************************
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#define AES_SYSSTATUS_RESETDONE 0x1U // Reset Done
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the AES_IRQSTATUS register
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//
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//*************************************************************************************************
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#define AES_IRQSTATUS_CONTEXT_IN 0x1U // Context In Interrupt Status
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#define AES_IRQSTATUS_DATA_IN 0x2U // Data In Interrupt Status
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#define AES_IRQSTATUS_DATA_OUT 0x4U // Data Out Interrupt Status
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#define AES_IRQSTATUS_CONTEXT_OUT 0x8U // Context Output Interrupt Status
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the AES_IRQENABLE register
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//
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//*************************************************************************************************
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#define AES_IRQENABLE_CONTEXT_IN 0x1U // Context In Interrupt Enable
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#define AES_IRQENABLE_DATA_IN 0x2U // Data In Interrupt Enable
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#define AES_IRQENABLE_DATA_OUT 0x4U // Data Out Interrupt Enable
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#define AES_IRQENABLE_CONTEXT_OUT 0x8U // Context Out Interrupt Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the AES_DIRTY_BITS register
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//
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//*************************************************************************************************
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#define AES_DIRTY_BITS_S_ACCESS 0x1U // AES Access Bit
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#define AES_DIRTY_BITS_S_DIRTY 0x2U // AES Dirty Bit
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#endif
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