430 lines
23 KiB
C
430 lines
23 KiB
C
//###########################################################################
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//
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// FILE: hw_i2c.h
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//
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// TITLE: Definitions for the I2C registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_I2C_H
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#define HW_I2C_H
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//*************************************************************************************************
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//
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// The following are defines for the I2C register offsets
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//
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//*************************************************************************************************
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#define I2C_O_MSA 0x0U // I2C Master Slave Address
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#define I2C_O_MCS 0x4U // I2C Master Control/Status
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#define I2C_O_MDR 0x8U // I2C Master Data
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#define I2C_O_MTPR 0xCU // I2C Master Timer Period
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#define I2C_O_MIMR 0x10U // I2C Master Interrupt Mask
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#define I2C_O_MRIS 0x14U // I2C Master Raw Interrupt Status
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#define I2C_O_MMIS 0x18U // I2C Master Masked Interrupt Status
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#define I2C_O_MICR 0x1CU // I2C Master Interrupt Clear
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#define I2C_O_MCR 0x20U // I2C Master Configuration
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#define I2C_O_MCLKOCNT 0x24U // I2C Master Clock Low Timeout Count
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#define I2C_O_MBMON 0x2CU // I2C Master Bus Monitor
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#define I2C_O_MBLEN 0x30U // I2C Master Burst Length
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#define I2C_O_MBCNT 0x34U // I2C Master Burst Count
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#define I2C_O_SOAR 0x800U // I2C Slave Own Address
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#define I2C_O_SCSR 0x804U // I2C Slave Control/Status
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#define I2C_O_SDR 0x808U // I2C Slave Data
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#define I2C_O_SIMR 0x80CU // I2C Slave Interrupt Mask
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#define I2C_O_SRIS 0x810U // I2C Slave Raw Interrupt Status
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#define I2C_O_SMIS 0x814U // I2C Slave Masked Interrupt Status
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#define I2C_O_SICR 0x818U // I2C Slave Interrupt Clear
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#define I2C_O_SOAR2 0x81CU // I2C Slave Own Address 2
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#define I2C_O_SACKCTL 0x820U // I2C Slave ACK Control
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#define I2C_O_FIFODATARX 0xF00U // I2C FIFO Data RX
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#define I2C_O_FIFOCTL 0xF04U // I2C FIFO Control
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#define I2C_O_FIFOSTATUS 0xF08U // I2C FIFO Status
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#define I2C_O_PP 0xFC0U // I2C Peripheral Properties
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#define I2C_O_PC 0xFC4U // I2C Peripheral Configuration
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#define I2C_O_MCS_WRITE 0x4U // I2C Master Control/Status
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#define I2C_O_SCSR_WRITE 0x804U // I2C Slave Control/Status
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#define I2C_O_FIFODATATX 0xF00U // I2C FIFO Data TX
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CMSA register
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//
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//*************************************************************************************************
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#define I2C_MSA_RS 0x1U // Receive/Send
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#define I2C_MSA_SA_S 1U
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#define I2C_MSA_SA_M 0xFEU // I2C Slave Address
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CMCS register
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//
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//*************************************************************************************************
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#define I2C_MCS_BUSY 0x1U // I2C Busy
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#define I2C_MCS_ERROR 0x2U // Error
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#define I2C_MCS_ADRACK 0x4U // Acknowledge Address
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#define I2C_MCS_DATACK 0x8U // Acknowledge Data
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#define I2C_MCS_ARBLST 0x10U // Arbitration Lost
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#define I2C_MCS_IDLE 0x20U // I2C Idle
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#define I2C_MCS_BUSBSY 0x40U // Bus Busy
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#define I2C_MCS_CLKTO 0x80U // Clock Timeout Error
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#define I2C_MCS_ACTDMATX 0x40000000U // DMA TX Active Status
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#define I2C_MCS_ACTDMARX 0x80000000U // DMA RX Active Status
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CMDR register
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//
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//*************************************************************************************************
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#define I2C_MDR_DATA_S 0U
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#define I2C_MDR_DATA_M 0xFFU // Data transmitted/received
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CMTPR register
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//
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//*************************************************************************************************
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#define I2C_MTPR_TPR_S 0U
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#define I2C_MTPR_TPR_M 0x7FU // Timer Period
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#define I2C_MTPR_HS 0x80U // High-Speed Enable
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#define I2C_MTPR_PULSEL_S 16U
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#define I2C_MTPR_PULSEL_M 0x70000U // Glitch Suppression Pulse Width
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CMIMR register
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//
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//*************************************************************************************************
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#define I2C_MIMR_IM 0x1U // Master Interrupt Mask
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#define I2C_MIMR_CLKIM 0x2U // Clock Timeout Interrupt Mask
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#define I2C_MIMR_DMARXIM 0x4U // Receive DMA Interrupt Mask
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#define I2C_MIMR_DMATXIM 0x8U // Transmit DMA Interrupt Mask
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#define I2C_MIMR_NACKIM 0x10U // Address/Data NACK Interrupt Mask
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#define I2C_MIMR_STARTIM 0x20U // START Detection Interrupt Mask
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#define I2C_MIMR_STOPIM 0x40U // STOP Detection Interrupt Mask
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#define I2C_MIMR_ARBLOSTIM 0x80U // Arbitration Lost Interrupt Mask
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#define I2C_MIMR_TXIM 0x100U // Transmit FIFO Request Interrupt Mask
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#define I2C_MIMR_RXIM 0x200U // Receive FIFO Request Interrupt Mask
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#define I2C_MIMR_TXFEIM 0x400U // Transmit FIFO Empty Interrupt Mask
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#define I2C_MIMR_RXFFIM 0x800U // Receive FIFO Full Interrupt Mask
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CMRIS register
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//
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//*************************************************************************************************
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#define I2C_MRIS_RIS 0x1U // Master Raw Interrupt Status
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#define I2C_MRIS_CLKRIS 0x2U // Clock Timeout Raw Interrupt Status
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#define I2C_MRIS_DMARXRIS 0x4U // Receive DMA Raw Interrupt Status
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#define I2C_MRIS_DMATXRIS 0x8U // Transmit DMA Raw Interrupt Status
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#define I2C_MRIS_NACKRIS 0x10U // Address/Data NACK Raw Interrupt Status
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#define I2C_MRIS_STARTRIS 0x20U // START Detection Raw Interrupt Status
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#define I2C_MRIS_STOPRIS 0x40U // STOP Detection Raw Interrupt Status
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#define I2C_MRIS_ARBLOSTRIS 0x80U // Arbitration Lost Raw Interrupt Status
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#define I2C_MRIS_TXRIS 0x100U // Transmit Request Raw Interrupt Status
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#define I2C_MRIS_RXRIS 0x200U // Receive FIFO Request Raw Interrupt Status
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#define I2C_MRIS_TXFERIS 0x400U // Transmit FIFO Empty Raw Interrupt Status
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#define I2C_MRIS_RXFFRIS 0x800U // Receive FIFO Full Raw Interrupt Status
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CMMIS register
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//
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//*************************************************************************************************
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#define I2C_MMIS_MIS 0x1U // Masked Interrupt Status
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#define I2C_MMIS_CLKMIS 0x2U // Clock Timeout Masked Interrupt Status
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#define I2C_MMIS_DMARXMIS 0x4U // Receive DMA Interrupt Status
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#define I2C_MMIS_DMATXMIS 0x8U // Transmit DMA Interrupt Status
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#define I2C_MMIS_NACKMIS 0x10U // Address/Data NACK Interrupt Mask
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#define I2C_MMIS_STARTMIS 0x20U // START Detection Interrupt Mask
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#define I2C_MMIS_STOPMIS 0x40U // STOP Detection Interrupt Mask
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#define I2C_MMIS_ARBLOSTMIS 0x80U // Arbitration Lost Interrupt Mask
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#define I2C_MMIS_TXMIS 0x100U // Transmit Request Interrupt Mask
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#define I2C_MMIS_RXMIS 0x200U // Receive FIFO Request Interrupt Mask
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#define I2C_MMIS_TXFEMIS 0x400U // Transmit FIFO Empty Interrupt Mask
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#define I2C_MMIS_RXFFMIS 0x800U // Receive FIFO Full Interrupt Mask
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CMICR register
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//
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//*************************************************************************************************
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#define I2C_MICR_IC 0x1U // Master Interrupt Clear
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#define I2C_MICR_CLKIC 0x2U // Clock Timeout Interrupt Clear
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#define I2C_MICR_DMARXIC 0x4U // Receive DMA Interrupt Clear
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#define I2C_MICR_DMATXIC 0x8U // Transmit DMA Interrupt Clear
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#define I2C_MICR_NACKIC 0x10U // Address/Data NACK Interrupt Clear
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#define I2C_MICR_STARTIC 0x20U // START Detection Interrupt Clear
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#define I2C_MICR_STOPIC 0x40U // STOP Detection Interrupt Clear
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#define I2C_MICR_ARBLOSTIC 0x80U // Arbitration Lost Interrupt Clear
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#define I2C_MICR_TXIC 0x100U // Transmit FIFO Request Interrupt Clear
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#define I2C_MICR_RXIC 0x200U // Receive FIFO Request Interrupt Clear
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#define I2C_MICR_TXFEIC 0x400U // Transmit FIFO Empty Interrupt Clear
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#define I2C_MICR_RXFFIC 0x800U // Receive FIFO Full Interrupt Clear
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CMCR register
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//
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//*************************************************************************************************
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#define I2C_MCR_LPBK 0x1U // I2C Loopback
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#define I2C_MCR_MFE 0x10U // I2C Master Function Enable
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#define I2C_MCR_SFE 0x20U // I2C Slave Function Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CMCLKOCNT register
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//
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//*************************************************************************************************
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#define I2C_MCLKOCNT_CNTL_S 0U
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#define I2C_MCLKOCNT_CNTL_M 0xFFU // I2C Master Count
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CMBMON register
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//
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//*************************************************************************************************
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#define I2C_MBMON_SCL 0x1U // I2C SCL Status
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#define I2C_MBMON_SDA 0x2U // I2C SDA Status
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CMBLEN register
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//
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//*************************************************************************************************
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#define I2C_MBLEN_CNTL_S 0U
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#define I2C_MBLEN_CNTL_M 0xFFU // I2C Burst Length
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CMBCNT register
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//
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//*************************************************************************************************
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#define I2C_MBCNT_CNTL_S 0U
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#define I2C_MBCNT_CNTL_M 0xFFU // I2C Master Burst Count
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CSOAR register
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//
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//*************************************************************************************************
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#define I2C_SOAR_OAR_S 0U
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#define I2C_SOAR_OAR_M 0x7FU // I2C Slave Own Address
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CSCSR register
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//
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//*************************************************************************************************
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#define I2C_SCSR_RREQ 0x1U // Receive Request
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#define I2C_SCSR_TREQ 0x2U // Transmit Request
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#define I2C_SCSR_FBR 0x4U // First Byte Received
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#define I2C_SCSR_OAR2SEL 0x8U // OAR2 Address Matched
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#define I2C_SCSR_QCMDST 0x10U // Quick Command Status
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#define I2C_SCSR_QCMDRW 0x20U // Quick Command Read / Write
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#define I2C_SCSR_ACTDMATX 0x40000000U // DMA TX Active Status
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#define I2C_SCSR_ACTDMARX 0x80000000U // DMA RX Active Status
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CSDR register
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//
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//*************************************************************************************************
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#define I2C_SDR_DATA_S 0U
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#define I2C_SDR_DATA_M 0xFFU // Data for Transfer
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CSIMR register
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//
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//*************************************************************************************************
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#define I2C_SIMR_DATAIM 0x1U // Data Interrupt Mask
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#define I2C_SIMR_STARTIM 0x2U // Start Condition Interrupt Mask
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#define I2C_SIMR_STOPIM 0x4U // Stop Condition Interrupt Mask
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#define I2C_SIMR_DMARXIM 0x8U // Receive DMA Interrupt Mask
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#define I2C_SIMR_DMATXIM 0x10U // Transmit DMA Interrupt Mask
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#define I2C_SIMR_TXIM 0x20U // Transmit FIFO Request Interrupt Mask
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#define I2C_SIMR_RXIM 0x40U // Receive FIFO Request Interrupt Mask
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#define I2C_SIMR_TXFEIM 0x80U // Transmit FIFO Empty Interrupt Mask
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#define I2C_SIMR_RXFFIM 0x100U // Receive FIFO Full Interrupt Mask
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CSRIS register
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//
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//*************************************************************************************************
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#define I2C_SRIS_DATARIS 0x1U // Data Raw Interrupt Status
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#define I2C_SRIS_STARTRIS 0x2U // Start Condition Raw Interrupt Status
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#define I2C_SRIS_STOPRIS 0x4U // Stop Condition Raw Interrupt Status
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#define I2C_SRIS_DMARXRIS 0x8U // Receive DMA Raw Interrupt Status
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#define I2C_SRIS_DMATXRIS 0x10U // Transmit DMA Raw Interrupt Status
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#define I2C_SRIS_TXRIS 0x20U // Transmit Request Raw Interrupt Status
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#define I2C_SRIS_RXRIS 0x40U // Receive FIFO Request Raw Interrupt Status
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#define I2C_SRIS_TXFERIS 0x80U // Transmit FIFO Empty Raw Interrupt Status
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#define I2C_SRIS_RXFFRIS 0x100U // Receive FIFO Full Raw Interrupt Status
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CSMIS register
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//
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//*************************************************************************************************
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#define I2C_SMIS_DATAMIS 0x1U // Data Masked Interrupt Status
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#define I2C_SMIS_STARTMIS 0x2U // Start Condition Masked Interrupt Status
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#define I2C_SMIS_STOPMIS 0x4U // Stop Condition Masked Interrupt Status
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#define I2C_SMIS_DMARXMIS 0x8U // Receive DMA Masked Interrupt Status
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#define I2C_SMIS_DMATXMIS 0x10U // Transmit DMA Masked Interrupt Status
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#define I2C_SMIS_TXMIS 0x20U // Transmit FIFO Request Interrupt Mask
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#define I2C_SMIS_RXMIS 0x40U // Receive FIFO Request Interrupt Mask
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#define I2C_SMIS_TXFEMIS 0x80U // Transmit FIFO Empty Interrupt Mask
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#define I2C_SMIS_RXFFMIS 0x100U // Receive FIFO Full Interrupt Mask
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CSICR register
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//
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//*************************************************************************************************
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#define I2C_SICR_DATAIC 0x1U // Data Interrupt Clear
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#define I2C_SICR_STARTIC 0x2U // Start Condition Interrupt Clear
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#define I2C_SICR_STOPIC 0x4U // Stop Condition Interrupt Clear
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#define I2C_SICR_DMARXIC 0x8U // Receive DMA Interrupt Clear
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#define I2C_SICR_DMATXIC 0x10U // Transmit DMA Interrupt Clear
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#define I2C_SICR_TXIC 0x20U // Transmit Request Interrupt Mask
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#define I2C_SICR_RXIC 0x40U // Receive Request Interrupt Mask
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#define I2C_SICR_TXFEIC 0x80U // Transmit FIFO Empty Interrupt Mask
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#define I2C_SICR_RXFFIC 0x100U // Receive FIFO Full Interrupt Mask
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CSOAR2 register
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//
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//*************************************************************************************************
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#define I2C_SOAR2_OAR2_S 0U
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#define I2C_SOAR2_OAR2_M 0x7FU // I2C Slave Own Address 2
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#define I2C_SOAR2_OAR2EN 0x80U // I2C Slave Own Address 2 Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CSACKCTL register
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//
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//*************************************************************************************************
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#define I2C_SACKCTL_ACKOEN 0x1U // I2C Slave ACK Override Enable
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#define I2C_SACKCTL_ACKOVAL 0x2U // I2C Slave ACK Override Value
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CFIFODATARX register
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//
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//*************************************************************************************************
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#define I2C_FIFODATARX_DATA_S 0U
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#define I2C_FIFODATARX_DATA_M 0xFFU // I2C RX FIFO Read Data Byte
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CFIFOCTL register
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//
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//*************************************************************************************************
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#define I2C_FIFOCTL_TXTRIG_S 0U
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#define I2C_FIFOCTL_TXTRIG_M 0x7U // TX FIFO Trigger
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#define I2C_FIFOCTL_DMATXENA 0x2000U // DMA TX Channel Enable
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#define I2C_FIFOCTL_TXFLUSH 0x4000U // TX FIFO Flush
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#define I2C_FIFOCTL_TXASGNMT 0x8000U // TX Control Assignment
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#define I2C_FIFOCTL_RXTRIG_S 16U
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#define I2C_FIFOCTL_RXTRIG_M 0x70000U // RX FIFO Trigger
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#define I2C_FIFOCTL_DMARXENA 0x20000000U // DMA RX Channel Enable
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#define I2C_FIFOCTL_RXFLUSH 0x40000000U // RX FIFO Flush
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#define I2C_FIFOCTL_RXASGNMT 0x80000000U // RX Control Assignment
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CFIFOSTATUS register
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//
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//*************************************************************************************************
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#define I2C_FIFOSTATUS_TXFE 0x1U // TX FIFO Empty
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#define I2C_FIFOSTATUS_TXFF 0x2U // TX FIFO Full
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#define I2C_FIFOSTATUS_TXBLWTRIG 0x4U // TX FIFO Below Trigger Level
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#define I2C_FIFOSTATUS_RXFE 0x10000U // RX FIFO Empty
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#define I2C_FIFOSTATUS_RXFF 0x20000U // RX FIFO Full
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#define I2C_FIFOSTATUS_RXABVTRIG 0x40000U // RX FIFO Above Trigger Level
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CPP register
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//
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//*************************************************************************************************
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#define I2C_PP_HS 0x1U // High-Speed Capable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CPC register
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//
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//*************************************************************************************************
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#define I2C_PC_HS 0x1U // High-Speed Capable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CMCS_WRITE register
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//
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//*************************************************************************************************
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#define I2C_MCS_WRITE_RUN 0x1U // I2C Master Enable
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#define I2C_MCS_WRITE_START 0x2U // Generate START
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#define I2C_MCS_WRITE_STOP 0x4U // Generate STOP
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#define I2C_MCS_WRITE_ACK 0x8U // Data Acknowledge Enable
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#define I2C_MCS_WRITE_HS 0x10U // High-Speed Enable
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#define I2C_MCS_WRITE_QCMD 0x20U // Quick Command
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#define I2C_MCS_WRITE_BURST 0x40U // Burst Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CSCSR_WRITE register
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//
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//*************************************************************************************************
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#define I2C_SCSR_WRITE_DA 0x1U // Device Active
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#define I2C_SCSR_WRITE_TXFIFO 0x2U // TX FIFO Enable
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#define I2C_SCSR_WRITE_RXFIFO 0x4U // RX FIFO Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the I2CFIFODATATX register
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//
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//*************************************************************************************************
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#define I2C_FIFODATATX_DATA_S 0U
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#define I2C_FIFODATATX_DATA_M 0xFFU // I2C TX FIFO Write Data Byte
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#endif
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