675 lines
24 KiB
C
675 lines
24 KiB
C
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//###########################################################################
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//
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// FILE: interrupt.h
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//
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// TITLE: Driver for the NVIC Interrupt Controller.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef INTERRUPT_H
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#define INTERRUPT_H
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//*****************************************************************************
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//
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// If building with a C++ compiler, make all of the definitions in this header
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// have a C binding.
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//
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//*****************************************************************************
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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//*****************************************************************************
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//
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//! \addtogroup interrupt_api INTERRUPT
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//! \brief This module configures the NVIC interrupt controller.
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//! @{
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//
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//*****************************************************************************
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#include <stdbool.h>
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#include <stdint.h>
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#include "cpu.h"
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#include "debug.h"
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#include "inc/hw_ints.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_nvic.h"
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#include "inc/hw_types.h"
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#ifndef DOXYGEN_PDF_IGNORE
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//*****************************************************************************
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//
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// Defines for the API.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Defines for specifying NVIC module register offset increment.
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//
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//*****************************************************************************
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#define NVIC_OFFSET_INC 0x4U //!< 8-bit offset increment
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//*****************************************************************************
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//
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// Define for specifying the key for AIRCR register.
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//
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//*****************************************************************************
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#define NVIC_AIRCR_VECTKEY 0x05FA0000U
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//*****************************************************************************
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//
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// Flash Vector Table defined in startup.ccs.
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//
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//*****************************************************************************
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#ifndef USE_RTOS
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extern void (*vectorTableFlash[NUM_INTERRUPTS])(void);
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#endif
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//*****************************************************************************
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//
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// RAM Vector Table to be used as dstVectorTable in
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// Interrupt_initRAMVectorTable(). Set the size of the vector table to the
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// largest number of interrupts of any device.
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//
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//*****************************************************************************
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#ifndef USE_RTOS
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extern void (*vectorTableRAM[NUM_INTERRUPTS])(void);
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#endif
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#endif
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//*****************************************************************************
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//
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//! Values that can be passed to Interrupt_setPriorityGrouping() as priGroup
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//! parameter.
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//
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//*****************************************************************************
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typedef enum
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{
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Interrupt_PriorityGrouping_7_1 = 0x00000000U, //!<Priority group 7.1 split
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Interrupt_PriorityGrouping_6_2 = 0x00000100U, //!<Priority group 6.2 split
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Interrupt_PriorityGrouping_5_3 = 0x00000200U, //!<Priority group 5.3 split
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Interrupt_PriorityGrouping_4_4 = 0x00000300U, //!<Priority group 4.4 split
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Interrupt_PriorityGrouping_3_5 = 0x00000400U, //!<Priority group 3.5 split
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Interrupt_PriorityGrouping_2_6 = 0x00000500U, //!<Priority group 2.6 split
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Interrupt_PriorityGrouping_1_7 = 0x00000600U, //!<Priority group 1.7 split
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Interrupt_PriorityGrouping_0_8 = 0x00000700U //!<Priority group 0.8 split
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} Interrupt_PriorityGrouping;
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//*****************************************************************************
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//
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// Prototypes for the APIs.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \internal
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//! The default interrupt handler.
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//!
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//! This is the default interrupt handler for all interrupts. It simply loops
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//! forever so that the system state is preserved for observation by a
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//! debugger. Since interrupts must be disabled before unregistering the
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//! corresponding handler, this should never be called during normal operation.
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//!
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//! \return None.
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//
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//*****************************************************************************
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#ifndef USE_RTOS
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static inline void
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Interrupt_defaultHandler(void)
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{
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//
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// Go into an infinite loop.
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//
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while((bool)true)
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{
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}
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}
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#endif
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//*****************************************************************************
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//
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//! Enables the processor interrupt.
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//!
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//! This function allows the processor to respond to interrupts. This function
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//! does not affect the set of interrupts enabled in the interrupt controller,
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//! it just gates the single interrupt from the controller to the processor.
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//!
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//! \return Returns \b true if interrupts were disabled when the function was
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//! called or \b false if they were initially enabled.
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//
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//*****************************************************************************
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static inline bool
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Interrupt_enableInProcessor(void)
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{
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//
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// Enable processor interrupts.
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//
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return(CPU_clearPRIMASK() == 0x1UL);
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}
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//*****************************************************************************
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//
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//! Disables the processor interrupt.
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//!
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//! This function prevents the processor from receiving interrupts. This
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//! function does not affect the set of interrupts enabled in the interrupt
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//! controller; it just gates the single interrupt from the controller to the
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//! processor.
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//!
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//! \return Returns \b true if interrupts were already disabled when the
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//! function was called or \b false if they were initially enabled.
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//
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//*****************************************************************************
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static inline bool
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Interrupt_disableInProcessor(void)
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{
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//
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// Disable processor interrupts.
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//
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return(CPU_setPRIMASK() == 0x1UL);
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}
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//*****************************************************************************
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//
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//! Triggers an interrupt.
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//!
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//! \param interruptNum specifies the interrupt to be triggered.
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//!
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//! This function performs a software trigger of an interrupt.The interrupt
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//! controller behaves as if the corresponding interrupt line was asserted,
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//! and the interrupt is handled in the same manner (meaning that it must be
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//! enabled in order to be processed, and the processing is based on its
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//! priority with respect to other unhandled interrupts).
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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Interrupt_setSoftwareTrigger(uint32_t interruptNum)
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{
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//
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// Check the arguments.
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//
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ASSERT((interruptNum >= 16U) && (interruptNum < NUM_INTERRUPTS));
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//
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// Trigger this interrupt.
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//
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HWREG(NVIC_BASE + NVIC_O_STIR) = interruptNum - 16U;
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}
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//*****************************************************************************
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//
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//! Sets the offset address of the vector table.
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//!
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//! \param addr is the new address of the vector table.
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//!
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//! Sets the address of the vector table. This function is for advanced users
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//! who might want to switch between multiple instances of vector tables
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//! (perhaps between flash/ram). The param addr can take following values:
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//! (uint32_t)vectorTableFlash - Offset address for Flash Vector Table
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//! (uint32_t)vectorTableRAM - Offset address for RAM Vector Table
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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Interrupt_setVectorTableOffset(uint32_t addr)
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{
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HWREG(NVIC_BASE + NVIC_O_VTOR) = addr;
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}
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//*****************************************************************************
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//
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//! Returns the offset address of the interrupt vector table.
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//!
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//! This function returns the offset address of the interrupt vector table.
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//!
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//! \return Offset address of the vector table.
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//
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//*****************************************************************************
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static inline uint32_t
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Interrupt_getVectorTableOffset(void)
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{
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return(HWREG(NVIC_BASE + NVIC_O_VTOR));
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}
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//*****************************************************************************
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//
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//! Sets the priority grouping of the interrupt controller.
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//!
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//! \param priGrouping specifies the required priority grouping
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//!
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//! This function specifies the split between preemptable priority levels and
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//! sub-priority levels in the interrupt priority specification. The range of
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//! the grouping values are dependent upon the hardware implementation; on
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//! the MSP432 family, three bits are available for hardware interrupt
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//! prioritization and therefore priority grouping values of three through
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//! seven have the same effect.
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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Interrupt_setPriorityGrouping(Interrupt_PriorityGrouping priGrouping)
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{
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//
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// Check the arguments.
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//
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ASSERT(priGrouping < NUM_PRIORITY);
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//
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// Set the priority grouping.
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//
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HWREG(NVIC_BASE + NVIC_O_AIRCR) = NVIC_AIRCR_VECTKEY |
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(uint32_t)priGrouping;
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}
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//*****************************************************************************
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//
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//! Gets the priority grouping of the interrupt controller.
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//!
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//! This function returns the split between preemptable priority levels and
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//! sub-priority levels in the interrupt priority specification.
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//!
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//! \return The number of bits of preemptable priority.
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//
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//*****************************************************************************
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static inline uint32_t
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Interrupt_getPriorityGrouping(void)
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{
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//
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// Read the priority grouping.
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//
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return(HWREG(NVIC_BASE + NVIC_O_AIRCR) & NVIC_AIRCR_PRIGROUP_M);
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}
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//*****************************************************************************
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//! Resets the core and all on-chip peripherals except Debug interface.
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//!
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//! This function will perform a software reset of the entire device. The
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//! processor and all peripherals will be reset and all device registers will
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//! return to their default values (with the exception of the reset cause
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//! register, which will maintain its current value but have the software reset
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//! bit set as well).
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//!
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//! \return None
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//*****************************************************************************
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static inline void
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Interrupt_requestSystemReset(void)
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{
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//
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// Perform a software reset request. This will cause the device to reset,
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// no further code will be executed.
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//
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HWREG(NVIC_BASE + NVIC_O_AIRCR) = NVIC_AIRCR_VECTKEY |
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NVIC_AIRCR_SYSRESETREQ;
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//
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// The device should have reset, so this should never be reached. Just in
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// case, loop forever.
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//
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while((bool)true)
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{
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}
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}
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//*****************************************************************************
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//
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//! Sets the priority masking level.
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//!
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//! \param priorityMask is the priority level that is masked.
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//!
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//! This function sets the interrupt priority masking level so that all
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//! interrupts at the specified or lesser priority level are masked. Masking
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//! interrupts can be used to globally disable a set of interrupts with
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//! priority below a predetermined threshold. A value of 0 disables priority
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//! masking.
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//!
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//! Smaller numbers correspond to higher interrupt priorities. So for example
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//! a priority level mask of 4 allows interrupts of priority level 0-3,
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//! and interrupts with a numerical priority of 4 and greater are blocked.
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//!
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//! \return None.
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//
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//*****************************************************************************
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static inline void
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Interrupt_setPriorityMask(uint32_t priorityMask)
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{
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//
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// Set the priority mask.
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//
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CPU_setBASEPRI(priorityMask);
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}
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//*****************************************************************************
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//
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//! Gets the priority masking level.
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//!
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//! This function gets the current setting of the interrupt priority masking
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//! level. The value returned is the priority level such that all interrupts
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//! of that and lesser priority are masked. A value of 0 means that priority
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//! masking is disabled.
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//!
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//! Smaller numbers correspond to higher interrupt priorities. So for example
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//! a priority level mask of 4 allows interrupts of priority level 0-3,
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//! and interrupts with a numerical priority of 4 and greater are blocked.
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//!
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//! \return Returns the value of the interrupt priority level mask.
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//
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//*****************************************************************************
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static inline uint32_t
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Interrupt_getPriorityMask(void)
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{
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//
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// Return the current priority mask.
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//
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|
|
return((uint32_t)CPU_getBASEPRI());
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Enables the processor to sleep when exiting an ISR.
|
||
|
|
//!
|
||
|
|
//! This function enables the processor to sleep when exiting an ISR. For low
|
||
|
|
//! power operation, this is ideal as power cycles are not wasted with the
|
||
|
|
//! processing required for waking up from an ISR and going back to sleep.
|
||
|
|
//!
|
||
|
|
//! \return None
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
static inline void
|
||
|
|
Interrupt_enableSleepOnISRExit(void)
|
||
|
|
{
|
||
|
|
HWREG(NVIC_BASE + NVIC_O_SCR) |= NVIC_SCR_SLEEPONEXIT;
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Disables the processor to sleep when exiting an ISR.
|
||
|
|
//!
|
||
|
|
//! This function disables the processor to sleep when exiting an ISR.
|
||
|
|
//!
|
||
|
|
//! \return None
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
static inline void
|
||
|
|
Interrupt_disableSleepOnISRExit(void)
|
||
|
|
{
|
||
|
|
HWREG(NVIC_BASE + NVIC_O_SCR) &= ~NVIC_SCR_SLEEPONEXIT;
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Unregisters the function to be called when an interrupt occurs.
|
||
|
|
//!
|
||
|
|
//! This function is used to indicate that no handler should be called when the
|
||
|
|
//! given interrupt is asserted to the processor. The interrupt source is
|
||
|
|
//! automatically disabled (via Interrupt_disableInterrupt()) if necessary.
|
||
|
|
//!
|
||
|
|
//! \sa Interrupt_registerInterrupt() for important information about
|
||
|
|
//! registering interrupt handlers.
|
||
|
|
//!
|
||
|
|
//! See \link Interrupt_enable() \endlink for details about the interrupt
|
||
|
|
//! parameter
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
static inline void
|
||
|
|
Interrupt_unregisterHandler(uint32_t interruptNum)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT(interruptNum < NUM_INTERRUPTS);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Reset the interrupt handler.
|
||
|
|
//
|
||
|
|
vectorTableRAM[interruptNum] = Interrupt_defaultHandler;
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Registers a function to be called when an interrupt occurs.
|
||
|
|
//!
|
||
|
|
//! \param interruptNum specifies the interrupt in question.
|
||
|
|
//! \param intHandler is a pointer to the function to be called.
|
||
|
|
//!
|
||
|
|
//! \note The use of this function (directly or indirectly via a peripheral
|
||
|
|
//! driver interrupt register function) moves the interrupt vector table from
|
||
|
|
//! flash to SRAM. Therefore, care must be taken when linking the application
|
||
|
|
//! to ensure that the SRAM vector table is located at the beginning of SRAM,
|
||
|
|
//! otherwise the NVIC does not look in the correct portion of memory for the
|
||
|
|
//! vector table (it requires the vector table be on a 1 kB memory alignment).
|
||
|
|
//! Normally, the SRAM vector table is so placed via the use of linker scripts.
|
||
|
|
//! See the discussion of compile-time versus run-time interrupt handler
|
||
|
|
//! registration in the introduction to this chapter.
|
||
|
|
//!
|
||
|
|
//! \note This function is only used if the customer wants to specify the
|
||
|
|
//! interrupt handler at run time. In most cases, this is done through means
|
||
|
|
//! of the user setting the ISR function pointer in the startup file. Refer
|
||
|
|
//! Refer to the Module Operation section for more details.
|
||
|
|
//!
|
||
|
|
//! See \link Interrupt_enable() \endlink for details about the interrupt
|
||
|
|
//! parameter
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
extern void
|
||
|
|
Interrupt_registerHandler(uint32_t interruptNum, void (*intHandler)(void));
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Enables an interrupt in interrupt controller.
|
||
|
|
//!
|
||
|
|
//! \param interruptNum is the interrupt to be enabled.
|
||
|
|
//!
|
||
|
|
//! This function enables the specified interrupt in the interrupt controller.
|
||
|
|
//! The parameter interruptNum can take any of the valid interrupts from
|
||
|
|
//! hw_ints.h file. Other enables for the interrupt (such as at the peripheral
|
||
|
|
//! level) are unaffected by this function.
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
extern void
|
||
|
|
Interrupt_enable(uint32_t interruptNum);
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Disables an interrupt in interrupt controller.
|
||
|
|
//!
|
||
|
|
//! \param interruptNum is the interrupt to be disabled.
|
||
|
|
//!
|
||
|
|
//! This function disables the specified interrupt in the interrupt controller.
|
||
|
|
//! The parameter interruptNum can take any of the valid interrupts from
|
||
|
|
//! hw_ints.h file. Other enables for the interrupt (such as at the peripheral
|
||
|
|
//! level) are unaffected by this function.
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
extern void
|
||
|
|
Interrupt_disable(uint32_t interruptNum);
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Returns if a peripheral interrupt is enabled.
|
||
|
|
//!
|
||
|
|
//! \param interruptNum is the interrupt to be checked.
|
||
|
|
//!
|
||
|
|
//! This function checks if the specified interrupt is enabled in the interrupt
|
||
|
|
//! controller. The \e interruptNum parameter must be one of the valid
|
||
|
|
//! interrupts defined in the inc/hw_ints.h header file.
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
extern bool
|
||
|
|
Interrupt_isEnabled(uint32_t interruptNum);
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Pends an interrupt.
|
||
|
|
//!
|
||
|
|
//! \param interruptNum specifies the interrupt to be pended.
|
||
|
|
//!
|
||
|
|
//! The specified interrupt is pended in the interrupt controller. Pending an
|
||
|
|
//! interrupt causes the interrupt controller to execute the corresponding
|
||
|
|
//! interrupt handler at the next available time, based on the current
|
||
|
|
//! interrupt state priorities. For example, if called by a higher priority
|
||
|
|
//! interrupt handler, the specified interrupt handler is not called until
|
||
|
|
//! after the current interrupt handler has completed execution. The interrupt
|
||
|
|
//! must have been enabled for it to be called.
|
||
|
|
//!
|
||
|
|
//! See \link Interrupt_enable() \endlink for details about the
|
||
|
|
//! interrupt parameter
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
extern void
|
||
|
|
Interrupt_pend(uint32_t interruptNum);
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Un-pends an interrupt.
|
||
|
|
//!
|
||
|
|
//! \param interruptNum specifies the interrupt to be un-pended.
|
||
|
|
//!
|
||
|
|
//! The specified interrupt is un-pended in the interrupt controller. This
|
||
|
|
//! will cause any previously generated interrupts that have not been handled
|
||
|
|
//! yet (due to higher priority interrupts or the interrupt no having been
|
||
|
|
//! enabled yet) to be discarded.
|
||
|
|
//!
|
||
|
|
//! See \link Interrupt_enable() \endlink for details about the interrupt
|
||
|
|
//! parameter
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
extern void
|
||
|
|
Interrupt_unpend(uint32_t interruptNum);
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Sets the priority of an interrupt.
|
||
|
|
//!
|
||
|
|
//! \param interruptNum specifies the interrupt in question.
|
||
|
|
//! \param priority specifies the priority of the interrupt.
|
||
|
|
//!
|
||
|
|
//! This function is used to set the priority of an interrupt. When multiple
|
||
|
|
//! interrupts are asserted simultaneously, the ones with the highest priority
|
||
|
|
//! are processed before the lower priority interrupts. Smaller numbers
|
||
|
|
//! correspond to higher interrupt priorities; priority 0 is the highest
|
||
|
|
//! interrupt priority.
|
||
|
|
//!
|
||
|
|
//! The hardware priority mechanism only looks at the upper N bits of the
|
||
|
|
//! priority level, so any prioritization must be performed in those bits.
|
||
|
|
//! The remaining bits can be used to sub-prioritize the interrupt sources,
|
||
|
|
//! and may be used by the hardware priority mechanism on a future part. This
|
||
|
|
//! arrangement allows priorities to migrate to different NVIC implementations
|
||
|
|
//! without changing the gross prioritization of the interrupts.
|
||
|
|
//!
|
||
|
|
//! See \link Interrupt_enable() \endlink for details about the interrupt
|
||
|
|
//! parameter
|
||
|
|
//!
|
||
|
|
//! \return None.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
extern void
|
||
|
|
Interrupt_setPriority(uint32_t interruptNum, uint32_t priority);
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Gets the priority of an interrupt.
|
||
|
|
//!
|
||
|
|
//! \param interruptNum specifies the interrupt in question.
|
||
|
|
//!
|
||
|
|
//! This function gets the priority of an interrupt. See
|
||
|
|
//! Interrupt_setPriority() for a definition of the priority value.
|
||
|
|
//!
|
||
|
|
//! See \link Interrupt_enable() \endlink for details about the interrupt
|
||
|
|
//! parameter
|
||
|
|
//!
|
||
|
|
//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
|
||
|
|
//! specified.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
extern uint32_t
|
||
|
|
Interrupt_getPriority(uint32_t interruptNum);
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
//! Initializes all the ISRs in the RAM vector table.
|
||
|
|
//!
|
||
|
|
//! \param srcVectorTable is source vector table array
|
||
|
|
//! \param dstVectorTable is destination vector table array
|
||
|
|
//!
|
||
|
|
//! This function initializes all the ISRs in the RAM vector table. It copies
|
||
|
|
//! the ISR addresses from temporary source table to destination RAM vector
|
||
|
|
//! table. The \e srcVectorTable can be preinitialised table which can be used
|
||
|
|
//! to initialize vector table in one go. \e dstVectorTable can be the RAM
|
||
|
|
//! vector table to be populated.
|
||
|
|
//!
|
||
|
|
//! \return None
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
extern void
|
||
|
|
Interrupt_initRAMVectorTable(void (*srcVectorTable[])(void),
|
||
|
|
void (*dstVectorTable[])(void));
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// Close the Doxygen group.
|
||
|
|
//! @}
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// Mark the end of the C bindings section for C++ compilers.
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif // INTERRUPT_H
|