304 lines
16 KiB
C
304 lines
16 KiB
C
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//###########################################################################
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//
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// FILE: hw_udma.h
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//
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// TITLE: Definitions for the UDMA registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_UDMA_H
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#define HW_UDMA_H
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//*************************************************************************************************
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//
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// The following are defines for the UDMA register offsets
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//
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//*************************************************************************************************
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#define UDMA_O_DMASRCENDP 0x0U // DMA Channel Source Address End Pointer
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#define UDMA_O_DMADSTENDP 0x4U // DMA Channel Destination Address End Pointer
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#define UDMA_O_DMACHCTL 0x8U // DMA Channel Control Word
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#define UDMA_O_DMASTAT 0x0U // DMA Status
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#define UDMA_O_DMACFG 0x4U // DMA Configuration
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#define UDMA_O_DMACTLBASE 0x8U // DMA Channel Control Base Pointer
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#define UDMA_O_DMAALTBASE 0xCU // DMA Alternate Channel Control Base Pointer
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#define UDMA_O_DMASWREQ 0x14U // DMA Channel Software Request
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#define UDMA_O_DMAUSEBURSTSET 0x18U // DMA Channel Useburst Set
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#define UDMA_O_DMAUSEBURSTCLR 0x1CU // DMA Channel Useburst Clear
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#define UDMA_O_DMAREQMASKSET 0x20U // DMA Channel Request Mask Set
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#define UDMA_O_DMAREQMASKCLR 0x24U // DMA Channel Request Mask Clear
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#define UDMA_O_DMAENASET 0x28U // DMA Channel Enable Set
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#define UDMA_O_DMAENACLR 0x2CU // DMA Channel Enable Clear
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#define UDMA_O_DMAALTSET 0x30U // DMA Channel Primary Alternate Set
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#define UDMA_O_DMAALTCLR 0x34U // DMA Channel Primary Alternate Clear
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#define UDMA_O_DMAPRIOSET 0x38U // DMA Channel Priority Set
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#define UDMA_O_DMAPRIOCLR 0x3CU // DMA Channel Priority Clear
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#define UDMA_O_DMAERRCLR 0x4CU // DMA Bus Error Clear
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#define UDMA_O_DMACHMAP0 0x510U // DMA Channel Map Select 0
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#define UDMA_O_DMACHMAP1 0x514U // DMA Channel Map Select 1
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#define UDMA_O_DMACHMAP2 0x518U // DMA Channel Map Select 2
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#define UDMA_O_DMACHMAP3 0x51CU // DMA Channel Map Select 3
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#define UDMA_O_DMAPERIPHID4 0xFD0U // DMA Peripheral Identification 4
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#define UDMA_O_DMAPERIPHID0 0xFE0U // DMA Peripheral Identification 0
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#define UDMA_O_DMAPERIPHID1 0xFE4U // DMA Peripheral Identification 1
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#define UDMA_O_DMAPERIPHID2 0xFE8U // DMA Peripheral Identification 2
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#define UDMA_O_DMAPERIPHID3 0xFECU // DMA Peripheral Identification 3
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#define UDMA_O_DMAPCELLID0 0xFF0U // DMA PrimeCell Identification 0
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#define UDMA_O_DMAPCELLID1 0xFF4U // DMA PrimeCell Identification 1
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#define UDMA_O_DMAPCELLID2 0xFF8U // DMA PrimeCell Identification 2
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#define UDMA_O_DMAPCELLID3 0xFFCU // DMA PrimeCell Identification 3
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMACHCTL register
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//
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//*************************************************************************************************
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#define UDMA_DMACHCTL_XFERMODE_S 0U
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#define UDMA_DMACHCTL_XFERMODE_M 0x7U // DMA Transfer Mode
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#define UDMA_DMACHCTL_NXTUSEBURST 0x8U // Next Useburst
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#define UDMA_DMACHCTL_XFERSIZE_S 4U
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#define UDMA_DMACHCTL_XFERSIZE_M 0x3FF0U // Transfer Size (minus 1)
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#define UDMA_DMACHCTL_ARBSIZE_S 14U
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#define UDMA_DMACHCTL_ARBSIZE_M 0x3C000U // Arbitration Size
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#define UDMA_DMACHCTL_SRCPROT0 0x40000U // Source Privilege Access
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#define UDMA_DMACHCTL_DSTPROT0 0x200000U // Destination Privilege Access
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#define UDMA_DMACHCTL_SRCSIZE_S 24U
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#define UDMA_DMACHCTL_SRCSIZE_M 0x3000000U // Source Data Size
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#define UDMA_DMACHCTL_SRCINC_S 26U
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#define UDMA_DMACHCTL_SRCINC_M 0xC000000U // Source Address Increment
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#define UDMA_DMACHCTL_DSTSIZE_S 28U
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#define UDMA_DMACHCTL_DSTSIZE_M 0x30000000U // Destination Data Size
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#define UDMA_DMACHCTL_DSTINC_S 30U
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#define UDMA_DMACHCTL_DSTINC_M 0xC0000000U // Destination Address Increment
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMASTAT register
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//
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//*************************************************************************************************
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#define UDMA_DMASTAT_MASTEN 0x1U // Master Enable Status
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#define UDMA_DMASTAT_STATE_S 4U
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#define UDMA_DMASTAT_STATE_M 0xF0U // Control State Machine Status
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#define UDMA_DMASTAT_DMACHANS_S 16U
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#define UDMA_DMASTAT_DMACHANS_M 0x1F0000U // Available DMA Channels Minus 1
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMACFG register
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//
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//*************************************************************************************************
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#define UDMA_DMACFG_MASTEN 0x1U // Controller Master Enable
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMACTLBASE register
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//
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//*************************************************************************************************
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#define UDMA_DMACTLBASE_ADDR_S 10U
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#define UDMA_DMACTLBASE_ADDR_M 0xFFFFFC00U // Channel Control Base Address
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMAERRCLR register
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//
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//*************************************************************************************************
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#define UDMA_DMAERRCLR_ERRCLR 0x1U // DMA Bus Error Status
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMACHMAP0 register
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//
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//*************************************************************************************************
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#define UDMA_DMACHMAP0_CH0SEL_S 0U
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#define UDMA_DMACHMAP0_CH0SEL_M 0xFU // DMA Channel 0 Source Select
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#define UDMA_DMACHMAP0_CH1SEL_S 4U
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#define UDMA_DMACHMAP0_CH1SEL_M 0xF0U // DMA Channel 1 Source Select
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#define UDMA_DMACHMAP0_CH2SEL_S 8U
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#define UDMA_DMACHMAP0_CH2SEL_M 0xF00U // DMA Channel 2 Source Select
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#define UDMA_DMACHMAP0_CH3SEL_S 12U
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#define UDMA_DMACHMAP0_CH3SEL_M 0xF000U // DMA Channel 3 Source Select
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#define UDMA_DMACHMAP0_CH4SEL_S 16U
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#define UDMA_DMACHMAP0_CH4SEL_M 0xF0000U // DMA Channel 4 Source Select
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#define UDMA_DMACHMAP0_CH5SEL_S 20U
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#define UDMA_DMACHMAP0_CH5SEL_M 0xF00000U // DMA Channel 5 Source Select
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#define UDMA_DMACHMAP0_CH6SEL_S 24U
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#define UDMA_DMACHMAP0_CH6SEL_M 0xF000000U // DMA Channel 6 Source Select
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#define UDMA_DMACHMAP0_CH7SEL_S 28U
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#define UDMA_DMACHMAP0_CH7SEL_M 0xF0000000U // DMA Channel 7 Source Select
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMACHMAP1 register
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//
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//*************************************************************************************************
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#define UDMA_DMACHMAP1_CH8SEL_S 0U
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#define UDMA_DMACHMAP1_CH8SEL_M 0xFU // DMA Channel 8 Source Select
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#define UDMA_DMACHMAP1_CH9SEL_S 4U
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#define UDMA_DMACHMAP1_CH9SEL_M 0xF0U // DMA Channel 9 Source Select
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#define UDMA_DMACHMAP1_CH10SEL_S 8U
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#define UDMA_DMACHMAP1_CH10SEL_M 0xF00U // DMA Channel 10 Source Select
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#define UDMA_DMACHMAP1_CH11SEL_S 12U
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#define UDMA_DMACHMAP1_CH11SEL_M 0xF000U // DMA Channel 11 Source Select
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#define UDMA_DMACHMAP1_CH12SEL_S 16U
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#define UDMA_DMACHMAP1_CH12SEL_M 0xF0000U // DMA Channel 12 Source Select
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#define UDMA_DMACHMAP1_CH13SEL_S 20U
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#define UDMA_DMACHMAP1_CH13SEL_M 0xF00000U // DMA Channel 13 Source Select
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#define UDMA_DMACHMAP1_CH14SEL_S 24U
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#define UDMA_DMACHMAP1_CH14SEL_M 0xF000000U // DMA Channel 14 Source Select
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#define UDMA_DMACHMAP1_CH15SEL_S 28U
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#define UDMA_DMACHMAP1_CH15SEL_M 0xF0000000U // DMA Channel 15 Source Select
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMACHMAP2 register
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//
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//*************************************************************************************************
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#define UDMA_DMACHMAP2_CH16SEL_S 0U
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#define UDMA_DMACHMAP2_CH16SEL_M 0xFU // DMA Channel 16 Source Select
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#define UDMA_DMACHMAP2_CH17SEL_S 4U
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#define UDMA_DMACHMAP2_CH17SEL_M 0xF0U // DMA Channel 17 Source Select
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#define UDMA_DMACHMAP2_CH18SEL_S 8U
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#define UDMA_DMACHMAP2_CH18SEL_M 0xF00U // DMA Channel 18 Source Select
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#define UDMA_DMACHMAP2_CH19SEL_S 12U
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#define UDMA_DMACHMAP2_CH19SEL_M 0xF000U // DMA Channel 19 Source Select
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#define UDMA_DMACHMAP2_CH20SEL_S 16U
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#define UDMA_DMACHMAP2_CH20SEL_M 0xF0000U // DMA Channel 20 Source Select
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#define UDMA_DMACHMAP2_CH21SEL_S 20U
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#define UDMA_DMACHMAP2_CH21SEL_M 0xF00000U // DMA Channel 21 Source Select
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#define UDMA_DMACHMAP2_CH22SEL_S 24U
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#define UDMA_DMACHMAP2_CH22SEL_M 0xF000000U // DMA Channel 22 Source Select
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#define UDMA_DMACHMAP2_CH23SEL_S 28U
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#define UDMA_DMACHMAP2_CH23SEL_M 0xF0000000U // DMA Channel 23 Source Select
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMACHMAP3 register
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//
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//*************************************************************************************************
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#define UDMA_DMACHMAP3_CH24SEL_S 0U
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#define UDMA_DMACHMAP3_CH24SEL_M 0xFU // DMA Channel 24 Source Select
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#define UDMA_DMACHMAP3_CH25SEL_S 4U
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#define UDMA_DMACHMAP3_CH25SEL_M 0xF0U // DMA Channel 25 Source Select
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#define UDMA_DMACHMAP3_CH26SEL_S 8U
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#define UDMA_DMACHMAP3_CH26SEL_M 0xF00U // DMA Channel 26 Source Select
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#define UDMA_DMACHMAP3_CH27SEL_S 12U
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#define UDMA_DMACHMAP3_CH27SEL_M 0xF000U // DMA Channel 27 Source Select
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#define UDMA_DMACHMAP3_CH28SEL_S 16U
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#define UDMA_DMACHMAP3_CH28SEL_M 0xF0000U // DMA Channel 28 Source Select
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#define UDMA_DMACHMAP3_CH29SEL_S 20U
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#define UDMA_DMACHMAP3_CH29SEL_M 0xF00000U // DMA Channel 29 Source Select
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#define UDMA_DMACHMAP3_CH30SEL_S 24U
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#define UDMA_DMACHMAP3_CH30SEL_M 0xF000000U // DMA Channel 30 Source Select
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#define UDMA_DMACHMAP3_CH31SEL_S 28U
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#define UDMA_DMACHMAP3_CH31SEL_M 0xF0000000U // DMA Channel 31 Source Select
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMAPeriphID4 register
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//
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//*************************************************************************************************
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#define UDMA_DMAPERIPHID4_PID4_S 0U
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#define UDMA_DMAPERIPHID4_PID4_M 0xFFU // DMA Peripheral ID Register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMAPeriphID0 register
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//
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//*************************************************************************************************
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#define UDMA_DMAPERIPHID0_PID0_S 0U
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#define UDMA_DMAPERIPHID0_PID0_M 0xFFU // DMA Peripheral ID Register [7:0]
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMAPeriphID1 register
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//
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//*************************************************************************************************
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#define UDMA_DMAPERIPHID1_PID1_S 0U
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#define UDMA_DMAPERIPHID1_PID1_M 0xFFU // DMA Peripheral ID Register [15:8]
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMAPeriphID2 register
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//
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//*************************************************************************************************
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#define UDMA_DMAPERIPHID2_PID2_S 0U
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#define UDMA_DMAPERIPHID2_PID2_M 0xFFU // DMA Peripheral ID Register [23:16]
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMAPeriphID3 register
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//
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//*************************************************************************************************
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#define UDMA_DMAPERIPHID3_PID3_S 0U
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#define UDMA_DMAPERIPHID3_PID3_M 0xFFU // DMA Peripheral ID Register [31:24]
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMAPCellID0 register
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//
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//*************************************************************************************************
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#define UDMA_DMAPCELLID0_CID0_S 0U
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#define UDMA_DMAPCELLID0_CID0_M 0xFFU // DMA PrimeCell ID Register [7:0]
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMAPCellID1 register
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//
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//*************************************************************************************************
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#define UDMA_DMAPCELLID1_CID1_S 0U
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#define UDMA_DMAPCELLID1_CID1_M 0xFFU // DMA PrimeCell ID Register [15:8]
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMAPCellID2 register
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//
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//*************************************************************************************************
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#define UDMA_DMAPCELLID2_CID2_S 0U
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#define UDMA_DMAPCELLID2_CID2_M 0xFFU // DMA PrimeCell ID Register [23:16]
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the DMAPCellID3 register
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//
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//*************************************************************************************************
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#define UDMA_DMAPCELLID3_CID3_S 0U
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#define UDMA_DMAPCELLID3_CID3_M 0xFFU // DMA PrimeCell ID Register [31:24]
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#endif
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