280 lines
18 KiB
C
280 lines
18 KiB
C
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//###########################################################################
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//
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// FILE: hw_cmmpu.h
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//
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// TITLE: Definitions for the CMMPU registers.
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//
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//###########################################################################
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef HW_CMMPU_H
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#define HW_CMMPU_H
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//*************************************************************************************************
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//
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// The following are defines for the CMMPU register offsets
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//
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//*************************************************************************************************
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#define CMMPU_O_MPU_CONTROL_REG 0x0U // MPU control regster
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#define CMMPU_O_ACC_VIO_INTEN 0x20U // Access violation interrupt enable
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#define CMMPU_O_ACC_VIO_FLAGS 0x24U // Access violation flag register
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#define CMMPU_O_ACC_VIO_FLAGS_SET 0x28U // Acesss violation set register
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#define CMMPU_O_ACC_VIO_FLAGS_CLR 0x2CU // Access violation clear register
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#define CMMPU_O_ACC_VIO_ADDR_REG 0x30U // Access violation address register
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#define CMMPU_O_REGION0_STARTADDRESSS 0x40U // Region 0 start address register
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#define CMMPU_O_REGION0_CONFIG 0x44U // Region 0 configuration register
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#define CMMPU_O_REGION1_STARTADDRESSS 0x48U // Region 1 start address register
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#define CMMPU_O_REGION1_CONFIG 0x4CU // Region 1 configuration register
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#define CMMPU_O_REGION2_STARTADDRESSS 0x50U // Region 2 start address register
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#define CMMPU_O_REGION2_CONFIG 0x54U // Region 2 configuration register
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#define CMMPU_O_REGION3_STARTADDRESSS 0x58U // Region 3 start address register
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#define CMMPU_O_REGION3_CONFIG 0x5CU // Region 3 configuration register
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#define CMMPU_O_REGION4_STARTADDRESSS 0x60U // Region 4 start address register
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#define CMMPU_O_REGION4_CONFIG 0x64U // Region 4 configuration register
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#define CMMPU_O_REGION5_STARTADDRESSS 0x68U // Region 5 start address register
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#define CMMPU_O_REGION5_CONFIG 0x6CU // Region 5 configuration register
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#define CMMPU_O_REGION6_STARTADDRESSS 0x70U // Region 6 start address register
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#define CMMPU_O_REGION6_CONFIG 0x74U // Region 6 configuration register
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#define CMMPU_O_REGION7_STARTADDRESSS 0x78U // Region 7 start address register
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#define CMMPU_O_REGION7_CONFIG 0x7CU // Region 7 configuration register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the MPU_CONTROL_REG register
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//
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//*************************************************************************************************
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#define CMMPU_MPU_CONTROL_REG_ENABLE 0x1U // Global Enable register
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ACC_VIO_INTEN register
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//
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//*************************************************************************************************
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#define CMMPU_ACC_VIO_INTEN_INTEN 0x1U // Interrupt enable register
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#define CMMPU_ACC_VIO_INTEN_KEY_S 16U
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#define CMMPU_ACC_VIO_INTEN_KEY_M 0xFFFF0000U // KEY to allow write access
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ACC_VIO_FLAGS register
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//
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//*************************************************************************************************
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#define CMMPU_ACC_VIO_FLAGS_RD 0x1U // Read access violation flag
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#define CMMPU_ACC_VIO_FLAGS_WR 0x2U // Write access violation flag
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ACC_VIO_FLAGS_SET register
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//
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//*************************************************************************************************
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#define CMMPU_ACC_VIO_FLAGS_SET_RD 0x1U // Read access violation flag set
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#define CMMPU_ACC_VIO_FLAGS_SET_WR 0x2U // Write access violation flag set
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#define CMMPU_ACC_VIO_FLAGS_SET_KEY_S 16U
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#define CMMPU_ACC_VIO_FLAGS_SET_KEY_M 0xFFFF0000U // KEY to allow write access
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the ACC_VIO_FLAGS_CLR register
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//
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//*************************************************************************************************
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#define CMMPU_ACC_VIO_FLAGS_CLR_RD 0x1U // Read access violation flag clear
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#define CMMPU_ACC_VIO_FLAGS_CLR_WR 0x2U // Write access violation flag clear
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#define CMMPU_ACC_VIO_FLAGS_CLR_KEY_S 16U
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#define CMMPU_ACC_VIO_FLAGS_CLR_KEY_M 0xFFFF0000U // KEY to allow write access
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the REGION0_CONFIG register
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//
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//*************************************************************************************************
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#define CMMPU_REGION0_CONFIG_ENABLE 0x1U // Region Enable bit
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#define CMMPU_REGION0_CONFIG_PROT_TYPE_S 4U
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#define CMMPU_REGION0_CONFIG_PROT_TYPE_M 0x30U // Access permission configuration
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// bits
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#define CMMPU_REGION0_CONFIG_SIZE_S 8U
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#define CMMPU_REGION0_CONFIG_SIZE_M 0x1F00U // Size of the region 0
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#define CMMPU_REGION0_CONFIG_SUBREGION0_DISABLE 0x10000U // Sub region 0 disable bit
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#define CMMPU_REGION0_CONFIG_SUBREGION1_DISABLE 0x20000U // Sub region 1 disable bit
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#define CMMPU_REGION0_CONFIG_SUBREGION2_DISABLE 0x40000U // Sub region 2 disable bit
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#define CMMPU_REGION0_CONFIG_SUBREGION3_DISABLE 0x80000U // Sub region 3 disable bit
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#define CMMPU_REGION0_CONFIG_SUBREGION4_DISABLE 0x100000U // Sub region 4 disable bit
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#define CMMPU_REGION0_CONFIG_SUBREGION5_DISABLE 0x200000U // Sub region 5 disable bit
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#define CMMPU_REGION0_CONFIG_SUBREGION6_DISABLE 0x400000U // Sub region 6 disable bit
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#define CMMPU_REGION0_CONFIG_SUBREGION7_DISABLE 0x800000U // Sub region 7 disable bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the REGION1_CONFIG register
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//
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//*************************************************************************************************
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#define CMMPU_REGION1_CONFIG_ENABLE 0x1U // Region Enable bit
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#define CMMPU_REGION1_CONFIG_PROT_TYPE_S 4U
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#define CMMPU_REGION1_CONFIG_PROT_TYPE_M 0x30U // Access permission configuration
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// bits
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#define CMMPU_REGION1_CONFIG_SIZE_S 8U
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#define CMMPU_REGION1_CONFIG_SIZE_M 0x1F00U // Size of the region 1
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#define CMMPU_REGION1_CONFIG_SUBREGION0_DISABLE 0x10000U // Sub region 0 disable bit
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#define CMMPU_REGION1_CONFIG_SUBREGION1_DISABLE 0x20000U // Sub region 1 disable bit
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#define CMMPU_REGION1_CONFIG_SUBREGION2_DISABLE 0x40000U // Sub region 2 disable bit
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#define CMMPU_REGION1_CONFIG_SUBREGION3_DISABLE 0x80000U // Sub region 3 disable bit
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#define CMMPU_REGION1_CONFIG_SUBREGION4_DISABLE 0x100000U // Sub region 4 disable bit
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#define CMMPU_REGION1_CONFIG_SUBREGION5_DISABLE 0x200000U // Sub region 5 disable bit
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#define CMMPU_REGION1_CONFIG_SUBREGION6_DISABLE 0x400000U // Sub region 6 disable bit
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#define CMMPU_REGION1_CONFIG_SUBREGION7_DISABLE 0x800000U // Sub region 7 disable bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the REGION2_CONFIG register
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//
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//*************************************************************************************************
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#define CMMPU_REGION2_CONFIG_ENABLE 0x1U // Region Enable bit
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#define CMMPU_REGION2_CONFIG_PROT_TYPE_S 4U
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#define CMMPU_REGION2_CONFIG_PROT_TYPE_M 0x30U // Access permission configuration
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// bits
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#define CMMPU_REGION2_CONFIG_SIZE_S 8U
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#define CMMPU_REGION2_CONFIG_SIZE_M 0x1F00U // Size of the region 2
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#define CMMPU_REGION2_CONFIG_SUBREGION0_DISABLE 0x10000U // Sub region 0 disable bit
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#define CMMPU_REGION2_CONFIG_SUBREGION1_DISABLE 0x20000U // Sub region 1 disable bit
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#define CMMPU_REGION2_CONFIG_SUBREGION2_DISABLE 0x40000U // Sub region 2 disable bit
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#define CMMPU_REGION2_CONFIG_SUBREGION3_DISABLE 0x80000U // Sub region 3 disable bit
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#define CMMPU_REGION2_CONFIG_SUBREGION4_DISABLE 0x100000U // Sub region 4 disable bit
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#define CMMPU_REGION2_CONFIG_SUBREGION5_DISABLE 0x200000U // Sub region 5 disable bit
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#define CMMPU_REGION2_CONFIG_SUBREGION6_DISABLE 0x400000U // Sub region 6 disable bit
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#define CMMPU_REGION2_CONFIG_SUBREGION7_DISABLE 0x800000U // Sub region 7 disable bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the REGION3_CONFIG register
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//
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//*************************************************************************************************
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#define CMMPU_REGION3_CONFIG_ENABLE 0x1U // Region Enable bit
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#define CMMPU_REGION3_CONFIG_PROT_TYPE_S 4U
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#define CMMPU_REGION3_CONFIG_PROT_TYPE_M 0x30U // Access permission configuration
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// bits
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#define CMMPU_REGION3_CONFIG_SIZE_S 8U
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#define CMMPU_REGION3_CONFIG_SIZE_M 0x1F00U // Size of the region 3
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#define CMMPU_REGION3_CONFIG_SUBREGION0_DISABLE 0x10000U // Sub region 0 disable bit
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#define CMMPU_REGION3_CONFIG_SUBREGION1_DISABLE 0x20000U // Sub region 1 disable bit
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#define CMMPU_REGION3_CONFIG_SUBREGION2_DISABLE 0x40000U // Sub region 2 disable bit
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#define CMMPU_REGION3_CONFIG_SUBREGION3_DISABLE 0x80000U // Sub region 3 disable bit
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#define CMMPU_REGION3_CONFIG_SUBREGION4_DISABLE 0x100000U // Sub region 4 disable bit
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#define CMMPU_REGION3_CONFIG_SUBREGION5_DISABLE 0x200000U // Sub region 5 disable bit
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#define CMMPU_REGION3_CONFIG_SUBREGION6_DISABLE 0x400000U // Sub region 6 disable bit
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#define CMMPU_REGION3_CONFIG_SUBREGION7_DISABLE 0x800000U // Sub region 7 disable bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the REGION4_CONFIG register
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//
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//*************************************************************************************************
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#define CMMPU_REGION4_CONFIG_ENABLE 0x1U // Region Enable bit
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#define CMMPU_REGION4_CONFIG_PROT_TYPE_S 4U
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#define CMMPU_REGION4_CONFIG_PROT_TYPE_M 0x30U // Access permission configuration
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// bits
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#define CMMPU_REGION4_CONFIG_SIZE_S 8U
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#define CMMPU_REGION4_CONFIG_SIZE_M 0x1F00U // Size of the region 4
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#define CMMPU_REGION4_CONFIG_SUBREGION0_DISABLE 0x10000U // Sub region 0 disable bit
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#define CMMPU_REGION4_CONFIG_SUBREGION1_DISABLE 0x20000U // Sub region 1 disable bit
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#define CMMPU_REGION4_CONFIG_SUBREGION2_DISABLE 0x40000U // Sub region 2 disable bit
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#define CMMPU_REGION4_CONFIG_SUBREGION3_DISABLE 0x80000U // Sub region 3 disable bit
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#define CMMPU_REGION4_CONFIG_SUBREGION4_DISABLE 0x100000U // Sub region 4 disable bit
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#define CMMPU_REGION4_CONFIG_SUBREGION5_DISABLE 0x200000U // Sub region 5 disable bit
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#define CMMPU_REGION4_CONFIG_SUBREGION6_DISABLE 0x400000U // Sub region 6 disable bit
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#define CMMPU_REGION4_CONFIG_SUBREGION7_DISABLE 0x800000U // Sub region 7 disable bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the REGION5_CONFIG register
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//
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//*************************************************************************************************
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#define CMMPU_REGION5_CONFIG_ENABLE 0x1U // Region Enable bit
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#define CMMPU_REGION5_CONFIG_PROT_TYPE_S 4U
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#define CMMPU_REGION5_CONFIG_PROT_TYPE_M 0x30U // Access permission configuration
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// bits
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#define CMMPU_REGION5_CONFIG_SIZE_S 8U
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#define CMMPU_REGION5_CONFIG_SIZE_M 0x1F00U // Size of the region 5
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#define CMMPU_REGION5_CONFIG_SUBREGION0_DISABLE 0x10000U // Sub region 0 disable bit
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#define CMMPU_REGION5_CONFIG_SUBREGION1_DISABLE 0x20000U // Sub region 1 disable bit
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#define CMMPU_REGION5_CONFIG_SUBREGION2_DISABLE 0x40000U // Sub region 2 disable bit
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#define CMMPU_REGION5_CONFIG_SUBREGION3_DISABLE 0x80000U // Sub region 3 disable bit
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#define CMMPU_REGION5_CONFIG_SUBREGION4_DISABLE 0x100000U // Sub region 4 disable bit
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#define CMMPU_REGION5_CONFIG_SUBREGION5_DISABLE 0x200000U // Sub region 5 disable bit
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#define CMMPU_REGION5_CONFIG_SUBREGION6_DISABLE 0x400000U // Sub region 6 disable bit
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#define CMMPU_REGION5_CONFIG_SUBREGION7_DISABLE 0x800000U // Sub region 7 disable bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the REGION6_CONFIG register
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//
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//*************************************************************************************************
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#define CMMPU_REGION6_CONFIG_ENABLE 0x1U // Region Enable bit
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#define CMMPU_REGION6_CONFIG_PROT_TYPE_S 4U
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#define CMMPU_REGION6_CONFIG_PROT_TYPE_M 0x30U // Access permission configuration
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// bits
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#define CMMPU_REGION6_CONFIG_SIZE_S 8U
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#define CMMPU_REGION6_CONFIG_SIZE_M 0x1F00U // Size of the region 6
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#define CMMPU_REGION6_CONFIG_SUBREGION0_DISABLE 0x10000U // Sub region 0 disable bit
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#define CMMPU_REGION6_CONFIG_SUBREGION1_DISABLE 0x20000U // Sub region 1 disable bit
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#define CMMPU_REGION6_CONFIG_SUBREGION2_DISABLE 0x40000U // Sub region 2 disable bit
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#define CMMPU_REGION6_CONFIG_SUBREGION3_DISABLE 0x80000U // Sub region 3 disable bit
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#define CMMPU_REGION6_CONFIG_SUBREGION4_DISABLE 0x100000U // Sub region 4 disable bit
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#define CMMPU_REGION6_CONFIG_SUBREGION5_DISABLE 0x200000U // Sub region 5 disable bit
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#define CMMPU_REGION6_CONFIG_SUBREGION6_DISABLE 0x400000U // Sub region 6 disable bit
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#define CMMPU_REGION6_CONFIG_SUBREGION7_DISABLE 0x800000U // Sub region 7 disable bit
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//*************************************************************************************************
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//
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// The following are defines for the bit fields in the REGION7_CONFIG register
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//
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//*************************************************************************************************
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#define CMMPU_REGION7_CONFIG_ENABLE 0x1U // Region Enable bit
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#define CMMPU_REGION7_CONFIG_PROT_TYPE_S 4U
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#define CMMPU_REGION7_CONFIG_PROT_TYPE_M 0x30U // Access permission configuration
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// bits
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#define CMMPU_REGION7_CONFIG_SIZE_S 8U
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#define CMMPU_REGION7_CONFIG_SIZE_M 0x1F00U // Size of the region 7
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#define CMMPU_REGION7_CONFIG_SUBREGION0_DISABLE 0x10000U // Sub region 0 disable bit
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#define CMMPU_REGION7_CONFIG_SUBREGION1_DISABLE 0x20000U // Sub region 1 disable bit
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#define CMMPU_REGION7_CONFIG_SUBREGION2_DISABLE 0x40000U // Sub region 2 disable bit
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#define CMMPU_REGION7_CONFIG_SUBREGION3_DISABLE 0x80000U // Sub region 3 disable bit
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#define CMMPU_REGION7_CONFIG_SUBREGION4_DISABLE 0x100000U // Sub region 4 disable bit
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#define CMMPU_REGION7_CONFIG_SUBREGION5_DISABLE 0x200000U // Sub region 5 disable bit
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#define CMMPU_REGION7_CONFIG_SUBREGION6_DISABLE 0x400000U // Sub region 6 disable bit
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||
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#define CMMPU_REGION7_CONFIG_SUBREGION7_DISABLE 0x800000U // Sub region 7 disable bit
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||
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||
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||
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||
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#endif
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