656 lines
21 KiB
C
656 lines
21 KiB
C
//###########################################################################
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//
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// FILE: memcfg.c
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//
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// TITLE: CM SRAM config driver.
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//
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//###########################################################################
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// $TI Release: F2838x Support Library v3.04.00.00 $
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// $Release Date: Fri Feb 12 19:08:49 IST 2021 $
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// $Copyright:
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// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#include "memcfg.h"
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//*****************************************************************************
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//
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// MemCfg_lockConfig
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//
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//*****************************************************************************
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void
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MemCfg_lockConfig(uint32_t memSections)
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{
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//
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// Check the arguments.
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//
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ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_CX) ||
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((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_SX) ||
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((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_ROM) ||
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((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_PERIMEM)||
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((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_CMMSGX) ||
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(memSections == MEMCFG_SECT_ALL));
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//
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// Set the bit that blocks writes to the sections' configuration registers.
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//
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switch(memSections & MEMCFG_SECT_TYPE_MASK)
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{
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case MEMCFG_SECT_TYPE_CX:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_CXLOCK) |= (MEMCFG_SECT_NUM_MASK &
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memSections);
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break;
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case MEMCFG_SECT_TYPE_CMMSGX:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_CMMSGXLOCK) |= (MEMCFG_SECT_NUM_MASK
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& memSections);
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break;
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case MEMCFG_SECT_TYPE_SX:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_SXGROUP1_LOCK) |=
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(MEMCFG_SECT_NUM_MASK & memSections);
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break;
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case MEMCFG_SECT_TYPE_ROM:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_ROM_LOCK) |= (MEMCFG_SECT_NUM_MASK &
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memSections);
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break;
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case MEMCFG_SECT_TYPE_PERIMEM:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_LOCK) |=
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(MEMCFG_SECT_NUM_MASK & memSections);
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break;
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case MEMCFG_SECT_TYPE_MASK:
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//
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// Lock configuration for all sections.
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//
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HWREG(CMMEMCFG_BASE + MEMCFG_O_CXLOCK) |=
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(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_CX_ALL);
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HWREG(CMMEMCFG_BASE + MEMCFG_O_CMMSGXLOCK) |=
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(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_CMMSGX_ALL);
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HWREG(CMMEMCFG_BASE + MEMCFG_O_SXGROUP1_LOCK) |=
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(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_SX_ALL);
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HWREG(CMMEMCFG_BASE + MEMCFG_O_ROM_LOCK) |=
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(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_ROM);
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HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_LOCK) |=
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(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_PERIMEM_ALL);
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break;
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default:
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//
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// Do nothing. Invalid memSections. Make sure you aren't OR-ing
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// values for two different types of RAM.
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//
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break;
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}
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}
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//*****************************************************************************
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//
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// MemCfg_unlockConfig
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//
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//*****************************************************************************
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void
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MemCfg_unlockConfig(uint32_t memSections)
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{
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//
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// Check the arguments.
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//
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ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_CX) ||
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((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_SX) ||
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((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_ROM) ||
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((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_PERIMEM)||
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((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_CMMSGX) ||
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(memSections == MEMCFG_SECT_ALL));
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//
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// Clear the bit that blocks writes to the sections' configuration
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// registers.
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//
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switch(memSections & MEMCFG_SECT_TYPE_MASK)
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{
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case MEMCFG_SECT_TYPE_CX:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_CXLOCK) &=
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~(MEMCFG_SECT_NUM_MASK & memSections);
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break;
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case MEMCFG_SECT_TYPE_CMMSGX:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_CMMSGXLOCK) &=
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~(MEMCFG_SECT_NUM_MASK & memSections);
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break;
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case MEMCFG_SECT_TYPE_SX:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_SXGROUP1_LOCK) &=
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~(MEMCFG_SECT_NUM_MASK & memSections);
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break;
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case MEMCFG_SECT_TYPE_ROM:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_ROM_LOCK) &=
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~(MEMCFG_SECT_NUM_MASK & memSections);
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break;
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case MEMCFG_SECT_TYPE_PERIMEM:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_LOCK) &=
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~(MEMCFG_SECT_NUM_MASK & memSections);
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break;
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case MEMCFG_SECT_TYPE_MASK:
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//
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// Lock configuration for all sections.
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//
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HWREG(CMMEMCFG_BASE + MEMCFG_O_CXLOCK) &= ~((uint32_t)
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(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_CX_ALL));
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HWREG(CMMEMCFG_BASE + MEMCFG_O_CMMSGXLOCK) &= ~((uint32_t)
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(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_CMMSGX_ALL));
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HWREG(CMMEMCFG_BASE + MEMCFG_O_SXGROUP1_LOCK) &= ~((uint32_t)
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(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_SX_ALL));
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HWREG(CMMEMCFG_BASE + MEMCFG_O_ROM_LOCK) &= ~((uint32_t)
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(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_ROM));
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HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_LOCK) &= ~((uint32_t)
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(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_PERIMEM_ALL));
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break;
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default:
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//
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// Do nothing. Invalid memSections. Make sure you aren't OR-ing
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// values for two different types of RAM.
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//
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break;
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}
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}
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//*****************************************************************************
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//
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// MemCfg_setTestMode
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//
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//*****************************************************************************
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void
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MemCfg_setTestMode(uint32_t memSection, MemCfg_TestMode testMode)
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{
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uint32_t shiftVal = 0U;
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uint32_t maskVal;
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uint32_t regVal;
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uint32_t sectionNum;
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//
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// Check the arguments.
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//
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ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_CX) ||
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((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_SX) ||
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((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_ROM) ||
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((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_CMMSGX));
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//
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// Calculate how far the protect mode value needs to be shifted. Each
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// section number is represented by a bit in the lower word of memSection
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// and 2 bits in the corresponding TEST register.
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//
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sectionNum = memSection & MEMCFG_SECT_NUM_MASK;
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while(sectionNum != 1U)
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{
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sectionNum = sectionNum >> 1U;
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shiftVal += 2U;
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}
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maskVal = (uint32_t)MEMCFG_TESTMODE_M << shiftVal;
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regVal = ((uint32_t)testMode) << shiftVal;
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//
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// Write the test mode into the appropriate field
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//
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switch(memSection & MEMCFG_SECT_TYPE_MASK)
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{
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case MEMCFG_SECT_TYPE_CX:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_CXTEST) =
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((HWREG(CMMEMCFG_BASE + MEMCFG_O_CXTEST) & ~maskVal) | regVal);
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break;
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case MEMCFG_SECT_TYPE_CMMSGX:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_CMMSGXTEST) =
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((HWREG(CMMEMCFG_BASE + MEMCFG_O_CMMSGXTEST) & ~maskVal) | regVal);
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break;
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case MEMCFG_SECT_TYPE_SX:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_SXGROUP1_TEST) =
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((HWREG(CMMEMCFG_BASE + MEMCFG_O_CXTEST) & ~maskVal) | regVal);
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break;
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case MEMCFG_SECT_TYPE_ROM:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_ROM_TEST) =
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((HWREG(CMMEMCFG_BASE + MEMCFG_O_ROM_TEST) & ~maskVal) | regVal);
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break;
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default:
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//
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// Do nothing. Invalid memSection.
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//
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break;
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}
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}
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//*****************************************************************************
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//
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// MemCfg_initSections
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//
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//*****************************************************************************
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void
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MemCfg_initSections(uint32_t ramSections)
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{
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//
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// Check the arguments.
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//
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ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_CX) ||
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((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_SX) ||
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((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_CMMSGX) ||
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(ramSections == MEMCFG_SECT_ALL));
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//
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// Set the bit in the various initialization registers that starts
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// initialization.
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//
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switch(ramSections & MEMCFG_SECT_TYPE_MASK)
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{
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case MEMCFG_SECT_TYPE_CX:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_CXINIT) |=
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(MEMCFG_SECT_NUM_MASK & ramSections);
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break;
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case MEMCFG_SECT_TYPE_CMMSGX:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_CMMSGXINIT) |=
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(MEMCFG_SECT_NUM_MASK & ramSections);
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break;
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case MEMCFG_SECT_TYPE_SX:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_SXGROUP1_INIT) |=
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(MEMCFG_SECT_NUM_MASK & ramSections);
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break;
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case MEMCFG_SECT_TYPE_MASK:
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//
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// Initialize all sections.
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//
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HWREG(CMMEMCFG_BASE + MEMCFG_O_CXINIT) |=
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(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_CX_ALL);
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HWREG(CMMEMCFG_BASE + MEMCFG_O_CMMSGXINIT) |=
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(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_CMMSGX_ALL);
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HWREG(CMMEMCFG_BASE + MEMCFG_O_SXGROUP1_INIT) |=
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(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_SX_ALL);
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break;
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default:
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//
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// Do nothing. Invalid ramSections. Make sure you aren't OR-ing
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// values for two different types of RAM.
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//
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break;
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}
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}
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//*****************************************************************************
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//
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// MemCfg_getInitStatus
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//
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//*****************************************************************************
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bool
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MemCfg_getInitStatus(uint32_t ramSections)
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{
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uint32_t status;
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//
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// Check the arguments.
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//
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ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_CX) ||
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((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_SX) ||
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((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_CMMSGX) ||
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(ramSections == MEMCFG_SECT_ALL));
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//
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// Read registers containing the initialization complete status.
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//
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switch(ramSections & MEMCFG_SECT_TYPE_MASK)
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{
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case MEMCFG_SECT_TYPE_CX:
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status = HWREG(CMMEMCFG_BASE + MEMCFG_O_CXINITDONE);
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break;
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case MEMCFG_SECT_TYPE_CMMSGX:
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status = HWREG(CMMEMCFG_BASE + MEMCFG_O_CMMSGXINITDONE);
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break;
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case MEMCFG_SECT_TYPE_SX:
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status = HWREG(CMMEMCFG_BASE + MEMCFG_O_SXGROUP1_INITDONE);
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break;
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case MEMCFG_SECT_TYPE_MASK:
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//
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// Return the overall status.
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//
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if((HWREG(CMMEMCFG_BASE + MEMCFG_O_CXINITDONE) ==
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MEMCFG_SECT_CX_ALL) &&
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(HWREG(CMMEMCFG_BASE + MEMCFG_O_CMMSGXINITDONE) ==
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MEMCFG_SECT_CMMSGX_ALL) &&
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(HWREG(CMMEMCFG_BASE + MEMCFG_O_SXGROUP1_INITDONE) ==
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MEMCFG_SECT_SX_ALL))
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{
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status = MEMCFG_SECT_NUM_MASK;
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}
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else
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{
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status = 0x0U;
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}
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break;
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default:
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//
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// Invalid ramSections. Make sure you aren't OR-ing values for two
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// different types of RAM.
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//
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status = 0x0U;
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break;
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}
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return((ramSections & status) == (ramSections & MEMCFG_SECT_NUM_MASK));
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}
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//*****************************************************************************
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//
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// MemCfg_forceMemError
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//
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//*****************************************************************************
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void
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MemCfg_forceMemError(uint32_t memTypes)
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{
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//
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// Check the arguments.
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//
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ASSERT((memTypes == MEMCFG_SECT_ROM) ||
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(memTypes == MEMCFG_SECT_PERIMEM_EMAC) ||
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(memTypes == MEMCFG_SECT_PERIMEM_ETHERCAT) ||
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(memTypes == MEMCFG_SECT_ALL));
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//
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// Forces error in the selected memory.
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//
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switch(memTypes)
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{
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case MEMCFG_SECT_ROM:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_ROM_FORCE_ERROR) |=
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MEMCFG_ROM_FORCE_ERROR_FORCE_BOOTROM_ERROR;
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break;
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case MEMCFG_SECT_PERIMEM_EMAC:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_CONTROL) |=
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MEMCFG_PERI_MEM_TEST_CONTROL_EMAC_MEM_FORCE_ERROR;
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break;
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case MEMCFG_SECT_PERIMEM_ETHERCAT:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_CONTROL) |=
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MEMCFG_PERI_MEM_TEST_CONTROL_ETHERCAT_MEM_FORCE_ERROR;
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break;
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case MEMCFG_SECT_ALL:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_ROM_FORCE_ERROR) |=
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MEMCFG_ROM_FORCE_ERROR_FORCE_BOOTROM_ERROR;
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HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_CONTROL) |=
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MEMCFG_PERI_MEM_TEST_CONTROL_EMAC_MEM_FORCE_ERROR;
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HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_CONTROL) |=
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MEMCFG_PERI_MEM_TEST_CONTROL_ETHERCAT_MEM_FORCE_ERROR;
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break;
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default:
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//
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// Do nothing. Invalid memory.
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//
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break;
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}
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}
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//*****************************************************************************
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//
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// MemCfg_enablePeriMemTestMode
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//
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//*****************************************************************************
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void
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MemCfg_enablePeriMemTestMode(uint32_t memTypes)
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{
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//
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// Check the arguments.
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//
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ASSERT((memTypes == MEMCFG_SECT_PERIMEM_EMAC) ||
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(memTypes == MEMCFG_SECT_PERIMEM_ETHERCAT) ||
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(memTypes == MEMCFG_SECT_PERIMEM_ALL));
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//
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// Enables test mode for selected memory type.
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//
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switch(memTypes)
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{
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case MEMCFG_SECT_PERIMEM_EMAC:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_CONTROL) |=
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MEMCFG_PERI_MEM_TEST_CONTROL_EMAC_TEST_ENABLE;
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break;
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case MEMCFG_SECT_PERIMEM_ETHERCAT:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_CONTROL) |=
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MEMCFG_PERI_MEM_TEST_CONTROL_ETHERCAT_TEST_ENABLE;
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break;
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case MEMCFG_SECT_PERIMEM_ALL:
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HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_CONTROL) |=
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MEMCFG_PERI_MEM_TEST_CONTROL_EMAC_TEST_ENABLE;
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HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_CONTROL) |=
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MEMCFG_PERI_MEM_TEST_CONTROL_ETHERCAT_TEST_ENABLE;
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break;
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default:
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//
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// Do nothing. Invalid memory type.
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//
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break;
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}
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}
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//*****************************************************************************
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//
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// MemCfg_disablePeriMemTestMode
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
MemCfg_disablePeriMemTestMode(uint32_t memTypes)
|
|
{
|
|
//
|
|
// Check the arguments.
|
|
//
|
|
ASSERT((memTypes == MEMCFG_SECT_PERIMEM_EMAC) ||
|
|
(memTypes == MEMCFG_SECT_PERIMEM_ETHERCAT) ||
|
|
(memTypes == MEMCFG_SECT_PERIMEM_ALL));
|
|
|
|
//
|
|
// Disables test mode for selected memory type.
|
|
//
|
|
switch(memTypes)
|
|
{
|
|
case MEMCFG_SECT_PERIMEM_EMAC:
|
|
HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_CONTROL) &=
|
|
~MEMCFG_PERI_MEM_TEST_CONTROL_EMAC_TEST_ENABLE;
|
|
break;
|
|
|
|
case MEMCFG_SECT_PERIMEM_ETHERCAT:
|
|
HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_CONTROL) &=
|
|
~MEMCFG_PERI_MEM_TEST_CONTROL_ETHERCAT_TEST_ENABLE;
|
|
break;
|
|
|
|
case MEMCFG_SECT_PERIMEM_ALL:
|
|
HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_CONTROL) &=
|
|
~MEMCFG_PERI_MEM_TEST_CONTROL_EMAC_TEST_ENABLE;
|
|
|
|
HWREG(CMMEMCFG_BASE + MEMCFG_O_PERI_MEM_TEST_CONTROL) &=
|
|
~MEMCFG_PERI_MEM_TEST_CONTROL_ETHERCAT_TEST_ENABLE;
|
|
break;
|
|
|
|
default:
|
|
//
|
|
// Do nothing. Invalid memory type.
|
|
//
|
|
break;
|
|
}
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MemCfg_getUncorrErrorAddress
|
|
//
|
|
//*****************************************************************************
|
|
uint32_t
|
|
MemCfg_getUncorrErrorAddress(uint32_t stsFlag)
|
|
{
|
|
uint32_t errAddress;
|
|
|
|
//
|
|
// Gets address location of selected uncorrectable read/write error.
|
|
//
|
|
switch(stsFlag)
|
|
{
|
|
case MEMCFG_UCERR_M4READ:
|
|
case MEMCFG_UCERR_M4WRITE:
|
|
errAddress = HWREG(CMMEMORYERROR_BASE + MEMCFG_O_UCM4EADDR);
|
|
break;
|
|
|
|
case MEMCFG_UCERR_EMACREAD:
|
|
errAddress = HWREG(CMMEMORYERROR_BASE + MEMCFG_O_UCEMACEADDR);
|
|
break;
|
|
|
|
case MEMCFG_UCERR_UDMAREAD:
|
|
case MEMCFG_UCERR_UDMAWRITE:
|
|
errAddress = HWREG(CMMEMORYERROR_BASE + MEMCFG_O_UCUDMAEADDR);
|
|
break;
|
|
|
|
case MEMCFG_UCERR_ETHERCATMEMREAD:
|
|
errAddress = HWREG(CMMEMORYERROR_BASE + MEMCFG_O_UCETHERCATMEMREADDR);
|
|
break;
|
|
|
|
case MEMCFG_UCERR_EMACMEMREAD:
|
|
errAddress = HWREG(CMMEMORYERROR_BASE + MEMCFG_O_UCEMACMEMREADDR);
|
|
break;
|
|
|
|
default:
|
|
//
|
|
// Invalid stsFlag.
|
|
//
|
|
errAddress = 0x0U;
|
|
break;
|
|
}
|
|
return(errAddress);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MemCfg_getCorrErrorAddress
|
|
//
|
|
//*****************************************************************************
|
|
uint32_t
|
|
MemCfg_getCorrErrorAddress(uint32_t stsFlag)
|
|
{
|
|
uint32_t errAddress;
|
|
|
|
//
|
|
// Gets address location of selected uncorrectable read/write error.
|
|
//
|
|
switch(stsFlag)
|
|
{
|
|
case MEMCFG_CERR_M4READ:
|
|
case MEMCFG_CERR_M4WRITE:
|
|
errAddress = HWREG(CMMEMORYERROR_BASE + MEMCFG_O_CM4EADDR);
|
|
break;
|
|
|
|
case MEMCFG_CERR_EMACREAD:
|
|
errAddress = HWREG(CMMEMORYERROR_BASE + MEMCFG_O_CEMACEADDR);
|
|
break;
|
|
|
|
case MEMCFG_CERR_UDMAREAD:
|
|
case MEMCFG_CERR_UDMAWRITE:
|
|
errAddress = HWREG(CMMEMORYERROR_BASE + MEMCFG_O_CUDMAEADDR);
|
|
break;
|
|
|
|
default:
|
|
//
|
|
// Invalid stsFlag.
|
|
//
|
|
errAddress = 0x0U;
|
|
break;
|
|
}
|
|
return(errAddress);
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// MemCfg_getBusFaultAddress
|
|
//
|
|
//*****************************************************************************
|
|
uint32_t
|
|
MemCfg_getBusFaultAddress(uint32_t busMaster)
|
|
{
|
|
uint32_t offset, temp;
|
|
|
|
//
|
|
// Calculate the address offset for selected bus master.
|
|
//
|
|
offset = 0U;
|
|
temp = busMaster;
|
|
while(temp > 1U)
|
|
{
|
|
temp = temp >> 1U;
|
|
offset += (uint32_t)(MEMCFG_O_UDMABUSFAULTADDR -
|
|
MEMCFG_O_M4BUSFAULTADDR);
|
|
}
|
|
|
|
//
|
|
// Read and return the bus fault address at the calculated offset.
|
|
//
|
|
return(HWREG(CMMEMORYERROR_BASE + (uint32_t)MEMCFG_O_M4BUSFAULTADDR +
|
|
offset));
|
|
}
|