/* STATIC RAM */

MEMORY {
   RESET            : origin = 0x3FFFC0, length = 0x000002

   BOOT_STACK       : origin = 0x000002, length = 0x0001AE     /* Part of M0, BOOT rom will use this for stack */

/*
   RAMM0            : origin = 0x0001B0, length = 0x000250
*/
   RAM_FUNC			: origin = 0x0001B0, length = 0x000250

/*
   RAMM1            : origin = 0x000400, length = 0x000400
*/
   RAM_STACK		: origin = 0x000400, length = 0x000400

/*
   RAMD0            : origin = 0x00C000, length = 0x000800
   RAMD1            : origin = 0x00C800, length = 0x000800
*/
   RAM_RTOS_HEAP0	: origin = 0x00C000, length = 0x001000

/*
   RAMLS0           : origin = 0x008000, length = 0x000800
   RAMLS1           : origin = 0x008800, length = 0x000800
   RAMLS2           : origin = 0x009000, length = 0x000800
   RAMLS3           : origin = 0x009800, length = 0x000800
*/
   RAM_APP_HEAP0   	: origin = 0x008000, length = 0x002000

/*
   RAMLS4           : origin = 0x00A000, length = 0x000800
*/
   RAM_CLA_PROG		: origin = 0x00A000, length = 0x000800

/*
   RAMLS5           : origin = 0x00A800, length = 0x000800
*/
   RAM_CLA_DATA		: origin = 0x00A800, length = 0x000800

/*
   RAMLS6           : origin = 0x00B000, length = 0x000800
   RAMLS7           : origin = 0x00B800, length = 0x000800
*/

/*
   RAMGS0           : origin = 0x00D000, length = 0x001000
   RAMGS1           : origin = 0x00E000, length = 0x001000
   RAMGS2           : origin = 0x00F000, length = 0x001000
   RAMGS3           : origin = 0x010000, length = 0x001000
*/
   RAM_DATA    		: origin = 0x00D000, length = 0x004000

/*
   RAMGS4           : origin = 0x011000, length = 0x001000
   RAMGS5           : origin = 0x012000, length = 0x001000
   RAMGS6           : origin = 0x013000, length = 0x001000
   RAMGS7           : origin = 0x014000, length = 0x001000
*/
   RAM_APP_HEAP1	: origin = 0x011000, length = 0x004000

/*
   RAMGS8           : origin = 0x015000, length = 0x001000
   RAMGS9           : origin = 0x016000, length = 0x001000
   RAMGS10          : origin = 0x017000, length = 0x001000
   RAMGS11			: origin = 0x018000, length = 0x001000
   RAMGS12          : origin = 0x019000, length = 0x001000
   RAMGS13          : origin = 0x01A000, length = 0x001000
   RAMGS14          : origin = 0x01B000, length = 0x001000
   RAMGS15          : origin = 0x01C000, length = 0x001000
*/
}

/* FLASH ROM */

MEMORY {

GROUP { /* GROUP memory ranges for crc/checksum of entire flash */

   /* BEGIN is used for the "boot to Flash" bootloader mode   */
   BEGIN            : origin = 0x080000, length = 0x000002

/*
   FLASH0           : origin = 0x080002, length = 0x002000 - 0x000002
   FLASH1           : origin = 0x082000, length = 0x002000
   FLASH2           : origin = 0x084000, length = 0x002000
   FLASH3           : origin = 0x086000, length = 0x002000
*/
   FLASH_DATA		: origin = 0x080002, length = 0x008000 - 0x000002

/*
   FLASH4           : origin = 0x088000, length = 0x008000
   FLASH5           : origin = 0x090000, length = 0x008000
   FLASH6           : origin = 0x098000, length = 0x008000
   FLASH7           : origin = 0x0A0000, length = 0x008000
   FLASH8           : origin = 0x0A8000, length = 0x008000
   FLASH9           : origin = 0x0B0000, length = 0x008000
*/
   FLASH_PROG		: origin = 0x088000, length = 0x030000

/*
   FLASH10          : origin = 0x0B8000, length = 0x002000
   FLASH11          : origin = 0x0BA000, length = 0x002000
*/
   FLASH_EX			: origin = 0x0B8000, length = 0x004000

/*
   FLASH12          : origin = 0x0BC000, length = 0x002000
   FLASH13          : origin = 0x0BE000, length = 0x001FF0
   FLASH_RESERVED   : origin = 0x0BFFF0, length = 0x000010
*/
   
}  crc(_ccs_flash_checksum, algorithm=C28_CHECKSUM_16)

}

/* IPC RAM */

MEMORY {
   CMTOCPUXMSGRAM0      : origin = 0x038000, length = 0x000400
   CMTOCPUXMSGRAM1      : origin = 0x038400, length = 0x000400

   CPUXTOCMMSGRAM0      : origin = 0x039000, length = 0x000400
   CPUXTOCMMSGRAM1      : origin = 0x039400, length = 0x000400

   CPU1TOCPU2MSGRAM0    : origin = 0x03A000, length = 0x000400
   CPU1TOCPU2MSGRAM1    : origin = 0x03A400, length = 0x000400

   CPU2TOCPU1MSGRAM0    : origin = 0x03B000, length = 0x000400
   CPU2TOCPU1MSGRAM1    : origin = 0x03B400, length = 0x000400

   CANA_MSG_RAM     	: origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     	: origin = 0x04B000, length = 0x000800
}

SECTIONS {
   .reset              	: > RESET, TYPE = DSECT
   codestart           	: > BEGIN, ALIGN(4)

   .text               	: > FLASH_PROG, ALIGN(4)
   .switch             	: > FLASH_PROG, ALIGN(4)
   .cinit              	: > FLASH_PROG, ALIGN(4)
   .init_array      	: > FLASH_PROG, ALIGN(4)

   .stack              	: > RAM_STACK
   .bss             	: > RAM_DATA
   .data            	: > RAM_DATA
   .sysmem          	: > RAM_DATA

   .c28xabi.extab		: > FLASH_EX
   .c28xabi.exidx		: > FLASH_EX

   /* Initalized sections go in Flash */
   .const           	: > FLASH_DATA, ALIGN(4)

   .TI.ramfunc 			: LOAD = FLASH_PROG,
   						  LOAD_START(RamfuncsLoadStart), LOAD_SIZE(RamfuncsLoadSize), LOAD_END(RamfuncsLoadEnd),
   						  RUN = RAM_FUNC,
   						  RUN_START(RamfuncsRunStart), RUN_SIZE(RamfuncsRunSize), RUN_END(RamfuncsRunEnd),
   						  ALIGN(4)

   /* crc/checksum section configured as COPY section to avoid including in executable */
   .TI.memcrc          	: type = COPY
}

/* RTOS Heap Regions */

__RTOS_HEAP0_SIZE = 0x00001000;

SECTIONS {
	.rtos_heap0: { . += __RTOS_HEAP0_SIZE; } > RAM_RTOS_HEAP0, TYPE = NOINIT, RUN_START(__RTOS_HEAP0_START)
}

/* Application Heap Regions */

__APP_HEAP0_SIZE = 0x00002000;
__APP_HEAP1_SIZE = 0x00004000;

SECTIONS {
	.app_heap0: { . += __APP_HEAP0_SIZE; } > RAM_APP_HEAP0, TYPE = NOINIT, RUN_START(__APP_HEAP0_START)
	.app_heap1: { . += __APP_HEAP1_SIZE; } > RAM_APP_HEAP1, TYPE = NOINIT, RUN_START(__APP_HEAP1_START)
}

/* IPC Memory Regions */

__MSGRAM_SIZE = 0x00000400;

SECTIONS {
	/* CM -> CPUX */
	.cm_to_cpux_msgram0: { . += __MSGRAM_SIZE; } > CMTOCPUXMSGRAM0, TYPE = NOINIT, RUN_START(__CM_TO_CPUX_MSGRAM0_START)
	/*.cm_to_cpux_msgram1: { . += __MSGRAM_SIZE; } > CMTOCPUXMSGRAM1, TYPE = NOINIT, RUN_START(__CM_TO_CPUX_MSGRAM1_START)*/

	/* CPUX -> CM */
	.cpux_to_cm_msgram0: { . += __MSGRAM_SIZE; } > CPUXTOCMMSGRAM0, TYPE = NOINIT, RUN_START(__CPUX_TO_CM_MSGRAM0_START)
	/*.cpux_to_cm_msgram1: { . += __MSGRAM_SIZE; } > CPUXTOCMMSGRAM1, TYPE = NOINIT, RUN_START(__CPUX_TO_CM_MSGRAM1_START)*/

	/* CPU1 -> CPU2 */
	.cpu1_to_cpu2_msgram0: { . += __MSGRAM_SIZE; } > CPU1TOCPU2MSGRAM0, TYPE = NOINIT, RUN_START(__CPU1_TO_CPU2_MSGRAM0_START)
	/*.cpu1_to_cpu2_msgram1: { . += __MSGRAM_SIZE; } > CPU1TOCPU2MSGRAM1, TYPE = NOINIT, RUN_START(__CPU1_TO_CPU2_MSGRAM1_START)*/

	/* CPU2 -> CPU1 */
	.cpu2_to_cpu1_msgram0: { . += __MSGRAM_SIZE; } > CPU2TOCPU1MSGRAM0, TYPE = NOINIT, RUN_START(__CPU2_TO_CPU1_MSGRAM0_START)
	/*.cpu2_to_cpu1_msgram1: { . += __MSGRAM_SIZE; } > CPU2TOCPU1MSGRAM1, TYPE = NOINIT, RUN_START(__CPU2_TO_CPU1_MSGRAM1_START)*/

    MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2MSGRAM1, type=NOINIT
    MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1MSGRAM1, type=NOINIT
    MSGRAM_CPU_TO_CM   > CPUXTOCMMSGRAM1, type=NOINIT
    MSGRAM_CM_TO_CPU   > CMTOCPUXMSGRAM1, type=NOINIT
}