MEMORY {
	/* Reset vector (entry) */
	CMBANK0_RESETISR : ORIGIN = 0x00200000, LENGTH = 0x00000008

	/* Flash sectors */
	CMBANK0_SECTOR0  : ORIGIN = 0x00200008, LENGTH = 0x00004000 - 0x00000008
	CMBANK0_SECTOR1  : ORIGIN = 0x00204000, LENGTH = 0x00004000
	CMBANK0_SECTOR2  : ORIGIN = 0x00208000, LENGTH = 0x00004000
	CMBANK0_SECTOR3  : ORIGIN = 0x0020C000, LENGTH = 0x00004000
	CMBANK0_SECTOR4  : ORIGIN = 0x00210000, LENGTH = 0x00010000
	CMBANK0_SECTOR5  : ORIGIN = 0x00220000, LENGTH = 0x00010000
	CMBANK0_SECTOR6  : ORIGIN = 0x00230000, LENGTH = 0x00010000
	CMBANK0_SECTOR7  : ORIGIN = 0x00240000, LENGTH = 0x00010000
	CMBANK0_SECTOR8  : ORIGIN = 0x00250000, LENGTH = 0x00010000
	CMBANK0_SECTOR9  : ORIGIN = 0x00260000, LENGTH = 0x00010000
	CMBANK0_SECTOR10 : ORIGIN = 0x00270000, LENGTH = 0x00004000
	CMBANK0_SECTOR11 : ORIGIN = 0x00274000, LENGTH = 0x00004000
	CMBANK0_SECTOR12 : ORIGIN = 0x00278000, LENGTH = 0x00004000
	CMBANK0_SECTOR13 : ORIGIN = 0x0027C000, LENGTH = 0x00004000

	/* Dedicated RAM */
	C1RAM            : ORIGIN = 0x1FFFC000, LENGTH = 0x00002000
	C0RAM            : ORIGIN = 0x1FFFE000, LENGTH = 0x00002000

	/* Boot RAM */
	BOOT_RSVD        : ORIGIN = 0x20000000, LENGTH = 0x00000800

	/* Shared RAM */
    S0RAM            : ORIGIN = 0x20000800, LENGTH = 0x00004000 - 0x00000800
	S1RAM            : ORIGIN = 0x20004000, LENGTH = 0x00004000
	S2_3RAM			 : ORIGIN = 0x20008000, LENGTH = 0x00008000
//  S2RAM            : ORIGIN = 0x20008000, LENGTH = 0x00004000
//  S3RAM            : ORIGIN = 0x2000C000, LENGTH = 0x00004000
	E0RAM            : ORIGIN = 0x20010000, LENGTH = 0x00004000

	/* IPC RAM */
	CPU1TOCMMSGRAM0  : ORIGIN = 0x20080000, LENGTH = 0x00000800
	CPU1TOCMMSGRAM1  : ORIGIN = 0x20080800, LENGTH = 0x00000800

	CMTOCPU1MSGRAM0  : ORIGIN = 0x20082000, LENGTH = 0x00000800
	CMTOCPU1MSGRAM1  : ORIGIN = 0x20082800, LENGTH = 0x00000800

	CPU2TOCMMSGRAM0  : ORIGIN = 0x20084000, LENGTH = 0x00000800
	CPU2TOCMMSGRAM1  : ORIGIN = 0x20084800, LENGTH = 0x00000800

	CMTOCPU2MSGRAM0  : ORIGIN = 0x20086000, LENGTH = 0x00000800
	CMTOCPU2MSGRAM1  : ORIGIN = 0x20086800, LENGTH = 0x00000800
}

SECTIONS {
	.resetisr        : > CMBANK0_RESETISR

	.vftable         : > CMBANK0_SECTOR0 	/* Flash vtable */
	.vtable          : > C1RAM				/* RAM vtable */

	.text            : >> CMBANK0_SECTOR4 | CMBANK0_SECTOR5 | CMBANK0_SECTOR6 | CMBANK0_SECTOR7 | CMBANK0_SECTOR8 | CMBANK0_SECTOR9

	.cinit           : > CMBANK0_SECTOR0
	.pinit           : > CMBANK0_SECTOR0
	.init_array	     : > CMBANK0_SECTOR0
	.switch          : > CMBANK0_SECTOR0
	.const           : >> CMBANK0_SECTOR1 | CMBANK0_SECTOR2

	.stack           : > C1RAM
	.sysmem          : > C1RAM

	.data            : > C0RAM
	.bss             : > S0RAM

	.ARM.exidx       : > CMBANK0_SECTOR12
	.ARM.extab       : > CMBANK0_SECTOR13

    .TI.ramfunc : {} ALIGN(8),
    			     LOAD = CMBANK0_SECTOR0,
                     LOAD_START(RamfuncsLoadStart), LOAD_SIZE(RamfuncsLoadSize), LOAD_END(RamfuncsLoadEnd),
                     RUN = C0RAM,
                     RUN_START(RamfuncsRunStart), RUN_SIZE(RamfuncsRunSize), RUN_END(RamfuncsRunEnd)



}

/* RTOS Heap Regions */

__RTOS_HEAP0_SIZE = 0x00004000;

SECTIONS {
	.rtos_heap0: { . += __RTOS_HEAP0_SIZE; } > S1RAM, TYPE = NOINIT, RUN_START(__RTOS_HEAP0_START)
}

/* Application Heap Regions */

__APP_HEAP0_SIZE = 0x00004000;
__APP_HEAP1_SIZE = 0x00008000;

SECTIONS {
	.app_heap0: { . += __APP_HEAP0_SIZE; } > E0RAM, TYPE = NOINIT, RUN_START(__APP_HEAP0_START)
	.app_heap1: { . += __APP_HEAP1_SIZE; } > S2_3RAM, TYPE = NOINIT, RUN_START(__APP_HEAP1_START)
}

/* IPC Memory Regions */

__MSGRAM_SIZE = 0x00000800;

SECTIONS {
	/* CPU1 -> CM */
	.cpu1_to_cm_msgram0: { . += __MSGRAM_SIZE; } > CPU1TOCMMSGRAM0, TYPE = NOINIT, RUN_START(__CPU1_TO_CM_MSGRAM0_START)
	.cpu1_to_cm_msgram1: { . += __MSGRAM_SIZE; } > CPU1TOCMMSGRAM1, TYPE = NOINIT, RUN_START(__CPU1_TO_CM_MSGRAM1_START)

	/* CM -> CPU1 */
	.cm_to_cpu1_msgram0: { . += __MSGRAM_SIZE; } > CMTOCPU1MSGRAM0, TYPE = NOINIT, RUN_START(__CM_TO_CPU1_MSGRAM0_START)
	.cm_to_cpu1_msgram1: { . += __MSGRAM_SIZE; } > CMTOCPU1MSGRAM1, TYPE = NOINIT, RUN_START(__CM_TO_CPU1_MSGRAM1_START)

	/* CPU2 -> CM */
	.cpu2_to_cm_msgram0: { . += __MSGRAM_SIZE; } > CPU2TOCMMSGRAM0, TYPE = NOINIT, RUN_START(__CPU2_TO_CM_MSGRAM0_START)
	.cpu2_to_cm_msgram1: { . += __MSGRAM_SIZE; } > CPU2TOCMMSGRAM1, TYPE = NOINIT, RUN_START(__CPU2_TO_CM_MSGRAM1_START)

	/* CM -> CPU2 */
	.cm_to_cpu2_msgram0: { . += __MSGRAM_SIZE; } > CMTOCPU2MSGRAM0, TYPE = NOINIT, RUN_START(__CM_TO_CPU2_MSGRAM0_START)
	.cm_to_cpu2_msgram1: { . += __MSGRAM_SIZE; } > CMTOCPU2MSGRAM1, TYPE = NOINIT, RUN_START(__CM_TO_CPU2_MSGRAM1_START)
}