From b732ce16e9ae7eb6ee213915809f40b0e3082497 Mon Sep 17 00:00:00 2001 From: seklyuts Date: Tue, 21 May 2024 10:40:36 +0300 Subject: [PATCH] =?UTF-8?q?=D0=B8=D0=BD=D0=B8=D1=86=D0=B8=D0=B0=D0=BB?= =?UTF-8?q?=D0=B8=D0=B7=D0=B0=D1=86=D0=B8=D1=8F=20uart=20=D0=B8=D1=81?= =?UTF-8?q?=D0=BF=D1=80=D0=B0=D0=B2=D0=BB=D0=B5=D0=BD=D0=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Projects/epwm_test/src/frm_uart.c | 14 +++++++++----- Projects/epwm_test/src/init_perif.c | 1 + 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/Projects/epwm_test/src/frm_uart.c b/Projects/epwm_test/src/frm_uart.c index 8cbffad..72bf4af 100644 --- a/Projects/epwm_test/src/frm_uart.c +++ b/Projects/epwm_test/src/frm_uart.c @@ -58,14 +58,14 @@ void FRMUartInit(void) // EDIS; GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5); - GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL); + GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_ASYNC);//GPIO_PUSHPULL GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5); GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC); - GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0); - GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL); + GPIO_SetupPinMux(21, GPIO_MUX_CPU1, 0); + GPIO_SetupPinOptions(21, GPIO_OUTPUT, GPIO_PUSHPULL);//108 GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0); - GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL); + GPIO_SetupPinOptions(83, GPIO_OUTPUT, GPIO_PUSHPULL); EALLOW; GpioCtrlRegs.GPADIR.bit.GPIO21 = 1; @@ -77,7 +77,7 @@ void FRMUartInit(void) // GPIO_SetupPinMux(28, GPIO_MUX_CPU1, 1); // GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_PUSHPULL); // GPIO_SetupPinMux(29, GPIO_MUX_CPU1, 1); - GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC); + // GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC); // // Note: Clocks were turned on to the SCIA peripheral // in the InitSysCtrl() function @@ -123,6 +123,10 @@ void FRMUartInit(void) SciaRegs.SCILBAUD.all = 0xFF & Brr;//0x008B; SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset + + SciaRegs.SCICTL1.bit.TXENA = 1; + SciaRegs.SCICTL1.bit.RXENA = 1; + EDIS; FMSTREnableSet(); } diff --git a/Projects/epwm_test/src/init_perif.c b/Projects/epwm_test/src/init_perif.c index 3fd67e2..6557aed 100644 --- a/Projects/epwm_test/src/init_perif.c +++ b/Projects/epwm_test/src/init_perif.c @@ -32,6 +32,7 @@ void InitPerif(void) GpioSetGreen(); EALLOW; + ClkCfgRegs.CLKSEM.bit.SEM = 0x1; ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2; EDIS;