Добавлена команда сброса
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Eugene
parent
c8e8918851
commit
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@ -88,6 +88,7 @@ uint32_t InCommand,InAddr,InData;
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// IPC ISR for Flag 1
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// C28x core sends data with message queue using Flag 0
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//
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uint16_t offset;
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void FillBuff1(void)
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{
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@ -96,7 +97,7 @@ void FillBuff1(void)
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for(i=0; i < 2048; i++)
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{
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j = i & 0x7F;
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j = i+offset & 0x7F;
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a = (2*j<<8);
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b = (2*j+1);
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//Buffer = (uint16_t *)(CMTOCPU1MSGRAM0_BASE+2*i);
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@ -206,14 +207,12 @@ __interrupt void IPC1_ISR0()
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if(CounterCPU1Blocks > 0)
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{
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StartAddr += Data;
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offset += Data;
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FillBuff1();
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CounterCPU1Blocks--;
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WriteToCpu1 = 1;
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}
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// if(WriteToCpu1 != 2 )
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// {
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// putMessage_to_CPU1(0);
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// }
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else WriteToCpu1 = 0;
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//
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474
Projects/mem_test/lib/f2838x_emif.c
Normal file
474
Projects/mem_test/lib/f2838x_emif.c
Normal file
@ -0,0 +1,474 @@
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//###########################################################################
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//
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// FILE: f2838x_emif.c
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//
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// TITLE: F2838x EMIF Initialization & Support Functions.
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//
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//###########################################################################
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//
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//
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// $Copyright:
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// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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//
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// Included Files
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//
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#include "f2838x_device.h"
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#include "f2838x_examples.h"
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//
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// Emif1Initialize - This function initializes the EMIF1 to a known state.
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//
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void Emif1Initialize(void)
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{
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EALLOW;
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//
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// Perform a Module soft reset on EMIF
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//
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#ifdef CPU1
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DevCfgRegs.SOFTPRES1.all = 0x1;
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__asm (" nop");
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DevCfgRegs.SOFTPRES1.all = 0x0;
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#endif
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EDIS;
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}
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//
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// Emif2Initialize - This function initializes the EMIF2 to a known state.
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//
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void Emif2Initialize(void)
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{
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EALLOW;
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//
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// Perform a Module soft reset on EMIF
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//
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#ifdef CPU1
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DevCfgRegs.SOFTPRES1.all = 0x2;
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__asm (" nop");
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DevCfgRegs.SOFTPRES1.all = 0x0;
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#endif
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EDIS;
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}
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//
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// ASync_wait_config - Async wait configuration function
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//
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void ASync_wait_config(Uint16 inst, Uint16 wait_count, Uint16 wait_polarity)
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{
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if (inst == 0)
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{
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//
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// 7:0 Maximum Extended Wait cycles.
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//
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Emif1Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT = wait_count;
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//
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// 28 Wait Polarity for pad_wait_i[0].
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//
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Emif1Regs.ASYNC_WCCR.bit.WP0 = wait_polarity;
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}
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#ifdef CPU1
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else
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{
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//
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// 7:0 Maximum Extended Wait cycles.
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//
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Emif2Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT = wait_count;
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//
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// 28 Wait Polarity for pad_wait_i[0].
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//
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Emif2Regs.ASYNC_WCCR.bit.WP0 = wait_polarity;
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}
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#endif
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}
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//
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// ASync_cs2_config - Async CS2 Configuration
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//
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void ASync_cs2_config(Uint16 inst, Uint16 async_mem_data_width,
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Uint16 turn_around_time, Uint16 r_hold_time,
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Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold,
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Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait,
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Uint16 strobe_sel)
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{
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if (inst == 0)
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{
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//
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// 1:0 Asynchronous Memory Size.
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// 3:2 Turn Around cycles.
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// 6:4 Read Strobe Hold cycles.
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// 12:7 Read Strobe Duration cycles.
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// 16:13 Read Strobe Setup cycles.
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// 19:17 Write Strobe Hold cycles.
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// 25:20 Write Strobe Duration cycles.
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// 29:26 Write Strobe Setup cycles.
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// 30 Extend Wait mode.
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// 31 Select Strobe mode.
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//
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Emif1Regs.ASYNC_CS2_CR.bit.ASIZE = async_mem_data_width;
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Emif1Regs.ASYNC_CS2_CR.bit.TA= turn_around_time;
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Emif1Regs.ASYNC_CS2_CR.bit.R_HOLD= r_hold_time;
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Emif1Regs.ASYNC_CS2_CR.bit.R_STROBE = r_strobe_time;
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Emif1Regs.ASYNC_CS2_CR.bit.R_SETUP = r_setup;
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Emif1Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold;
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Emif1Regs.ASYNC_CS2_CR.bit.W_STROBE = w_strobe;
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Emif1Regs.ASYNC_CS2_CR.bit.W_SETUP = w_setup;
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Emif1Regs.ASYNC_CS2_CR.bit.EW = extend_wait;
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Emif1Regs.ASYNC_CS2_CR.bit.SS = strobe_sel;
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}
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#ifdef CPU1
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else
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{
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//
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// 1:0 Asynchronous Memory Size.
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// 3:2 Turn Around cycles.
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// 6:4 Read Strobe Hold cycles.
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// 12:7 Read Strobe Duration cycles.
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// 16:13 Read Strobe Setup cycles.
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// 19:17 Write Strobe Hold cycles.
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// 25:20 Write Strobe Duration cycles.
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// 29:26 Write Strobe Setup cycles.
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// 30 Extend Wait mode.
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// 31 Select Strobe mode.
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//
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Emif2Regs.ASYNC_CS2_CR.bit.ASIZE = async_mem_data_width;
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Emif2Regs.ASYNC_CS2_CR.bit.TA= turn_around_time;
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Emif2Regs.ASYNC_CS2_CR.bit.R_HOLD= r_hold_time;
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Emif2Regs.ASYNC_CS2_CR.bit.R_STROBE = r_strobe_time;
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Emif2Regs.ASYNC_CS2_CR.bit.R_SETUP = r_setup;
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Emif2Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold;
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Emif2Regs.ASYNC_CS2_CR.bit.W_STROBE = w_strobe;
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Emif2Regs.ASYNC_CS2_CR.bit.W_SETUP = w_setup;
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Emif2Regs.ASYNC_CS2_CR.bit.EW = extend_wait;
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Emif2Regs.ASYNC_CS2_CR.bit.SS = strobe_sel;
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}
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#endif
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}
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//
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// ASync_cs3_config - Async CS3 Configuration
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//
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void ASync_cs3_config(Uint16 inst, Uint16 async_mem_data_width,
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Uint16 turn_around_time, Uint16 r_hold_time,
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Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold,
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Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait,
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Uint16 strobe_sel)
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{
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//
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// 1:0 Asynchronous Memory Size.
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// 3:2 Turn Around cycles.
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// 6:4 Read Strobe Hold cycles.
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// 12:7 Read Strobe Duration cycles.
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// 16:13 Read Strobe Setup cycles.
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// 19:17 Write Strobe Hold cycles.
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// 25:20 Write Strobe Duration cycles.
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// 29:26 Write Strobe Setup cycles.
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// 30 Extend Wait mode.
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// 31 Select Strobe mode.
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//
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Emif1Regs.ASYNC_CS3_CR.bit.ASIZE = async_mem_data_width;
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Emif1Regs.ASYNC_CS3_CR.bit.TA= turn_around_time;
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Emif1Regs.ASYNC_CS3_CR.bit.R_HOLD= r_hold_time;
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Emif1Regs.ASYNC_CS3_CR.bit.R_STROBE = r_strobe_time;
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Emif1Regs.ASYNC_CS3_CR.bit.R_SETUP = r_setup;
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Emif1Regs.ASYNC_CS3_CR.bit.W_HOLD = w_hold;
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Emif1Regs.ASYNC_CS3_CR.bit.W_STROBE = w_strobe;
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Emif1Regs.ASYNC_CS3_CR.bit.W_SETUP = w_setup;
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Emif1Regs.ASYNC_CS3_CR.bit.EW = extend_wait;
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Emif1Regs.ASYNC_CS3_CR.bit.SS = strobe_sel;
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}
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//
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// ASync_cs4_config - Async CS4 Configuration
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//
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void ASync_cs4_config(Uint16 inst, Uint16 async_mem_data_width,
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Uint16 turn_around_time, Uint16 r_hold_time,
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Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold,
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Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait,
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Uint16 strobe_sel)
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{
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//
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// 1:0 Asynchronous Memory Size.
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// 3:2 Turn Around cycles.
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// 6:4 Read Strobe Hold cycles.
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// 12:7 Read Strobe Duration cycles.
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// 16:13 Read Strobe Setup cycles.
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// 19:17 Write Strobe Hold cycles.
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// 25:20 Write Strobe Duration cycles.
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// 29:26 Write Strobe Setup cycles.
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// 30 Extend Wait mode.
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// 31 Select Strobe mode.
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//
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Emif1Regs.ASYNC_CS4_CR.bit.ASIZE = async_mem_data_width;
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Emif1Regs.ASYNC_CS4_CR.bit.TA= turn_around_time;
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Emif1Regs.ASYNC_CS4_CR.bit.R_HOLD= r_hold_time;
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Emif1Regs.ASYNC_CS4_CR.bit.R_STROBE = r_strobe_time;
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Emif1Regs.ASYNC_CS4_CR.bit.R_SETUP = r_setup;
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Emif1Regs.ASYNC_CS4_CR.bit.W_HOLD = w_hold;
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Emif1Regs.ASYNC_CS4_CR.bit.W_STROBE = w_strobe;
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Emif1Regs.ASYNC_CS4_CR.bit.W_SETUP = w_setup;
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Emif1Regs.ASYNC_CS4_CR.bit.EW = extend_wait;
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Emif1Regs.ASYNC_CS4_CR.bit.SS = strobe_sel;
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}
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#ifdef CPU1
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//
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// setup_emif1_pinmux_async_16bit - function for EMIF1 GPIO pin setup
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//
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void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel)
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{
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Uint16 i;
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for (i=38; i<=52; i++)
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{
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if ((i != 42) && (i != 43))
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{
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GPIO_SetupPinMux(i,cpu_sel,2);//A0 - A12
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}
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}
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for (i=69; i<=92; i++)
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{
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if ((i != 83) && (i != 84) && (i != 85))
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{
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GPIO_SetupPinMux(i,cpu_sel,2);//D2 - D15, A13 - A19
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}
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}
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GPIO_SetupPinMux(55,cpu_sel,9);//D0
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GPIO_SetupPinMux(56,cpu_sel,9);//D1
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GPIO_SetupPinMux(26,cpu_sel,0);//RST
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GPIO_SetupPinMux(27,cpu_sel,0);//BYTE
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GpioCtrlRegs.GPADIR.bit.GPIO26 = 1;
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GpioDataRegs.GPADAT.bit.GPIO26 = 1;
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GpioCtrlRegs.GPADIR.bit.GPIO27 = 1;
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GpioDataRegs.GPADAT.bit.GPIO27 = 1;
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GPIO_SetupPinMux(29,cpu_sel,9);//CS3
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GPIO_SetupPinMux(31,cpu_sel,2);//WEN
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GPIO_SetupPinMux(36,cpu_sel,2);//WAIT
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GPIO_SetupPinMux(37,cpu_sel,2);//OEn
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//
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// setup async mode and enable pull-ups for Data pins
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//
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for (i=69; i<=92; i++)
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{
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if ((i != 84) && (i != 84) && (i != 85))
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{
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GPIO_SetupPinOptions(i,0,0x31); // GPIO_ASYNC||GPIO_PULLUP
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}
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}
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}
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//
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// setup_emif1_pinmux_async_32bit - Setup pinmux for 32bit async
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//
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void setup_emif1_pinmux_async_32bit(Uint16 cpu_sel)
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{
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Uint16 i;
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for (i=28; i<=87; i++)
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{
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if ((i != 42) && (i != 43) && (i != 84))
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{
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GPIO_SetupPinMux(i,cpu_sel,2);
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}
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}
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GPIO_SetupPinMux(88,cpu_sel,3);
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GPIO_SetupPinMux(89,cpu_sel,3);
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GPIO_SetupPinMux(90,cpu_sel,3);
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GPIO_SetupPinMux(91,cpu_sel,3);
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GPIO_SetupPinMux(92,cpu_sel,3);
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GPIO_SetupPinMux(93,cpu_sel,3);
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GPIO_SetupPinMux(94,cpu_sel,2);
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//
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// setup async mode for Data pins
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//
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for (i=53; i<=85; i++)
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{
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if (i != 84)
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{
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GPIO_SetupPinOptions(i,0,0x31);
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}
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}
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}
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//
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// setup_emif2_pinmux_async_16bit - function for EMIF2 GPIO pin setup
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//
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void setup_emif2_pinmux_async_16bit(Uint16 cpu_sel)
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{
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Uint16 i;
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for (i=96; i<=121; i++)
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{
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GPIO_SetupPinMux(i,cpu_sel,3);
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}
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for (i=53; i<=68; i++)
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{
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GPIO_SetupPinMux(i,cpu_sel,3);
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}
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//
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// setup async mode for Data pins
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//
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for (i=53; i<=68; i++)
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{
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GPIO_SetupPinOptions(i,0,0x31);
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}
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}
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//
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// setup_emif1_pinmux_sdram_16bit - Setup pinmux for 16bit SDRAM
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//
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void setup_emif1_pinmux_sdram_16bit(Uint16 cpu_sel)
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{
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int i;
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for (i=29; i<=52; i++)
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{
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if ((i != 42) && (i != 43))
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{
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GPIO_SetupPinMux(i,cpu_sel,2);
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}
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}
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for (i=69; i<=85; i++)
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{
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if (i != 84)
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{
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GPIO_SetupPinMux(i,cpu_sel,2);
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}
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}
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for(i=86; i<=93; i++)
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{
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GPIO_SetupPinMux(i,cpu_sel,3);
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}
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//
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//configure Data pins for Async mode
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//
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for (i = 69; i <= 85; i++)
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{
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if (i != 84)
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{
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GPIO_SetupPinOptions(i,0,0x31);
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}
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}
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GPIO_SetupPinOptions(88,0,0x31);
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GPIO_SetupPinOptions(89,0,0x31);
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GPIO_SetupPinOptions(90,0,0x31);
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GPIO_SetupPinOptions(91,0,0x31);
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}
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//
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// setup_emif2_pinmux_sdram_16bit - Setup pinmux for 16bit SDRAM
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//
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void setup_emif2_pinmux_sdram_16bit(Uint16 cpu_sel)
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{
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int i;
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for (i=53; i<=68; i++)
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{
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GPIO_SetupPinMux(i,cpu_sel,3);
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}
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for (i=96; i<=121; i++)
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{
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GPIO_SetupPinMux(i,cpu_sel,3);
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}
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|
||||
//
|
||||
//configure Data pins for Async mode
|
||||
//
|
||||
for (i = 53; i <= 68; i++)
|
||||
{
|
||||
GPIO_SetupPinOptions(i,0,0x31);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// setup_emif1_pinmux_sdram_32bit - Setup pinmux for 32bit SDRAM
|
||||
//
|
||||
void setup_emif1_pinmux_sdram_32bit(Uint16 cpu_sel)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=28; i<=85; i++)
|
||||
{
|
||||
if ((i != 42) && (i != 43) && (i != 84))
|
||||
{
|
||||
GPIO_SetupPinMux(i,cpu_sel,2);
|
||||
}
|
||||
}
|
||||
|
||||
for(i=86; i<=93; i++)
|
||||
{
|
||||
GPIO_SetupPinMux(i,cpu_sel,3);
|
||||
}
|
||||
|
||||
GPIO_SetupPinMux(94,cpu_sel,2);
|
||||
|
||||
//
|
||||
//configure Data pins for Async mode
|
||||
//
|
||||
for (i = 53; i <= 85; i++)
|
||||
{
|
||||
if (i != 84)
|
||||
{
|
||||
GPIO_SetupPinOptions(i,0,0x31);
|
||||
}
|
||||
}
|
||||
|
||||
GPIO_SetupPinOptions(88,0,0x31);
|
||||
GPIO_SetupPinOptions(89,0,0x31);
|
||||
GPIO_SetupPinOptions(90,0,0x31);
|
||||
GPIO_SetupPinOptions(91,0,0x31);
|
||||
}
|
||||
|
||||
#endif // CPU1
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
@ -9,6 +9,8 @@
|
||||
#include "ZD24C02A.h"
|
||||
#include "Arr.h"
|
||||
|
||||
//Нуждается в проверке и отладке, так как с этой микросхемой не удалось добиться стабильной работы, она то работает, то нет
|
||||
|
||||
volatile uint16_t SlaveAdr = I2C_SLAVE_ADDRESS;
|
||||
uint16_t BufferZD24C02A[17];
|
||||
|
||||
@ -21,7 +23,7 @@ uint16_t ZD24C02A_write_8(uint16_t Addr, uint16_t * Array, uint16_t quant)//
|
||||
uint16_t ZD24C02A_read_8(uint16_t Addr, uint16_t * Array, uint16_t quant)
|
||||
{
|
||||
|
||||
// if(I2CWrite(SlaveAdr, Addr, 0, false, Array)) return 1;
|
||||
if(I2CWrite(SlaveAdr, Addr, 0, false, Array)) return 1;
|
||||
if(I2CRead(SlaveAdr, quant, true, Array)) return 1;
|
||||
else return 0;
|
||||
}
|
||||
|
||||
@ -5,6 +5,378 @@
|
||||
* Author: seklyuts
|
||||
*/
|
||||
|
||||
#include "f28x_project.h"
|
||||
|
||||
#define TEST_PASS 0xABCDABCD
|
||||
#define TEST_FAIL 0xDEADDEAD
|
||||
#define ASRAM_CS2_START_ADDR 0x100000
|
||||
#define ASRAM_CS2_SIZE 0x8000
|
||||
#define EMIF1 0
|
||||
#define EMIF2 1
|
||||
#define MEM_D_WIDTH 1 // 16Bit Memory Interface
|
||||
#define TURN_AROUND_TIME 0 // Turn Around time of 2 Emif Clock
|
||||
#define RD_SETUP_TIME 0 // Read Setup time of 1 Emif Clock
|
||||
#define RD_STROBE_TIME 3 // Read Strobe time of 4 Emif Clock
|
||||
#define RD_HOLD_TIME 0 // Read Hold time of 1 Emif Clock
|
||||
#define WR_SETUP_TIME 0 // Write Hold time of 1 Emif Clock
|
||||
#define WR_STROBE_TIME 0 // Write Setup time of 1 Emif Clock
|
||||
#define WR_HOLD_TIME 0 // Write Hold time of 1 Emif Clock
|
||||
#define EXTEND_WAIT 0 // Disable Extended Wait
|
||||
#define STROBE_SEL 0 // Disable Strobe Mode.
|
||||
#define WAIT_POLAR_INV 0
|
||||
#define WAIT_COUNT 0
|
||||
|
||||
//
|
||||
// Globals
|
||||
//
|
||||
Uint16 ErrCount = 0;
|
||||
Uint32 TEST_STATUS;
|
||||
int i;
|
||||
|
||||
|
||||
//
|
||||
// Function Prototypes
|
||||
//
|
||||
extern void setup_emif1_pinmux_async_16bit(Uint16);
|
||||
|
||||
//
|
||||
// mem_read_write - This function performs simple read/write word accesses
|
||||
// to memory.
|
||||
//
|
||||
char
|
||||
mem_read_write(Uint32 start_addr, Uint32 mem_size)
|
||||
{
|
||||
unsigned long mem_rds;
|
||||
unsigned long mem_wds;
|
||||
long *XMEM_ps;
|
||||
unsigned int i;
|
||||
|
||||
//
|
||||
//Write data
|
||||
//
|
||||
XMEM_ps = (long *)start_addr;
|
||||
|
||||
//
|
||||
//Fill memory
|
||||
//
|
||||
mem_wds = 0x01234567;
|
||||
for (i=0; i < mem_size; i++)
|
||||
{
|
||||
*XMEM_ps++ = mem_wds;
|
||||
mem_wds += 0x11111111;
|
||||
}
|
||||
|
||||
//
|
||||
//Verify memory
|
||||
//
|
||||
mem_wds = 0x01234567;
|
||||
XMEM_ps = (long *)start_addr;
|
||||
for (i=0; i < mem_size; i++)
|
||||
{
|
||||
mem_rds = *XMEM_ps;
|
||||
if( mem_rds != mem_wds)
|
||||
{
|
||||
return(1);
|
||||
}
|
||||
XMEM_ps++;
|
||||
mem_wds += 0x11111111;
|
||||
}
|
||||
return(0);
|
||||
}
|
||||
|
||||
//
|
||||
// mem_data_walk - This function performs a walking 0 & 1 on data lines for
|
||||
// SRAM RD & WR
|
||||
//
|
||||
char
|
||||
mem_data_walk(Uint32 start_addr, Uint32 mem_size)
|
||||
{
|
||||
unsigned long sram_rd;
|
||||
unsigned long sram_wd;
|
||||
unsigned long i;
|
||||
int k;
|
||||
int m;
|
||||
unsigned long *XM_p;
|
||||
unsigned long *XMEM_p;
|
||||
|
||||
XM_p = (unsigned long *)start_addr;
|
||||
|
||||
for (i=0; i < mem_size; i=i+64)
|
||||
{
|
||||
for (m=0; m < 2; m++)
|
||||
{
|
||||
//
|
||||
//Write loop
|
||||
//
|
||||
XMEM_p = XM_p;
|
||||
sram_wd = 0x01;
|
||||
for (k=0; k < 32; k++)
|
||||
{
|
||||
if(m==0)
|
||||
{
|
||||
*XMEM_p++ = sram_wd;
|
||||
}
|
||||
else
|
||||
{
|
||||
*XMEM_p++ = ~sram_wd;
|
||||
}
|
||||
sram_wd = sram_wd<<1;
|
||||
}
|
||||
|
||||
//
|
||||
//Read loop
|
||||
//
|
||||
XMEM_p = XM_p;
|
||||
sram_wd = 0x01;
|
||||
for (k=0; k < 32; k++)
|
||||
{
|
||||
sram_rd = *XMEM_p;
|
||||
if(m==1)
|
||||
{
|
||||
sram_rd = ~sram_rd;
|
||||
}
|
||||
if(sram_rd != sram_wd)
|
||||
{
|
||||
return(1);
|
||||
}
|
||||
XMEM_p++;
|
||||
sram_wd=sram_wd<<1;
|
||||
}
|
||||
}
|
||||
XM_p = XMEM_p;
|
||||
}
|
||||
return(0);
|
||||
}
|
||||
|
||||
//
|
||||
// mem_addr_walk - This function performs a toggle on each address bit.
|
||||
//
|
||||
char
|
||||
mem_addr_walk(Uint32 start_addr, Uint32 addr_size)
|
||||
{
|
||||
unsigned long sram_rd;
|
||||
unsigned long sram_wd;
|
||||
unsigned int k;
|
||||
unsigned long xshift;
|
||||
unsigned long *XM_p;
|
||||
unsigned long *XMEM_p;
|
||||
|
||||
XM_p = (unsigned long *)start_addr;
|
||||
|
||||
//
|
||||
//Write loop
|
||||
//
|
||||
xshift = 0x00000001;
|
||||
sram_wd = 0x00;
|
||||
for (k=0; k < addr_size; k++)
|
||||
{
|
||||
XMEM_p = (unsigned long *)(start_addr + xshift);
|
||||
*XMEM_p = sram_wd++;
|
||||
xshift = xshift<<1;
|
||||
}
|
||||
|
||||
//
|
||||
//Read loop
|
||||
//
|
||||
XMEM_p = XM_p;
|
||||
xshift = 0x00000001;
|
||||
sram_wd = 0x00;
|
||||
for (k=0; k < addr_size; k++)
|
||||
{
|
||||
XMEM_p = (unsigned long *)(start_addr + xshift);
|
||||
sram_rd = *XMEM_p;
|
||||
if(sram_rd != sram_wd)
|
||||
{
|
||||
return(1);
|
||||
}
|
||||
|
||||
xshift = xshift<<1;
|
||||
sram_wd++;
|
||||
}
|
||||
return(0);
|
||||
}
|
||||
|
||||
//
|
||||
// mem_data_size - This function performs different data type
|
||||
// (HALFWORD/WORD) access.
|
||||
//
|
||||
char
|
||||
mem_data_size(Uint32 start_addr, Uint32 size_to_check)
|
||||
{
|
||||
unsigned short mem_rds;
|
||||
unsigned long mem_rdl;
|
||||
unsigned short mem_wds;
|
||||
unsigned long mem_wdl;
|
||||
int i;
|
||||
|
||||
short *XMEM_ps;
|
||||
long *XMEM_pl;
|
||||
|
||||
//
|
||||
//Write data short
|
||||
//
|
||||
XMEM_ps = (short *)start_addr;
|
||||
mem_wds = 0x0605;
|
||||
|
||||
for (i=0; i < 2; i++)
|
||||
{
|
||||
*XMEM_ps++ = mem_wds;
|
||||
mem_wds += 0x0202;
|
||||
}
|
||||
|
||||
//
|
||||
//Write data long
|
||||
//
|
||||
XMEM_pl = (long *)XMEM_ps;
|
||||
mem_wdl = 0x0C0B0A09;
|
||||
for (i=0; i < 2; i++)
|
||||
{
|
||||
*XMEM_pl++ = mem_wdl;
|
||||
mem_wdl += 0x04040404;
|
||||
}
|
||||
|
||||
//
|
||||
//Read data short
|
||||
//
|
||||
XMEM_ps = (short *)start_addr;
|
||||
mem_wds = 0x0605;
|
||||
for (i=0; i < 6; i++)
|
||||
{
|
||||
mem_rds = *XMEM_ps;
|
||||
if( mem_rds != mem_wds)
|
||||
{
|
||||
return(1);
|
||||
}
|
||||
XMEM_ps++;
|
||||
mem_wds += 0x0202;
|
||||
}
|
||||
|
||||
//
|
||||
//Read data long
|
||||
//
|
||||
XMEM_pl = (long *)start_addr;
|
||||
mem_wdl = 0x08070605;
|
||||
for (i=0; i < 3; i++)
|
||||
{
|
||||
mem_rdl = *XMEM_pl;
|
||||
if(mem_rdl != mem_wdl)
|
||||
{
|
||||
return(1);
|
||||
}
|
||||
XMEM_pl++;
|
||||
mem_wdl += 0x04040404;
|
||||
}
|
||||
return(0);
|
||||
}
|
||||
|
||||
void emif_init(void)
|
||||
{
|
||||
char ErrCount_local;
|
||||
//
|
||||
//Configure to run EMIF1 on full Rate (EMIF1CLK = CPU1SYSCLK)
|
||||
//
|
||||
EALLOW;
|
||||
ClkCfgRegs.PERCLKDIVSEL.bit.EMIF1CLKDIV = 0x0;
|
||||
EDIS;
|
||||
|
||||
EALLOW;
|
||||
//
|
||||
// Grab EMIF1 For CPU1
|
||||
//
|
||||
Emif1ConfigRegs.EMIF1MSEL.all = 0x93A5CE71;
|
||||
if(Emif1ConfigRegs.EMIF1MSEL.all != 0x1)
|
||||
{
|
||||
ErrCount++;
|
||||
}
|
||||
|
||||
//
|
||||
//Disable Access Protection (CPU_FETCH/CPU_WR/DMA_WR)
|
||||
//
|
||||
Emif1ConfigRegs.EMIF1ACCPROT0.all = 0x0;
|
||||
if(Emif1ConfigRegs.EMIF1ACCPROT0.all != 0x0)
|
||||
{
|
||||
ErrCount++;
|
||||
}
|
||||
|
||||
//
|
||||
// Commit the configuration related to protection. Till this bit remains set
|
||||
// content of EMIF1ACCPROT0 register can't be changed.
|
||||
//
|
||||
Emif1ConfigRegs.EMIF1COMMIT.all = 0x1;
|
||||
if(Emif1ConfigRegs.EMIF1COMMIT.all != 0x1)
|
||||
{
|
||||
ErrCount++;
|
||||
}
|
||||
|
||||
//
|
||||
// Lock the configuration so that EMIF1COMMIT register can't be
|
||||
// changed any more.
|
||||
//
|
||||
Emif1ConfigRegs.EMIF1LOCK.all = 0x1;
|
||||
if(Emif1ConfigRegs.EMIF1LOCK.all != 1)
|
||||
{
|
||||
ErrCount++;
|
||||
}
|
||||
|
||||
EDIS;
|
||||
|
||||
//
|
||||
//Configure GPIO pins for EMIF1
|
||||
//
|
||||
setup_emif1_pinmux_async_16bit(0);
|
||||
|
||||
//
|
||||
//Configure the access timing for CS2 space
|
||||
//
|
||||
Emif1Regs.ASYNC_CS3_CR.all = (EMIF_ASYNC_ASIZE_16 | // 16Bit Memory
|
||||
// Interface
|
||||
EMIF_ASYNC_TA_1 | // Turn Around time
|
||||
// of 2 Emif Clock
|
||||
EMIF_ASYNC_RHOLD_1 | // Read Hold time
|
||||
// of 1 Emif Clock
|
||||
EMIF_ASYNC_RSTROBE_4 | // Read Strobe time
|
||||
// of 4 Emif Clock
|
||||
EMIF_ASYNC_RSETUP_1 | // Read Setup time
|
||||
// of 1 Emif Clock
|
||||
EMIF_ASYNC_WHOLD_1 | // Write Hold time
|
||||
// of 1 Emif Clock
|
||||
EMIF_ASYNC_WSTROBE_1 | // Write Strobe time
|
||||
// of 1 Emif Clock
|
||||
EMIF_ASYNC_WSETUP_1 | // Write Setup time
|
||||
// of 1 Emif Clock
|
||||
EMIF_ASYNC_EW_DISABLE | // Extended Wait
|
||||
// Disable.
|
||||
EMIF_ASYNC_SS_DISABLE // Strobe Select Mode
|
||||
// Disable.
|
||||
);
|
||||
|
||||
//
|
||||
//Check basic RD/WR access to CS2 space
|
||||
//
|
||||
ErrCount_local = mem_read_write(ASRAM_CS2_START_ADDR, ASRAM_CS2_SIZE);
|
||||
ErrCount = ErrCount + ErrCount_local;
|
||||
|
||||
//
|
||||
//Address walk checks (Tested for Memory with address width of 16bit)
|
||||
//
|
||||
ErrCount_local = mem_addr_walk(ASRAM_CS2_START_ADDR, 16);
|
||||
ErrCount = ErrCount + ErrCount_local;
|
||||
|
||||
//
|
||||
//Data walk checks
|
||||
//
|
||||
ErrCount_local = mem_data_walk(ASRAM_CS2_START_ADDR, ASRAM_CS2_SIZE);
|
||||
ErrCount = ErrCount + ErrCount_local;
|
||||
|
||||
//
|
||||
//Data size checks
|
||||
//
|
||||
ErrCount_local = mem_data_size(ASRAM_CS2_START_ADDR, 4);
|
||||
ErrCount = ErrCount + ErrCount_local;
|
||||
|
||||
if (ErrCount == 0x0)
|
||||
{
|
||||
TEST_STATUS = TEST_PASS;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
#define SRC_EMIF_INIT_H_
|
||||
|
||||
|
||||
|
||||
void emif_init(void);
|
||||
|
||||
|
||||
#endif /* SRC_EMIF_INIT_H_ */
|
||||
|
||||
@ -49,6 +49,7 @@ typedef enum
|
||||
READ,
|
||||
WRITE,
|
||||
VERIFY,
|
||||
RESET_NOW,
|
||||
END = 0xFF
|
||||
} Command_Type_t;
|
||||
|
||||
@ -378,6 +379,9 @@ void ipc_run(void)
|
||||
{
|
||||
ReadFromCm = 2;
|
||||
IPC_readCommand(IPC_CPU1_L_CM_R, 0, 0, &InCommand, &InAddr, &InData );
|
||||
|
||||
if((InCommand >> 16) == RESET_NOW) CpuSysRegs.SIMRESET.bit.XRSn = 1;
|
||||
|
||||
switch(InCommand & 0xFFFF)
|
||||
{
|
||||
case INT_FLASH:
|
||||
|
||||
@ -81,8 +81,5 @@ void InitPerif(void)
|
||||
#endif
|
||||
ipc_init();
|
||||
Internal_flash_Init();
|
||||
|
||||
|
||||
// Bl25cm1a_en();
|
||||
|
||||
emif_init();
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user