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Рабочая версия для CPU2

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This commit is contained in:
seklyuts 2024-05-21 09:03:51 +03:00
parent e8bc1dfada
commit 3a383cfde6
19 changed files with 178 additions and 174 deletions
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1
Projects/epwm_test_biss_c_cpu1/epwm_test.c
View File

@ -24,6 +24,7 @@ void main(void)
{
InitPerif();
for(;;)
{
// asm (" NOP");

24
Projects/epwm_test_biss_c_cpu1/lib/f2838x_epwm.c
View File

@ -113,6 +113,7 @@ void InitEPwm2Gpio(void)
//
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO2 (EPWM2A)
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Disable pull-up on GPIO3 (EPWM2B)
// GpioCtrlRegs.GPEPUD.bit.GPIO147 = 1; // Disable pull-up on GPIO147 (EPWM2A)
// GpioCtrlRegs.GPEPUD.bit.GPIO148 = 1; // Disable pull-up on GPIO148 (EPWM2B)
@ -126,6 +127,9 @@ void InitEPwm2Gpio(void)
// GpioCtrlRegs.GPEMUX2.bit.GPIO147 = 1; // Configure GPIO147 as EPWM2A
// GpioCtrlRegs.GPEMUX2.bit.GPIO148 = 1; // Configure GPIO148 as EPWM2B
GpioCtrlRegs.GPACSEL1.bit.GPIO2 = 2;//to cpu2
GpioCtrlRegs.GPACSEL1.bit.GPIO3 = 2;
EDIS;
}
@ -155,6 +159,8 @@ void InitEPwm3Gpio(void)
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B
// GpioCtrlRegs.GPEMUX2.bit.GPIO149 = 1; // Configure GPIO149 as EPWM3A
// GpioCtrlRegs.GPEMUX2.bit.GPIO150 = 1; // Configure GPIO150 as EPWM3B
GpioCtrlRegs.GPACSEL1.bit.GPIO4 = 2;//to cpu2
GpioCtrlRegs.GPACSEL1.bit.GPIO5 = 2;
EDIS;
}
@ -185,6 +191,8 @@ void InitEPwm4Gpio(void)
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B
// GpioCtrlRegs.GPEMUX2.bit.GPIO151 = 1; // Configure GPIO151 as EPWM4A
// GpioCtrlRegs.GPEMUX2.bit.GPIO152 = 1; // Configure GPIO152 as EPWM4B
GpioCtrlRegs.GPACSEL1.bit.GPIO6 = 2;//to cpu2
GpioCtrlRegs.GPACSEL1.bit.GPIO7 = 2;
EDIS;
}
@ -215,6 +223,8 @@ void InitEPwm5Gpio(void)
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B
// GpioCtrlRegs.GPEMUX2.bit.GPIO153 = 1; // Configure GPIO153 as EPWM5A
// GpioCtrlRegs.GPEMUX2.bit.GPIO154 = 1; // Configure GPIO0154 as EPWM5B
GpioCtrlRegs.GPACSEL2.bit.GPIO8 = 2;//to cpu2
GpioCtrlRegs.GPACSEL2.bit.GPIO9 = 2;
EDIS;
}
@ -245,6 +255,8 @@ void InitEPwm6Gpio(void)
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B
// GpioCtrlRegs.GPEMUX2.bit.GPIO155 = 1; // Configure GPIO155 as EPWM6A
// GpioCtrlRegs.GPEMUX2.bit.GPIO156 = 1; // Configure GPIO156 as EPWM6B
GpioCtrlRegs.GPACSEL2.bit.GPIO10 = 2;//to cpu2
GpioCtrlRegs.GPACSEL2.bit.GPIO11 = 2;
EDIS;
}
@ -275,6 +287,8 @@ void InitEPwm7Gpio(void)
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EPWM7B
// GpioCtrlRegs.GPEMUX2.bit.GPIO157 = 1; // Configure GPIO157 as EPWM7A
// GpioCtrlRegs.GPEMUX2.bit.GPIO158 = 1; // Configure GPIO158 as EPWM7B
GpioCtrlRegs.GPACSEL2.bit.GPIO12 = 2;//to cpu2
GpioCtrlRegs.GPACSEL2.bit.GPIO13 = 2;
EDIS;
}
@ -305,6 +319,8 @@ void InitEPwm8Gpio(void)
// GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as EPWM8B
// GpioCtrlRegs.GPEMUX2.bit.GPIO159 = 1; // Configure GPIO159 as EPWM8A
// GpioCtrlRegs.GPFMUX1.bit.GPIO160 = 1; // Configure GPIO160 as EPWM8B
GpioCtrlRegs.GPACSEL2.bit.GPIO14 = 2;//to cpu2
EDIS;
}
@ -346,6 +362,8 @@ void InitEPwm9Gpio(void)
//
// GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPAMUX for EPWM9A
// GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPAMUX for EPWM9B
GpioCtrlRegs.GPBCSEL4.bit.GPIO61 = 2;//to cpu2
GpioCtrlRegs.GPBCSEL4.bit.GPIO62 = 2;
EDIS;
}
@ -387,6 +405,8 @@ void InitEPwm10Gpio(void)
//
// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPAMUX for EPWM10A
// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPAMUX for EPWM10B
GpioCtrlRegs.GPBCSEL4.bit.GPIO63 = 2;//to cpu2
GpioCtrlRegs.GPCCSEL1.bit.GPIO64 = 2;
EDIS;
}
@ -429,6 +449,9 @@ void InitEPwm11Gpio(void)
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPAMUX for EPWM11A
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPAMUX for EPWM11B
GpioCtrlRegs.GPACSEL3.bit.GPIO20 = 2;//to cpu2
GpioCtrlRegs.GPACSEL3.bit.GPIO21 = 2;
EDIS;
}
@ -470,6 +493,7 @@ void InitEPwm12Gpio(void)
// GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPAMUX for EPWM12A
// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPAMUX for EPWM12B
EDIS;
}

13
Projects/epwm_test_biss_c_cpu1/lib/f2838x_sysctrl.c
View File

@ -212,17 +212,8 @@ void InitSysCtrl(void)
// documentation on steps to reconfigure the controlCARD from 20MHz to
// 25MHz.
//
//ňóň âűëĺň ďî ęâŕđöó
//<EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
GpioDataRegs.GPADAT.bit.GPIO6 = 1;
GpioDataRegs.GPADAT.bit.GPIO6 = 1;
GpioDataRegs.GPADAT.bit.GPIO6 = 1;
GpioDataRegs.GPADAT.bit.GPIO7 = 0;
GpioDataRegs.GPADAT.bit.GPIO7 = 0;
GpioDataRegs.GPADAT.bit.GPIO7 = 0;
GpioDataRegs.GPADAT.bit.GPIO10 = 1;
GpioDataRegs.GPADAT.bit.GPIO10 = 1;
GpioDataRegs.GPADAT.bit.GPIO10 = 1;
ESTOP0;
while(1);
}
@ -278,7 +269,7 @@ void InitSysCtrl(void)
//
// Turn on all peripherals
//
InitPeripheralClocks();
// InitPeripheralClocks();
}
//

35
Projects/epwm_test_biss_c_cpu1/src/Peripherals/gpio_init.c
View File

@ -1,7 +1,7 @@
/*
* gpio_init.c
*
* Created on: 4 ñåíò. 2023 ã.
* Created on: 4 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
* Author: seklyuts
*/
#include "f28x_project.h"
@ -13,16 +13,19 @@ void GpioDiodInit(void)
GpioCtrlRegs.GPAGMUX1.bit.GPIO6 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO6 = 1;
GpioDataRegs.GPADAT.bit.GPIO6 = 0;
GpioCtrlRegs.GPACSEL1.bit.GPIO6 = 2;
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0;
GpioCtrlRegs.GPAGMUX1.bit.GPIO7 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO7 = 1;
GpioDataRegs.GPADAT.bit.GPIO7 = 0;
GpioCtrlRegs.GPACSEL1.bit.GPIO7 = 2;
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0;
GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO10 = 1;
GpioDataRegs.GPADAT.bit.GPIO10 = 0;
GpioCtrlRegs.GPACSEL2.bit.GPIO10 = 2;
EDIS;
}
@ -70,7 +73,7 @@ void GpioInit(void)
{
EALLOW;
GpioCtrlRegs.GPCMUX2.bit.GPIO95 = 0; // ðåëå ñèëîâîå
GpioCtrlRegs.GPCMUX2.bit.GPIO95 = 0; // <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
GpioCtrlRegs.GPCGMUX2.bit.GPIO95 = 0;
GpioCtrlRegs.GPCDIR.bit.GPIO95 = 1;
GpioDataRegs.GPCDAT.bit.GPIO95 = 1;
@ -85,22 +88,18 @@ void GpioInit(void)
GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1;
GpioDataRegs.GPBDAT.bit.GPIO57 = 1;//BISS-C_PWR_EN
GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 0;
GpioCtrlRegs.GPCGMUX2.bit.GPIO83 = 0;
GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
#ifdef RS485
GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
#else
GpioDataRegs.GPCDAT.bit.GPIO83 = 1;
#endif
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0;
GpioCtrlRegs.GPAGMUX2.bit.GPIO21 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
#ifdef RS485
GpioDataRegs.GPADAT.bit.GPIO21 = 1;
#else
GpioDataRegs.GPADAT.bit.GPIO21 = 0;
#endif
// GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 0;
// GpioCtrlRegs.GPCGMUX2.bit.GPIO83 = 0;
// GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
//
// GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
//
// GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0;
// GpioCtrlRegs.GPAGMUX2.bit.GPIO21 = 0;
// GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
//
// GpioDataRegs.GPADAT.bit.GPIO21 = 1;
GpioCtrlRegs.GPDMUX1.bit.GPIO103 = 0;
GpioCtrlRegs.GPDGMUX1.bit.GPIO103 = 0;
GpioCtrlRegs.GPDDIR.bit.GPIO103 = 1;

32
Projects/epwm_test_biss_c_cpu1/src/Peripherals/sdfm.c
View File

@ -123,44 +123,44 @@ void SdfmGpioInit(void)
EALLOW;
GPIO_SetupPinOptions(16, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(16,GPIO_MUX_CPU1,7); //SDFM-1 Channel 1 Data Input (Iu)a
GPIO_SetupPinMux(16,GPIO_MUX_CPU2,7); //SDFM-1 Channel 1 Data Input (Iu)a
GPIO_SetupPinOptions(17, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(17,GPIO_MUX_CPU1,7); //SDFM-1 Channel 1 Clock Input
GPIO_SetupPinMux(17,GPIO_MUX_CPU2,7); //SDFM-1 Channel 1 Clock Input
GPIO_SetupPinOptions(22, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(22,GPIO_MUX_CPU1,7); //SDFM-1 Channel 4 Data Input (Iv)b
GPIO_SetupPinMux(22,GPIO_MUX_CPU2,7); //SDFM-1 Channel 4 Data Input (Iv)b
GPIO_SetupPinOptions(23, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(23,GPIO_MUX_CPU1,7); //SDFM-1 Channel 4 Clock Input
GPIO_SetupPinMux(23,GPIO_MUX_CPU2,7); //SDFM-1 Channel 4 Clock Input
GPIO_SetupPinOptions(24, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(24,GPIO_MUX_CPU1,7); //SDFM-2 Channel 1 Data Input (Iw)c
GPIO_SetupPinMux(24,GPIO_MUX_CPU2,7); //SDFM-2 Channel 1 Data Input (Iw)c
GPIO_SetupPinOptions(25, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(25,GPIO_MUX_CPU1,7); //SDFM-2 Channel 1 Clock Input
GPIO_SetupPinMux(25,GPIO_MUX_CPU2,7); //SDFM-2 Channel 1 Clock Input
GPIO_SetupPinOptions(58, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(58,GPIO_MUX_CPU1,7); //SDFM-2 Channel 2 Data Input (Udc)
GPIO_SetupPinMux(58,GPIO_MUX_CPU2,7); //SDFM-2 Channel 2 Data Input (Udc)
GPIO_SetupPinOptions(59, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(59,GPIO_MUX_CPU1,7); //SDFM-2 Channel 2 Clock Input
GPIO_SetupPinMux(59,GPIO_MUX_CPU2,7); //SDFM-2 Channel 2 Clock Input
GPIO_SetupPinOptions(60, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(60,GPIO_MUX_CPU1,7); //SDFM-2 Channel 3 Data Input (brake)
GPIO_SetupPinMux(60,GPIO_MUX_CPU2,7); //SDFM-2 Channel 3 Data Input (brake)
GPIO_SetupPinOptions(61, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(61,GPIO_MUX_CPU1,7); //SDFM-2 Channel 3 Clock Input
GPIO_SetupPinMux(61,GPIO_MUX_CPU2,7); //SDFM-2 Channel 3 Clock Input
GPIO_SetupPinOptions(62, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(62,GPIO_MUX_CPU1,7); //SDFM-2 Channel 4 Data Input (sin)
GPIO_SetupPinMux(62,GPIO_MUX_CPU2,7); //SDFM-2 Channel 4 Data Input (sin)
GPIO_SetupPinOptions(63, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(63,GPIO_MUX_CPU1,7); //SDFM-2 Channel 4 Clock Input
GPIO_SetupPinMux(63,GPIO_MUX_CPU2,7); //SDFM-2 Channel 4 Clock Input
GPIO_SetupPinOptions(65, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(65,GPIO_MUX_CPU1,13); //SDFM-1 Channel 2 Data Input (cos)
GPIO_SetupPinMux(65,GPIO_MUX_CPU2,13); //SDFM-1 Channel 2 Data Input (cos)
GPIO_SetupPinOptions(66, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(66,GPIO_MUX_CPU1,13); //SDFM-1 Channel 2 Clock Input
GPIO_SetupPinMux(66,GPIO_MUX_CPU2,13); //SDFM-1 Channel 2 Clock Input
GPIO_SetupPinOptions(67, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(67,GPIO_MUX_CPU1,13); //SDFM-1 Channel 3 Data Input (ref)
GPIO_SetupPinMux(67,GPIO_MUX_CPU2,13); //SDFM-1 Channel 3 Data Input (ref)
GPIO_SetupPinOptions(68, GPIO_INPUT, GPIO_ASYNC);
GPIO_SetupPinMux(68,GPIO_MUX_CPU1,13); //SDFM-1 Channel 3 Clock Input
GPIO_SetupPinMux(68,GPIO_MUX_CPU2,13); //SDFM-1 Channel 3 Clock Input
EDIS;
}

31
Projects/epwm_test_biss_c_cpu1/src/frm_uart.c
View File

@ -33,31 +33,32 @@ void FMSTREnableSet(void)
void FRMGPIOInit(void)
{
GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5);
GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL);
GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5);
GPIO_SetupPinMux(85, GPIO_MUX_CPU2, 5);
GPIO_SetupPinOptions(85, GPIO_INPUT, (GPIO_ASYNC | GPIO_PULLUP));
GPIO_SetupPinMux(84, GPIO_MUX_CPU2, 5);
GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC);
GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL);
GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0);
GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL);
GPIO_SetupPinMux(21, GPIO_MUX_CPU2, 0);
GPIO_SetupPinOptions(21, GPIO_OUTPUT, GPIO_PUSHPULL);
GPIO_SetupPinMux(83, GPIO_MUX_CPU2, 0);
GPIO_SetupPinOptions(83, GPIO_OUTPUT, GPIO_PUSHPULL);
EALLOW;
GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
GpioDataRegs.GPADAT.bit.GPIO21 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
EDIS;
// EALLOW;
// GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
// GpioDataRegs.GPADAT.bit.GPIO21 = 1;
// GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
// EDIS;
GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
// GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
}
void FRMUartInit(void)
{
FMSTR_Init();
EALLOW;
CpuSysRegs.PCLKCR7.bit.SCI_A = 1;
EDIS;
//
// Note: Clocks were turned on to the SCIA peripheral

5
Projects/epwm_test_biss_c_cpu1/src/frmmstr_run.c
View File

@ -17,6 +17,7 @@ volatile uint16_t Rele=0;
void frmmstr_run(void)
{
static uint16_t diod = 0;
if(FMSTRIsEnable()) {
if(counter < 100) counter++;
else
@ -28,8 +29,8 @@ static uint16_t diod = 0;
counter1=0;
counter2++;
diod++;
if(diod > 7) diod = 0;
Gpio_rainbow(diod);
//if(diod > 7) diod = 0;
//Gpio_rainbow(diod);
//FMSTR_SCI_PUTCHAR(0xA5);
}
}

37
Projects/epwm_test_biss_c_cpu1/src/init_perif.c
View File

@ -26,6 +26,7 @@
#define TO_CPU1 0
#define TO_CPU2 1
//стр 395
#define CONNECT_SD1(x) EALLOW; DevCfgRegs.CPUSEL4.bit.SD1 = x; EDIS
#define CONNECT_SD2(x) EALLOW; DevCfgRegs.CPUSEL4.bit.SD2 = x; EDIS
@ -54,16 +55,15 @@
void InitPerif(void)
{
GpioDiodInit();
GpioSetGreen();
EALLOW;
// ClkCfgRegs.CLKSEM.bit.SEM = 0xA5A50002;
ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2;
EDIS;
InitSysCtrl();
GpioSetBlue();
@ -94,10 +94,19 @@ void InitPerif(void)
// The shell ISR routines are found in f2838x_defaultisr.c.
// This function is found in f2838x_pievect.c.
//
InitPieVectTable();
// InitPieVectTable();
GpioInit();
GpioDiodInit();
//GpioSetGreen();
//GpioSetBlue();
SdfmGpioInit();
SdfmTypeInit();
// SdfmInitEnable();
@ -120,6 +129,8 @@ void InitPerif(void)
FRMGPIOInit();
// FRMUartInit();
// ConfigureADC();
CONNECT_SD1(TO_CPU2);
CONNECT_SD2(TO_CPU2);
CONNECT_PWM1(TO_CPU2);
@ -131,12 +142,24 @@ void InitPerif(void)
CONNECT_PWM11(TO_CPU2);
CONNECT_PWM12(TO_CPU2);
CONNECT_SCIA(TO_CPU2);
// ConfigureADC();
//
// Enable global Interrupts and higher priority real-time debug events:
//
Cpu1toCpu2IpcRegs.CPU1TOCPU2IPCBOOTMODE = 0x5A00C803; //str 716
Cpu1toCpu2IpcRegs.CPU1TOCPU2IPCSET.bit.IPC0 = 1;
EALLOW;
DevCfgRegs.CPU2RESCTL.all = 0xA5A50000;
EDIS;
while(DevCfgRegs.RSTSTAT.bit.CPU2RES == 0);
// SysCtl_controlCPU2Reset(SYSCTL_CORE_DEACTIVE);
// while(SysCtl_isCPU2Reset() == 0x1U);
//Device_bootCPU2(BOOTMODE_BOOT_TO_FLASH_SECTOR0);
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM

2
Projects/epwm_test_biss_c_cpu2/.cproject
View File

@ -414,7 +414,7 @@
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="lib/f2838x_epwm.c|src/Peripherals/gpio_init.c|2838x_RAM_combined_lnk_cpu1.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
<entry excluding="lib/f2838x_epwm.c|2838x_RAM_combined_lnk_cpu1.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>

18
Projects/epwm_test_biss_c_cpu2/.settings/org.eclipse.core.resources.prefs Normal file
View File

@ -0,0 +1,18 @@
eclipse.preferences.version=1
encoding//CPU2_FLASH/Freemaster/subdir_rules.mk=UTF-8
encoding//CPU2_FLASH/Freemaster/subdir_vars.mk=UTF-8
encoding//CPU2_FLASH/lib/subdir_rules.mk=UTF-8
encoding//CPU2_FLASH/lib/subdir_vars.mk=UTF-8
encoding//CPU2_FLASH/makefile=UTF-8
encoding//CPU2_FLASH/objects.mk=UTF-8
encoding//CPU2_FLASH/sources.mk=UTF-8
encoding//CPU2_FLASH/src/CLB/subdir_rules.mk=UTF-8
encoding//CPU2_FLASH/src/CLB/subdir_vars.mk=UTF-8
encoding//CPU2_FLASH/src/ExternalEEPROM/subdir_rules.mk=UTF-8
encoding//CPU2_FLASH/src/ExternalEEPROM/subdir_vars.mk=UTF-8
encoding//CPU2_FLASH/src/Peripherals/subdir_rules.mk=UTF-8
encoding//CPU2_FLASH/src/Peripherals/subdir_vars.mk=UTF-8
encoding//CPU2_FLASH/src/subdir_rules.mk=UTF-8
encoding//CPU2_FLASH/src/subdir_vars.mk=UTF-8
encoding//CPU2_FLASH/subdir_rules.mk=UTF-8
encoding//CPU2_FLASH/subdir_vars.mk=UTF-8

12
Projects/epwm_test_biss_c_cpu2/2838x_FLASH_lnk_cpu2.cmd
View File

@ -74,7 +74,7 @@ SECTIONS
#if defined(__TI_EABI__)
.init_array : > FLASH1, ALIGN(8)
.bss : > RAMGS0 // instead of RAMLS5
.bss : > RAMLS5 // instead of RAMLS5
.bss:output : > RAMLS3
.bss:cio : > RAMLS5
.data : > RAMLS5
@ -99,11 +99,11 @@ SECTIONS
MSGRAM_CM_TO_CPU : > CMTOCPURAM, type=NOINIT
/* The following section definition are for SDFM examples */
Filter_RegsFile : > RAMGS0
Filter1_RegsFile : > RAMGS1, fill=0x1111
Filter2_RegsFile : > RAMGS2, fill=0x2222
Filter3_RegsFile : > RAMGS3, fill=0x3333
Filter4_RegsFile : > RAMGS4, fill=0x4444
Filter_RegsFile : > RAMGS10
Filter1_RegsFile : > RAMLS1, fill=0x1111
Filter2_RegsFile : > RAMLS2, fill=0x2222
Filter3_RegsFile : > RAMLS3, fill=0x3333
Filter4_RegsFile : > RAMLS4, fill=0x4444
Difference_RegsFile : >RAMGS5, fill=0x3333
#if defined(__TI_EABI__)

2
Projects/epwm_test_biss_c_cpu2/Freemaster/PE_freemaster_cfg.h
View File

@ -43,7 +43,7 @@
/* Recorder support */
#define FMSTR_USE_RECORDER 1 /* Recorder support enabled */
#define FMSTR_REC_BUFF_SIZE 2048 /* Recorder buffer size */
#define FMSTR_REC_BUFF_SIZE 1024 /* Recorder buffer size */
#define FMSTR_USE_FASTREC 0 /* Fast recorder support disabled */
#define FMSTR_REC_OWNBUFF 0 /* User-allocated rec. buffer is not used */
#define FMSTR_REC_FARBUFF 0 /* Buffer is not putted in "fardata" section */

2
Projects/epwm_test_biss_c_cpu2/Freemaster/PE_freemaster_serial.c
View File

@ -365,7 +365,7 @@ static void FMSTR_Rx(FMSTR_BCHR nRxChar)
return;
}
}
/* we have got a common character preceeded by the SOB - */
/* this is the command code! */
if(pcm_wFlags.flg.bRxLastCharSOB)

BIN
Projects/epwm_test_biss_c_cpu2/Start_rfm.pmp
View File

Binary file not shown.

4
Projects/epwm_test_biss_c_cpu2/epwm_test.c
View File

@ -23,13 +23,15 @@
void main(void)
{
InitPerif();
//SciaRegs.SCITXBUF.all = 0xA5;
for(;;)
{
// asm (" NOP");
frmmstr_run();
// Gpio_rainbow(diod);
// AdcRun();
BissClkgenRun();
// BissClkgenRun();
}
}

62
Projects/epwm_test_biss_c_cpu2/src/Peripherals/gpio_init.c
View File

@ -1,31 +1,12 @@
/*
* gpio_init.c
*
* Created on: 4 ñåíò. 2023 ã.
* Created on: 4 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
* Author: seklyuts
*/
#include "f28x_project.h"
void GpioDiodInit(void)
{
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0;
GpioCtrlRegs.GPAGMUX1.bit.GPIO6 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO6 = 1;
GpioDataRegs.GPADAT.bit.GPIO6 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0;
GpioCtrlRegs.GPAGMUX1.bit.GPIO7 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO7 = 1;
GpioDataRegs.GPADAT.bit.GPIO7 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0;
GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO10 = 1;
GpioDataRegs.GPADAT.bit.GPIO10 = 0;
EDIS;
}
void GpioSetGreen(void)
{
@ -66,48 +47,7 @@ void GpioSetOrange(void)
GpioDataRegs.GPADAT.bit.GPIO10 = 1;
}
void GpioInit(void)
{
EALLOW;
GpioCtrlRegs.GPCMUX2.bit.GPIO95 = 0; // ğåëå ñèëîâîå
GpioCtrlRegs.GPCGMUX2.bit.GPIO95 = 0;
GpioCtrlRegs.GPCDIR.bit.GPIO95 = 1;
GpioDataRegs.GPCDAT.bit.GPIO95 = 1;
GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 0;//FaultPWM
GpioCtrlRegs.GPCGMUX1.bit.GPIO64 = 0;
GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0;
GpioDataRegs.GPCDAT.bit.GPIO64 = 0;
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 0;
GpioCtrlRegs.GPBGMUX2.bit.GPIO57 = 0;
GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1;
GpioDataRegs.GPBDAT.bit.GPIO57 = 1;//BISS-C_PWR_EN
GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 0;
GpioCtrlRegs.GPCGMUX2.bit.GPIO83 = 0;
GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
#ifdef RS485
GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
#else
GpioDataRegs.GPCDAT.bit.GPIO83 = 1;
#endif
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0;
GpioCtrlRegs.GPAGMUX2.bit.GPIO21 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
#ifdef RS485
GpioDataRegs.GPADAT.bit.GPIO21 = 1;
#else
GpioDataRegs.GPADAT.bit.GPIO21 = 0;
#endif
GpioCtrlRegs.GPDMUX1.bit.GPIO103 = 0;
GpioCtrlRegs.GPDGMUX1.bit.GPIO103 = 0;
GpioCtrlRegs.GPDDIR.bit.GPIO103 = 1;
GpioDataRegs.GPDDAT.bit.GPIO103 = 0; //BISS-C_PWR_12V/5V
EDIS;
}
//void Gpio20out(uint16_t out_bit)
//{

31
Projects/epwm_test_biss_c_cpu2/src/frm_uart.c
View File

@ -35,24 +35,16 @@ void FMSTREnableSet(void)
void FRMUartInit(void)
{
FMSTR_Init();
EALLOW;
CpuSysRegs.PCLKCR7.bit.SCI_A = 1;
EDIS;
// GPIO_SetupPinMux(85, GPIO_MUX_CPU1, 5);
// GPIO_SetupPinOptions(85, GPIO_INPUT, GPIO_PUSHPULL);
// GPIO_SetupPinMux(84, GPIO_MUX_CPU1, 5);
// GPIO_SetupPinOptions(84, GPIO_OUTPUT, GPIO_ASYNC);
//
// GPIO_SetupPinMux(108, GPIO_MUX_CPU1, 0);
// GPIO_SetupPinOptions(108, GPIO_INPUT, GPIO_PUSHPULL);
// GPIO_SetupPinMux(83, GPIO_MUX_CPU1, 0);
// GPIO_SetupPinOptions(83, GPIO_INPUT, GPIO_PUSHPULL);
//
// EALLOW;
// GpioCtrlRegs.GPADIR.bit.GPIO21 = 1;
// GpioDataRegs.GPADAT.bit.GPIO21 = 1;
// GpioCtrlRegs.GPCDIR.bit.GPIO83 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
// EDIS;
EALLOW;
GpioDataRegs.GPADAT.bit.GPIO21 = 1;
GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
EDIS;
//
// GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC);
//
@ -75,6 +67,10 @@ void FRMUartInit(void)
SciaRegs.SCILBAUD.all = 0xFF & Brr;//0x008B;
SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
SciaRegs.SCICTL1.bit.RXENA = 1;
SciaRegs.SCICTL1.bit.TXENA = 1;
EDIS;
FMSTREnableSet();
}
@ -126,6 +122,11 @@ FMSTR_SCISR FMSTR_SCI_RDCLRSR(void)
SciSR = FMSTR_SCISR_RDRF;
}
// if (SciaRegs.SCIRXST.bit.RXWAKE) // UART receive buffer full
// {
// SciSR = FMSTR_SCISR_RDRF;
// }
if(SciaRegs.SCICTL2.bit.TXEMPTY) // UART is transmitting data or transmit register full (UART busy)
{
SciSR |= FMSTR_SCISR_TDRE;

20
Projects/epwm_test_biss_c_cpu2/src/frmmstr_run.c
View File

@ -13,10 +13,26 @@ volatile uint16_t counter=0 ;
volatile uint16_t counter1=0 ;
volatile uint16_t counter2=0 ;
volatile uint16_t Rele=0;
volatile uint16_t testMode = 0;
void frmmstr_run(void)
{
static uint16_t diod = 0;
FMSTREnableSet();
if(SciaRegs.SCIRXST.bit.RXERROR)
{
EALLOW;
SciaRegs.SCICTL1.bit.SWRESET = 0;
EDIS;
}
else
{
EALLOW;
SciaRegs.SCICTL1.bit.SWRESET = 1;
EDIS;
}
if(FMSTRIsEnable()) {
if(counter < 100) counter++;
else
@ -29,8 +45,8 @@ static uint16_t diod = 0;
counter2++;
diod++;
if(diod > 7) diod = 0;
//Gpio_rainbow(diod);
//FMSTR_SCI_PUTCHAR(0xA5);
Gpio_rainbow(diod);
if(testMode) FMSTR_SCI_PUTCHAR(0xA5);
}
}
FMSTR_Poll();

21
Projects/epwm_test_biss_c_cpu2/src/init_perif.c
View File

@ -27,17 +27,13 @@
void InitPerif(void)
{
// GpioDiodInit();
//
// GpioSetGreen();
//
// EALLOW;
// ClkCfgRegs.CLKSEM.all = 0xA5A50001;
// ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2;
// EDIS;
//
// InitSysCtrl();
// GpioSetBlue();
InitSysCtrl();
// Clear all interrupts and initialize PIE vector table:
@ -69,29 +65,20 @@ void InitPerif(void)
//
InitPieVectTable();
// GpioInit();
SdfmInitEnable();
SdfmInit();
// SdfmGpioInit();
SdfmInitInterruptEn();
PWMInitEnable();
PWMAllInit();
// PWMGpioInit();
PWMInitInterruptEn();
vectorInitCurrLoop();
// SpiCInit();
// SpiCGpioInit();
// BissGpioInit();
// BissInit();
FRMUartInit();
// ConfigureADC();
//
// Enable global Interrupts and higher priority real-time debug events:
//