seklyuts/MotorControlModuleSDFM_TMS320F28388D
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This commit is contained in:
Eugene 2023-12-08 08:44:59 +03:00
parent 2bd2955417
commit 307a25457e
10 changed files with 208 additions and 130 deletions
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2
Projects/mem_test/.cproject
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@ -450,7 +450,7 @@
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="src/Peripherals/pwm_interrupts.c|src/Peripherals/pwm_init.c|Freemaster|src/frmmstr_run.c|src/timer_base.c|src/Peripherals/i2c_init.c|src/ExternalEEPROM/ZD24C02A.c|src/ExternalEEPROM/GD25Q16ETIGR.c|src/ExternalEEPROM/ExtEEPROM.c|src/ExternalEEPROM/BL25CM1A.c|src/Peripherals/spi_init.c|src/Peripherals/gpio_init.c|src/frm_uart.c|lib/f2838x_epwm.c|device/driverlib|2838x_RAM_combined_lnk_cpu1.cmd|2838x_FLASH_lnk_cpu1.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
<entry excluding="src/Peripherals/pwm_interrupts.c|src/Peripherals/pwm_init.c|Freemaster|src/frmmstr_run.c|src/timer_base.c|src/Peripherals/i2c_init.c|src/ExternalEEPROM/ZD24C02A.c|src/ExternalEEPROM/GD25Q16ETIGR.c|src/ExternalEEPROM/BL25CM1A.c|src/Peripherals/spi_init.c|src/Peripherals/gpio_init.c|src/frm_uart.c|lib/f2838x_epwm.c|device/driverlib|2838x_RAM_combined_lnk_cpu1.cmd|2838x_FLASH_lnk_cpu1.cmd" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>

2
Projects/mem_test/.launches/mem_test.launch
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@ -29,7 +29,7 @@
<mapEntry key="org.eclipse.cdt.debug.ui.memory.memorybrowser.MemoryBrowser.PIN_CLONE_VIEW_3@#$Texas Instruments XDS100v2 USB Debug Probe_0/Cortex_M4_0" value="@@0x20082000"/>
<mapEntry key="org.eclipse.cdt.debug.ui.memory.memorybrowser.MemoryBrowser.PIN_CLONE_VIEW_4@#$Texas Instruments XDS100v2 USB Debug Probe_0/C28xx_CPU1" value="Data@@0x38000"/>
<mapEntry key="org.eclipse.cdt.debug.ui.memory.memorybrowser.MemoryBrowser.PIN_CLONE_VIEW_5@#$Texas Instruments XDS100v2 USB Debug Probe_0/C28xx_CPU1" value="Data@@0x39000"/>
<mapEntry key="org.eclipse.cdt.debug.ui.memory.memorybrowser.MemoryBrowser@#$Texas Instruments XDS100v2 USB Debug Probe_0/C28xx_CPU1" value="Data@@0x20080000"/>
<mapEntry key="org.eclipse.cdt.debug.ui.memory.memorybrowser.MemoryBrowser@#$Texas Instruments XDS100v2 USB Debug Probe_0/C28xx_CPU1" value="Data@@0x100000"/>
<mapEntry key="org.eclipse.cdt.debug.ui.memory.memorybrowser.MemoryBrowser@#$Texas Instruments XDS100v2 USB Debug Probe_0/C28xx_CPU2" value="Data@@0x82000"/>
<mapEntry key="org.eclipse.cdt.debug.ui.memory.memorybrowser.MemoryBrowser@#$Texas Instruments XDS100v2 USB Debug Probe_0/Cortex_M4_0" value="@@0x20080000"/>
</mapAttribute>

94
Projects/mem_test/2838x_RAM_combined_lnk_cpu1.cm_ Normal file
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@ -0,0 +1,94 @@
MEMORY
{
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002 // CPU1 IPC SERVER
BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x0001B1, length = 0x00024F // CPU1 IPC SERVER
RAMM1 : origin = 0x000400, length = 0x0003F8 // CPU1 IPC SERVER
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMD0 : origin = 0x00C000, length = 0x000800 // CPU1 IPC SERVER
RAMD1 : origin = 0x00C800, length = 0x000800 // CPU1 IPC SERVER
RAMLS0 : origin = 0x008000, length = 0x000800 // CPU1 IPC SERVER
RAMLS1 : origin = 0x008800, length = 0x000800 // CPU1 IPC SERVER
RAMLS2 : origin = 0x009000, length = 0x000800 // CPU1 IPC SERVER
RAMLS3 : origin = 0x009800, length = 0x000800 // CPU1 IPC SERVER
RAMLS4 : origin = 0x00A000, length = 0x000800 // CPU1 IPC SERVER
RAMLS5 : origin = 0x00A800, length = 0x000800 // CPU1 IPC BOOTLOADER
RAMLS6 : origin = 0x00B000, length = 0x000800 // CPU1 IPC BOOTLOADER
RAMLS7 : origin = 0x00B800, length = 0x000800 // CPU1 IPC BOOTLOADER
RAMGS0 : origin = 0x00D000, length = 0x001000 // CPU1 IPC BOOTLOADER
RAMGS1 : origin = 0x00E000, length = 0x001000 // CPU1 IPC SERVER
RAMGS2 : origin = 0x00F000, length = 0x001000 // CPU2 IPC SERVER
RAMGS3 : origin = 0x010000, length = 0x001000 // CPU2 IPC SERVER
RAMGS4 : origin = 0x011000, length = 0x001000 // CPU1 IPC SERVER
RAMGS5 : origin = 0x012000, length = 0x001000 // CM IPC BOOTLOADER
USB_CM_FIRMWARE : origin = 0x013000, length = 0x00A000 // CM USB SERVER
// RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
/* Flash sectors */
FLASH0 : origin = 0x080000, length = 0x002000 /* on-chip Flash */
FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASH13 : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
CPUTOCMRAM : origin = 0x039000, length = 0x000800
CMTOCPURAM : origin = 0x038000, length = 0x000800
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
}
SECTIONS
{
codestart : > BEGIN
.text : >> RAMM0 | RAMM1 | RAMD0 | RAMD1 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 //text - Code
.cinit : > RAMGS4 //cinit - Init values fos global vars
.switch : > RAMLS3 //switch - tables for switch statements
.reset : > RAMLS3, TYPE = DSECT /* not used, */
.stack : > RAMLS4 //stack - Local vars
#if defined(__TI_EABI__)
.bss : >> RAMLS4 | RAMGS1
.bss:output : > RAMLS4
.init_array : > RAMLS4
.const : > RAMLS4
.data : > RAMLS4
.sysmem : > RAMLS4
#else
.pinit : > RAMLS4 //pinit - tables for global constructors (C++)
.ebss : > RAMLS4 //ebss - Global vars
.econst : > RAMLS4
.esysmem : > RAMLS4
#endif
MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
MSGRAM_CPU_TO_CM > CPUTOCMRAM, type=NOINIT
MSGRAM_CM_TO_CPU > CMTOCPURAM, type=NOINIT
/* The following section definition are for SDFM examples */
.TI.ramfunc : {} > RAMGS1
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

95
Projects/mem_test/2838x_RAM_combined_lnk_cpu2.cm_ Normal file
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@ -0,0 +1,95 @@
MEMORY
{
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x000000, length = 0x000002 // CPU1 IPC SERVER
BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x0001B1, length = 0x00024F // CPU1 IPC SERVER
RAMM1 : origin = 0x000400, length = 0x0003F8 // CPU1 IPC SERVER
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMD0 : origin = 0x00C000, length = 0x000800 // CPU1 IPC SERVER
RAMD1 : origin = 0x00C800, length = 0x000800 // CPU1 IPC SERVER
RAMLS0 : origin = 0x008000, length = 0x000800 // CPU1 IPC SERVER
RAMLS1 : origin = 0x008800, length = 0x000800 // CPU1 IPC SERVER
RAMLS2 : origin = 0x009000, length = 0x000800 // CPU1 IPC SERVER
RAMLS3 : origin = 0x009800, length = 0x000800 // CPU1 IPC SERVER
RAMLS4 : origin = 0x00A000, length = 0x000800 // CPU1 IPC SERVER
RAMLS5 : origin = 0x00A800, length = 0x000800 // CPU1 IPC BOOTLOADER
RAMLS6 : origin = 0x00B000, length = 0x000800 // CPU1 IPC BOOTLOADER
RAMLS7 : origin = 0x00B800, length = 0x000800 // CPU1 IPC BOOTLOADER
RAMGS0 : origin = 0x00D000, length = 0x001000 // CPU1 IPC BOOTLOADER
RAMGS1 : origin = 0x00E000, length = 0x001000 // CPU1 IPC SERVER
RAMGS2 : origin = 0x00F000, length = 0x001000 // CPU2 IPC SERVER
RAMGS3 : origin = 0x010000, length = 0x001000 // CPU2 IPC SERVER
RAMGS4 : origin = 0x011000, length = 0x001000 // CPU1 IPC SERVER
RAMGS5 : origin = 0x012000, length = 0x001000 // CM IPC BOOTLOADER
USB_CM_FIRMWARE : origin = 0x013000, length = 0x00A000 // CM USB SERVER
// RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
/* Flash sectors */
FLASH0 : origin = 0x080000, length = 0x002000 /* on-chip Flash */
FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASH13 : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
CPU1TOCPU2RAM0 : origin = 0x03A000, length = 0x000008
CPU1TOCPU2RAM1 : origin = 0x03A400, length = 0x000400 // CPU2 IPC SERVER
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
CPUTOCMRAM0 : origin = 0x039000, length = 0x000400
CPUTOCMRAM1 : origin = 0x039400, length = 0x000400, fill=0x0000
CMTOCPURAM : origin = 0x038000, length = 0x000800
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
}
SECTIONS
{
codestart : > CPU1TOCPU2RAM1
.text : >> RAMGS2 | RAMGS3
.cinit : > RAMGS3
.switch : > RAMGS3
.reset : > RAMGS3, TYPE = DSECT
.stack : > RAMD0, TYPE = NOLOAD
#if defined(__TI_EABI__)
.bss : > RAMGS3
.bss:output : > RAMGS3
.init_array : > RAMGS3
.const : > RAMGS3
.data : > RAMGS3
.sysmem : > RAMGS3
#else
.pinit : > RAMGS3
.ebss : > RAMGS3
.econst : > RAMGS3
.esysmem : > RAMGS3
#endif
MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM0, type=NOINIT
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
MSGRAM_CPU_TO_CM > CPUTOCMRAM0, type=NOINIT
MSGRAM_CM_TO_CPU > CMTOCPURAM, type=NOINIT
.TI.ramfunc : {} > RAMGS3
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/

2
Projects/mem_test/lib/f2838x_emif.c
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@ -284,7 +284,7 @@ void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel)
GpioDataRegs.GPADAT.bit.GPIO26 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO27 = 1;
GpioDataRegs.GPADAT.bit.GPIO27 = 0;//Byte mode
GpioDataRegs.GPADAT.bit.GPIO27 = 1;//word mode
GPIO_SetupPinMux(29,cpu_sel,9);//CS3
GPIO_SetupPinMux(31,cpu_sel,2);//WEN

2
Projects/mem_test/lib/f2838x_sysctrl.c
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@ -286,6 +286,8 @@ void InitSysCtrl(void)
ClkCfgRegs.CMCLKCTL.bit.CMDIVSRCSEL = 0; // 0 : AuxPLL is the source for the CM clock divider.
EDIS;
///ClkCfgRegs.LOSPCP.bit.LSPCLKDIV
#ifndef _FLASH
//
// Call Device_cal function when run using debugger

3
Projects/mem_test/mem_test.c
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@ -17,7 +17,6 @@
//#include "f28x_project.h"
#ifdef CPU1
#include "frmmstr_run.h"
#include "ExtEEPROM.h"
#endif
#include "init_perif.h"
@ -31,7 +30,7 @@ void main(void)
asm (" NOP");
ipc_run();
#ifdef CPU1
// ExtEEPROM_run();
// frmmstr_run();
#endif
}

100
Projects/mem_test/src/ExternalEEPROM/ExtEEPROM.c
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@ -1,100 +0,0 @@
/*
* ExtEEPROM.c
*
* Created on: 14 ñåíò. 2023 ã.
* Author: seklyuts
*/
#include "f28x_project.h"
#include "i2c_init.h"
#include "BL25CM1A.h"
#include "GD25Q16ETIGR.h"
#include "ZD24C02A.h"
#define MAX_BUFFER_SIZE 0x10
uint16_t sendNowI2C = 0, sendNowSPIGD25 = 0, sendNowSPIBL25 = 0;
uint16_t TestADR = 0;
uint16_t NByte = 16;
uint16_t WriteI2C = 0;
uint16_t Adr = 0x0;
uint32_t SpiAdr = 0;
char ArrayForTests[MAX_BUFFER_SIZE+1] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0x51, 0x52};
char ArrayMax[256];
void ExtEEPROM_run(void)
{
if(sendNowI2C==1)
{
if(WriteI2C)
{
ArrayForTests[0] = Adr;
//ZD24C02A_write(NByte, ArrayForTests);
}
else
{
ArrayMax[0] = Adr;
//ZD24C02A_read(NByte, ArrayMax);
}
sendNowI2C = 0;
}
else if(sendNowI2C==2)
{
I2CWriteRes();
sendNowI2C = 0;
}
switch(sendNowSPIGD25)
{
case 1:
GD25Q16ETIGR_en();
sendNowSPIGD25 = 0;
break;
case 2:
//GD25Q16ETIGR_write();
sendNowSPIGD25 = 0;
break;
case 3:
GD25Q16ETIGR_en();
//GD25Q16ETIGR_write_data(SpiAdr);
sendNowSPIGD25 = 0;
break;
case 4:
//GD25Q16ETIGR_read_data(SpiAdr);
sendNowSPIGD25 = 0;
break;
case 5:
GD25Q16ETIGR_ReadManufacturerDeviceID();
sendNowSPIGD25 = 0;
break;
}
switch(sendNowSPIBL25)
{
case 1:
Bl25cm1a_en();
sendNowSPIBL25 = 0;
break;
case 2:
//Bl25cm1a_write();
sendNowSPIBL25 = 0;
break;
case 3:
Bl25cm1a_en();
//Bl25cm1a_write_data(SpiAdr);
sendNowSPIBL25 = 0;
break;
case 4:
//Bl25cm1a_read_data(SpiAdr);
sendNowSPIBL25 = 0;
break;
case 5:
//Bl25cm1a_en();
sendNowSPIBL25 = 0;
break;
}
}

13
Projects/mem_test/src/ExternalEEPROM/ExtEEPROM.h
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@ -1,13 +0,0 @@
/*
* ExtEEPROM.h
*
* Created on: 14 ñåíò. 2023 ã.
* Author: seklyuts
*/
#ifndef SRC_EXTEEPROM_H_
#define SRC_EXTEEPROM_H_
void ExtEEPROM_run(void);
#endif /* SRC_EXTEEPROM_H_ */

25
Projects/mem_test/src/Peripherals/emif_init.c
View File

@ -10,8 +10,8 @@
#define TEST_PASS 0xABCDABCD
#define TEST_FAIL 0xDEADDEAD
#define ASRAM_CS2_START_ADDR 0x100000
#define ASRAM_CS2_SIZE 0x100000
#define STEP 0x100
#define ASRAM_CS2_SIZE 0x10
#define EMIF1 0
#define EMIF2 1
#define MEM_D_WIDTH 1 // 16Bit Memory Interface
@ -44,10 +44,11 @@ extern void setup_emif1_pinmux_async_16bit(Uint16);
// mem_read_write - This function performs simple read/write word accesses
// to memory.
//
uint16_t Arr1[256], Arr2[256];
uint16_t Arr1[ASRAM_CS2_SIZE], Arr2[ASRAM_CS2_SIZE];
char
mem_read_write(Uint32 start_addr, Uint32 mem_size, Uint16 step)
mem_read_write(Uint32 start_addr, Uint32 mem_size)
{
unsigned long mem_rds;
unsigned long mem_wds;
@ -63,11 +64,11 @@ mem_read_write(Uint32 start_addr, Uint32 mem_size, Uint16 step)
//Fill memory
//
mem_wds = 0x01234567;
for (i=0; i < mem_size; i+=step)
for (i=0; i < mem_size; i++)
{
*XMEM_ps = mem_wds;
if(i < 256) Arr1[i] = mem_wds & 0x1FF;
XMEM_ps += step;
if(i < ASRAM_CS2_SIZE) Arr1[i] = mem_wds & 0x0FF;
XMEM_ps ++;
mem_wds += 0x11111111;
}
@ -76,14 +77,14 @@ mem_read_write(Uint32 start_addr, Uint32 mem_size, Uint16 step)
//
mem_wds = 0x01234567;
XMEM_ps = (long *)start_addr;
for (i=0; i < mem_size; i+=step)
for (i=0; i < mem_size; i++)
{
mem_rds = *XMEM_ps;
if( (mem_rds & 0x1FF) != (mem_wds & 0x1FF) )
if( (mem_rds & 0xFF) != (mem_wds & 0xFF) )
{
if(i < 256) Arr2[i] = mem_rds & 0x1FF;
if(i < ASRAM_CS2_SIZE) Arr2[i] = mem_rds & 0xFF;
}
XMEM_ps+= step;
XMEM_ps++;
mem_wds += 0x11111111;
}
return(0);
@ -360,7 +361,7 @@ void emif_init(void)
//
//Check basic RD/WR access to CS2 space
//
ErrCount_local = mem_read_write(ASRAM_CS2_START_ADDR, ASRAM_CS2_SIZE, STEP);
ErrCount_local = mem_read_write(ASRAM_CS2_START_ADDR, ASRAM_CS2_SIZE);
ErrCount = ErrCount + ErrCount_local;
//