MotorControlModuleSDFM_TMS320F28388D/Projects/epwm_test/src/Peripherals/spi_init.c

/*
 * spi_init.c
 *
 *  Created on: 5 <EFBFBD><EFBFBD><EFBFBD><EFBFBD>. 2023 <EFBFBD>.
 *      Author: seklyuts
 */

#include "f28x_project.h"

#define     SPI_PROGRAM_CS_GPAMUX1          GpioCtrlRegs.GPDMUX1.bit.GPIO98
#define     SPI_PROGRAM_CS_GPAGMUX1         GpioCtrlRegs.GPDGMUX1.bit.GPIO98
#define     SPI_PROGRAM_CS_GPADIR           GpioCtrlRegs.GPDDIR.bit.GPIO98
#define     SPI_PROGRAM_CS_GPADAT           GpioDataRegs.GPDDAT.bit.GPIO98


__interrupt void spia_rx_isr(void);
__interrupt void spia_tx_isr(void);

__interrupt void spib_rx_isr(void);
__interrupt void spib_tx_isr(void);



void SpiAInit(void)
{
    //
    // Initialize SPI-A
    //
    //
    // Initialize SPI FIFO registers
    //
    CpuSysRegs.PCLKCR8.bit.SPI_A = 1;

    SpiaRegs.SPIFFTX.all = 0xE040;
    SpiaRegs.SPIFFRX.all = 0x2044;
    SpiaRegs.SPIFFCT.all = 0x0;

    //
    // Initialize core SPI registers
    //
    //
    // Set reset low before configuration changes
    // Clock polarity (0 == rising, 1 == falling)
    // 16-bit character
    // Enable loop-back
    //
    SpiaRegs.SPICCR.bit.SPISWRESET = 0;
    SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;
    SpiaRegs.SPICCR.bit.SPICHAR = (8 - 1);
    SpiaRegs.SPICCR.bit.SPILBK = 0;

    //
    // Enable master (0 == slave, 1 == master)
    // Enable transmission (Talk)
    // Clock phase (0 == normal, 1 == delayed)
    // SPI interrupts are disabled
    //
    SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
    SpiaRegs.SPICTL.bit.TALK = 1;
    SpiaRegs.SPICTL.bit.CLK_PHASE = 1;
    SpiaRegs.SPICTL.bit.SPIINTENA = 0;

    PieCtrlRegs.PIEIER6.bit.INTx1 = 0;
    PieCtrlRegs.PIEIER6.bit.INTx2 = 0;

    PieVectTable.SPIA_RX_INT = &spia_rx_isr;
    PieVectTable.SPIA_TX_INT = &spia_tx_isr;
    //
    // Set the baud rate using a 1 MHz SPICLK
    // BRR = (LSPCLK / SPICLK) - 1
    //
    SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = ((50000000 / 1000000) - 1);

    // Set FREE bit
    // Halting on a breakpoint will not halt the SPI
    //
    SpiaRegs.SPIPRI.bit.FREE = 1;

    //
    // Release the SPI from reset
    //
    SpiaRegs.SPICCR.bit.SPISWRESET = 1;
}

void SpiAGpioInit(void)
{
       EALLOW;

    //
    // Enable internal pull-up for the selected pins
    //
    // Pull-ups can be enabled or disabled by the user.
    // This will enable the pullups for the specified pins.
    //
    GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0;  // Enable pull-up on (SPISIMOA)
    GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0;  // Enable pull-up on (SPISOMIA)
    GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0;  // Enable pull-up on (SPICLKA)
    GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0;  // Enable pull-up on (SPISTEA)

    //
    // Set qualification for selected pins to asynch only
    //
    // This will select asynch (no qualification) for the selected pins.
    //
    GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input (SPISIMOA)
    GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input (SPISOMIA)
    GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 3; // Asynch input (SPICLKA)
    GpioCtrlRegs.GPBQSEL1.bit.GPIO35 = 3; // Asynch input (SPISTEA)

    //
    // Configure SPI-A pins
    //
    // This specifies which of the possible GPIO pins will be SPI functional
    // pins.
    //
    GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 3; // Configure GPIO32 as SPISIMOA
    GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 3; // Configure GPIO33 as SPISOMIA
    GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // Configure GPIO34 as SPICLKA
    GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA


    SPI_PROGRAM_CS_GPAMUX1 = 0;//program CS for BL25CM1A
    SPI_PROGRAM_CS_GPAGMUX1 = 0;
    SPI_PROGRAM_CS_GPADIR = 1;
    SPI_PROGRAM_CS_GPADAT = 0;

    EDIS;
}


void spi_TurnOnCS1_GD25Q16E(void)
{
    EALLOW;
    GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // Configure GPIO35 as SPISTEA
    EDIS;
}

void spi_TurnOffCS1_GD25Q16E(void)
{
    EALLOW;
    GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 0;
    GpioDataRegs.GPBDAT.bit.GPIO35 = 1;
    EDIS;
}

void Gpio_SPI_CS_BL25CM1A(uint16_t out_bit)
{
    EALLOW;
    SPI_PROGRAM_CS_GPADAT = out_bit;
    EDIS;
}


void spi_transmitAData(uint16_t a)
{
    SpiaRegs.SPITXBUF = a<<8;
}


__interrupt void spia_rx_isr(void)
{
    uint16_t temp = SpiaRegs.SPISTS.all;
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
}


__interrupt void spia_tx_isr(void)
{
    uint16_t temp = SpiaRegs.SPISTS.all;
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
}





void SpiBInit(void)
{

    CpuSysRegs.PCLKCR8.bit.SPI_B = 1;

    SpibRegs.SPIFFTX.all = 0xE040;
    SpibRegs.SPIFFRX.all = 0x2044;
    SpibRegs.SPIFFCT.all = 0x0;

    //
    // Initialize core SPI registers
    //
    //
    // Set reset low before configuration changes
    // Clock polarity (0 == rising, 1 == falling)
    // 16-bit character
    // Enable loop-back
    //
    SpibRegs.SPICCR.bit.SPISWRESET = 0;
    SpibRegs.SPICCR.bit.CLKPOLARITY = 0;
    SpibRegs.SPICCR.bit.SPICHAR = (8 - 1);
    SpibRegs.SPICCR.bit.SPILBK = 0;

    //
    // Enable master (0 == slave, 1 == master)
    // Enable transmission (Talk)
    // Clock phase (0 == normal, 1 == delayed)
    // SPI interrupts are disabled
    //
    SpibRegs.SPICTL.bit.MASTER_SLAVE = 1;
    SpibRegs.SPICTL.bit.TALK = 1;
    SpibRegs.SPICTL.bit.CLK_PHASE = 1;
    SpibRegs.SPICTL.bit.SPIINTENA = 0;

    PieCtrlRegs.PIEIER6.bit.INTx3 = 0; //3.4.5 PIE Channel Mapping str 150 of trm
    PieCtrlRegs.PIEIER6.bit.INTx4 = 0;

    PieVectTable.SPIB_RX_INT = &spib_rx_isr;
    PieVectTable.SPIB_TX_INT = &spib_tx_isr;
    //
    // Set the baud rate using a 1 MHz SPICLK
    // BRR = (LSPCLK / SPICLK) - 1
    //
    SpibRegs.SPIBRR.bit.SPI_BIT_RATE = 99;

    // Set FREE bit
    // Halting on a breakpoint will not halt the SPI
    //
    SpibRegs.SPIPRI.bit.FREE = 1;

    //
    // Release the SPI from reset
    //
    SpibRegs.SPICCR.bit.SPISWRESET = 1;
}

void SpiBGpioInit(void)
{
       EALLOW;

    //
    // Enable internal pull-up for the selected pins
    //
    // Pull-ups can be enabled or disabled by the user.
    // This will enable the pullups for the specified pins.
    //
    GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0;  // Enable pull-up on GPIO16 (SPISIMOA)
    GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0;  // Enable pull-up on GPIO17 (SPISOMIA)
    GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0;  // Enable pull-up on GPIO18 (SPICLKA)
    GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0;  // Enable pull-up on GPIO19 (SPISTEA)

    //
    // Set qualification for selected pins to asynch only
    //
    // This will select asynch (no qualification) for the selected pins.
    //
    GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 3; // Asynch input GPIO16 (SPISIMOA)
    GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // Asynch input GPIO17 (SPISOMIA)
    GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; // Asynch input GPIO18 (SPICLKA)
    GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; // Asynch input GPIO19 (SPISTEA)

    //
    // Configure SPI-A pins
    //
    // This specifies which of the possible GPIO pins will be SPI functional
    // pins.
    //
    GPIO_SetupPinMux(24, 0, 6);
    GPIO_SetupPinMux(25, 0, 6);
    GPIO_SetupPinMux(26, 0, 6);
    GPIO_SetupPinMux(27, 0, 6);

//    GpioCtrlRegs.GPAMUX1.bit.GPIO24 = 2; // Configure GPIO16 as SPISIMOA
//    GpioCtrlRegs.GPAMUX1.bit.GPIO25 = 2; // Configure GPIO17 as SPISOMIA
//    GpioCtrlRegs.GPAMUX1.bit.GPIO26 = 2; // Configure GPIO18 as SPICLKA
//    GpioCtrlRegs.GPAMUX1.bit.GPIO27 = 2; // Configure GPIO19 as SPISTEA
//    GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO16 as SPISIMOA
//    GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO17 as SPISOMIA
//    GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO18 as SPICLKA
//    GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO19 as SPISTEA
    EDIS;
}

void transmitBData(uint16_t a)
{
    SpibRegs.SPITXBUF = a<<8;
}


__interrupt void spib_rx_isr(void)
{
    uint16_t temp = SpibRegs.SPISTS.all;
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
}


__interrupt void spib_tx_isr(void)
{
    uint16_t temp = SpibRegs.SPISTS.all;
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP6;
}