529 lines
15 KiB
C
529 lines
15 KiB
C
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//###########################################################################
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//
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// FILE: interrupt.c
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//
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// TITLE: Driver for the NVIC Interrupt Controller.
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//
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//###########################################################################
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// $TI Release: F2838x Support Library v3.04.00.00 $
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// $Release Date: Fri Feb 12 19:08:49 IST 2021 $
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// $Copyright:
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// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#include "interrupt.h"
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//*****************************************************************************
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//
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// RAM Vector Table to be used as srcVectorTable in
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// Interrupt_initRAMVectorTable(). Set the size of the vector table to the
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// largest number of interrupts of any device.
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//
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//*****************************************************************************
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#ifndef USE_RTOS
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#pragma DATA_ALIGN(vectorTableRAM, 1024U)
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#pragma DATA_SECTION(vectorTableRAM, ".vtable")
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#pragma WEAK(vectorTableRAM)
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void (*vectorTableRAM[NUM_INTERRUPTS])(void);
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#endif
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//*****************************************************************************
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//
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// Interrupt_enable()
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//
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//*****************************************************************************
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void
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Interrupt_enable(uint32_t interruptNum)
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{
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//
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// Check the arguments.
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//
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ASSERT(interruptNum < NUM_INTERRUPTS);
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//
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// Enable the interrupt.
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//
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if(interruptNum == FAULT_MPU)
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{
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HWREG(NVIC_BASE + NVIC_O_SHCSRS) |= NVIC_SHCSRS_MEMFAULTENA;
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}
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else if(interruptNum == FAULT_BUS)
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{
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HWREG(NVIC_BASE + NVIC_O_SHCSRS) |= NVIC_SHCSRS_BUSFAULTENA;
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}
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else if(interruptNum == FAULT_USAGE)
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{
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HWREG(NVIC_BASE + NVIC_O_SHCSRS) |= NVIC_SHCSRS_USGFAULTENA;
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}
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else if(interruptNum == FAULT_SYSTICK)
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{
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HWREG(NVIC_BASE + NVIC_O_SYST_CSR) |= NVIC_SYST_CSR_TICKINT;
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}
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else if(interruptNum >= 16U)
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{
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HWREG(NVIC_BASE + NVIC_O_ISER0 +
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(NVIC_OFFSET_INC * ((interruptNum - 16U) / 32U))) =
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(uint32_t)1U << ((interruptNum - 16U) & 0x1FU);
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}
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else
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{
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//
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// Do Nothing.
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//
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}
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}
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//*****************************************************************************
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//
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// Interrupt_disable()
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//
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//*****************************************************************************
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void
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Interrupt_disable(uint32_t interruptNum)
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{
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//
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// Check the arguments.
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//
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ASSERT(interruptNum <= NUM_INTERRUPTS);
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//
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// Disable the interrupt.
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//
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if(interruptNum == FAULT_MPU)
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{
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HWREG(NVIC_BASE + NVIC_O_SHCSRS) &= ~NVIC_SHCSRS_MEMFAULTENA;
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}
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else if(interruptNum == FAULT_BUS)
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{
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HWREG(NVIC_BASE + NVIC_O_SHCSRS) &= ~NVIC_SHCSRS_BUSFAULTENA;
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}
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else if(interruptNum == FAULT_USAGE)
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{
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HWREG(NVIC_BASE + NVIC_O_SHCSRS) &= ~NVIC_SHCSRS_USGFAULTENA;
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}
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else if(interruptNum == FAULT_SYSTICK)
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{
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HWREG(NVIC_BASE + NVIC_O_SYST_CSR) &= ~NVIC_SYST_CSR_TICKINT;
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}
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else if(interruptNum >= 16U)
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{
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HWREG(NVIC_BASE + NVIC_O_ICER0 +
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(NVIC_OFFSET_INC * ((interruptNum - 16U) / 32U))) =
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(uint32_t)1U << ((interruptNum - 16U) & 0x1FU);
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}
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else
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{
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//
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// Do Nothing.
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//
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}
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}
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//*****************************************************************************
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//
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// Interrupt_isEnabled()
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//
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//*****************************************************************************
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bool
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Interrupt_isEnabled(uint32_t interruptNum)
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{
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uint32_t status;
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//
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// Check the arguments.
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//
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ASSERT(interruptNum <= NUM_INTERRUPTS);
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//
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// Return the interrupt status
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//
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if(interruptNum == FAULT_MPU)
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{
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status = HWREG(NVIC_BASE + NVIC_O_SHCSRS) & NVIC_SHCSRS_MEMFAULTENA;
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}
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else if(interruptNum == FAULT_BUS)
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{
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status = HWREG(NVIC_BASE + NVIC_O_SHCSRS) & NVIC_SHCSRS_BUSFAULTENA;
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}
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else if(interruptNum == FAULT_USAGE)
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{
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status = HWREG(NVIC_BASE + NVIC_O_SHCSRS) & NVIC_SHCSRS_USGFAULTENA;
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}
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else if(interruptNum == FAULT_SYSTICK)
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{
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status = HWREG(NVIC_BASE + NVIC_O_SYST_CSR) & NVIC_SYST_CSR_TICKINT;
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}
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else if(interruptNum >= 16U)
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{
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status = HWREG(NVIC_BASE + (uint32_t)NVIC_O_ISER0 +
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(NVIC_OFFSET_INC * ((interruptNum - 16U) / 32U))) &
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(1U << ((interruptNum - 16U) & 0x1FU));
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}
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else
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{
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status = 0U;
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}
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//
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// Return peripheral interrupt status.
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//
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return(status != 0U);
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}
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//*****************************************************************************
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//
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// Interrupt_pend()
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//
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//*****************************************************************************
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void
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Interrupt_pend(uint32_t interruptNum)
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{
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//
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// Check the arguments.
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//
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ASSERT(interruptNum <= NUM_INTERRUPTS);
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//
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// Pends the corresponding channel interrupt.
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//
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if(interruptNum == FAULT_NMI)
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{
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HWREG(NVIC_BASE + NVIC_O_ICSR) |= NVIC_ICSR_NMIPENDSET;
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}
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else if(interruptNum == FAULT_PENDSV)
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{
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HWREG(NVIC_BASE + NVIC_O_ICSR) |= NVIC_ICSR_PENDSVSET;
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}
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else if(interruptNum == FAULT_SYSTICK)
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{
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HWREG(NVIC_BASE + NVIC_O_ICSR) |= NVIC_ICSR_PENDSTSET;
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}
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else if(interruptNum == FAULT_SVCALL)
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{
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HWREG(NVIC_BASE + NVIC_O_SHCSRS) |= NVIC_SHCSRS_SVCALLPENDED;
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}
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else if(interruptNum == FAULT_BUS)
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{
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HWREG(NVIC_BASE + NVIC_O_SHCSRS) |= NVIC_SHCSRS_BUSFAULTPENDED;
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}
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else if(interruptNum == FAULT_MPU)
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{
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HWREG(NVIC_BASE + NVIC_O_SHCSRS) |= NVIC_SHCSRS_MEMFAULTPENDED;
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}
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else if(interruptNum == FAULT_USAGE)
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{
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HWREG(NVIC_BASE + NVIC_O_SHCSRS) |= NVIC_SHCSRS_USGFAULTPENDED;
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}
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else if(interruptNum >= 16U)
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{
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HWREG(NVIC_BASE + NVIC_O_ISPR0 +
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(NVIC_OFFSET_INC * ((interruptNum - 16U) / 32U))) =
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(uint32_t)1U << ((interruptNum - 16U) & 0x1FU);
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}
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else
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{
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//
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// Do Nothing.
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//
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}
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}
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//*****************************************************************************
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//
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// Interrupt_unpend()
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//
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//*****************************************************************************
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void
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Interrupt_unpend(uint32_t interruptNum)
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{
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//
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// Check the arguments.
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//
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ASSERT(interruptNum <= NUM_INTERRUPTS);
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//
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// Unpends the corresponding channel interrupt.
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//
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if(interruptNum == FAULT_PENDSV)
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{
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HWREG(NVIC_BASE + NVIC_O_ICSR) |= NVIC_ICSR_PENDSVCLR;
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}
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else if(interruptNum == FAULT_SYSTICK)
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{
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HWREG(NVIC_BASE + NVIC_O_ICSR) |= NVIC_ICSR_PENDSTCLR;
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}
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else if(interruptNum == FAULT_SVCALL)
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{
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HWREG(NVIC_BASE + NVIC_O_SHCSRS) &= ~NVIC_SHCSRS_SVCALLPENDED;
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}
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else if(interruptNum == FAULT_BUS)
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{
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HWREG(NVIC_BASE + NVIC_O_SHCSRS) &= ~NVIC_SHCSRS_BUSFAULTPENDED;
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}
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else if(interruptNum == FAULT_MPU)
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{
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HWREG(NVIC_BASE + NVIC_O_SHCSRS) &= ~NVIC_SHCSRS_MEMFAULTPENDED;
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}
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else if(interruptNum == FAULT_USAGE)
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{
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HWREG(NVIC_BASE + NVIC_O_SHCSRS) &= ~NVIC_SHCSRS_USGFAULTPENDED;
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}
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else if(interruptNum >= 16U)
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{
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HWREG(NVIC_BASE + NVIC_O_ICPR0 +
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(NVIC_OFFSET_INC * ((interruptNum - 16U) / 32U))) =
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(uint32_t)1U << ((interruptNum - 16U) & (uint32_t)0x1FU);
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}
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else
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{
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//
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// Do Nothing.
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//
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}
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}
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//*****************************************************************************
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//
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// Interrupt_setPriority()
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//
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//*****************************************************************************
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void
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Interrupt_setPriority(uint32_t interruptNum, uint32_t priority)
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{
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uint32_t offset, shift;
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//
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// Check the arguments.
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//
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ASSERT((interruptNum >= 4U) && (interruptNum < NUM_INTERRUPTS));
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//
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// Set the interrupt priority.
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//
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if(interruptNum == FAULT_MPU)
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{
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HWREG(NVIC_BASE + NVIC_O_SHPR1) = (HWREG(NVIC_BASE + NVIC_O_SHPR1) &
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~(uint32_t)NVIC_SHPR1_PRI_4_M) |
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(priority << NVIC_SHPR1_PRI_4_S);
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}
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else if(interruptNum == FAULT_BUS)
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{
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HWREG(NVIC_BASE + NVIC_O_SHPR1) = (HWREG(NVIC_BASE + NVIC_O_SHPR1) &
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~(uint32_t)NVIC_SHPR1_PRI_5_M) |
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(priority << NVIC_SHPR1_PRI_5_S);
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}
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else if(interruptNum == FAULT_USAGE)
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{
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HWREG(NVIC_BASE + NVIC_O_SHPR1) = (HWREG(NVIC_BASE + NVIC_O_SHPR1) &
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~(uint32_t)NVIC_SHPR1_PRI_6_M) |
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(priority << NVIC_SHPR1_PRI_6_S);
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}
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else if(interruptNum == FAULT_SVCALL)
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{
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HWREG(NVIC_BASE + NVIC_O_SHPR2) = (HWREG(NVIC_BASE + NVIC_O_SHPR2) &
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~(uint32_t)NVIC_SHPR2_PRI_11_M) |
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(priority << NVIC_SHPR2_PRI_11_S);
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}
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else if(interruptNum == FAULT_PENDSV)
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{
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HWREG(NVIC_BASE + NVIC_O_SHPR3) = (HWREG(NVIC_BASE + NVIC_O_SHPR3) &
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~(uint32_t)NVIC_SHPR3_PRI_14_M) |
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(priority << NVIC_SHPR3_PRI_14_S);
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}
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else if(interruptNum == FAULT_SYSTICK)
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{
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HWREG(NVIC_BASE + NVIC_O_SHPR3) = (HWREG(NVIC_BASE + NVIC_O_SHPR3) &
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~(uint32_t)NVIC_SHPR3_PRI_15_M) |
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(priority << NVIC_SHPR3_PRI_15_S);
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}
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else if(interruptNum >= 16U)
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{
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offset = (uint32_t)NVIC_OFFSET_INC * ((interruptNum - 16U) / 4U);
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|
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shift = ((uint32_t)8U * (interruptNum & 0x3U)) + 5U;
|
||
|
|
|
||
|
|
HWREG(NVIC_BASE + NVIC_O_IPR0 + offset) =
|
||
|
|
(HWREG(NVIC_BASE + (uint32_t)NVIC_O_IPR0 + offset) &
|
||
|
|
~((uint32_t)NVIC_IPR0_PRI_0_M << shift)) |
|
||
|
|
(priority << shift);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Do Nothing.
|
||
|
|
//
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// Interrupt_getPriority()
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
uint32_t
|
||
|
|
Interrupt_getPriority(uint32_t interruptNum)
|
||
|
|
{
|
||
|
|
uint32_t offset, shift, status;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT((interruptNum >= 4U) && (interruptNum < NUM_INTERRUPTS));
|
||
|
|
|
||
|
|
//
|
||
|
|
// Set the interrupt priority.
|
||
|
|
//
|
||
|
|
if(interruptNum == FAULT_MPU)
|
||
|
|
{
|
||
|
|
status = (HWREG(NVIC_BASE + NVIC_O_SHPR1) & NVIC_SHPR1_PRI_4_M) >>
|
||
|
|
NVIC_SHPR1_PRI_4_S;
|
||
|
|
}
|
||
|
|
else if(interruptNum == FAULT_BUS)
|
||
|
|
{
|
||
|
|
status = (HWREG(NVIC_BASE + NVIC_O_SHPR1) & NVIC_SHPR1_PRI_5_M) >>
|
||
|
|
NVIC_SHPR1_PRI_5_S;
|
||
|
|
}
|
||
|
|
else if(interruptNum == FAULT_USAGE)
|
||
|
|
{
|
||
|
|
status = (HWREG(NVIC_BASE + NVIC_O_SHPR1) & NVIC_SHPR1_PRI_6_M) >>
|
||
|
|
NVIC_SHPR1_PRI_6_S;
|
||
|
|
}
|
||
|
|
else if(interruptNum == FAULT_SVCALL)
|
||
|
|
{
|
||
|
|
status = (HWREG(NVIC_BASE + NVIC_O_SHPR2) & NVIC_SHPR2_PRI_11_M) >>
|
||
|
|
NVIC_SHPR2_PRI_11_S;
|
||
|
|
}
|
||
|
|
else if(interruptNum == FAULT_PENDSV)
|
||
|
|
{
|
||
|
|
status = (HWREG(NVIC_BASE + NVIC_O_SHPR3) & NVIC_SHPR3_PRI_14_M) >>
|
||
|
|
NVIC_SHPR3_PRI_14_S;
|
||
|
|
}
|
||
|
|
else if(interruptNum == FAULT_SYSTICK)
|
||
|
|
{
|
||
|
|
status = (HWREG(NVIC_BASE + NVIC_O_SHPR3) & NVIC_SHPR3_PRI_15_M) >>
|
||
|
|
NVIC_SHPR3_PRI_15_S;
|
||
|
|
}
|
||
|
|
else if(interruptNum >= 16U)
|
||
|
|
{
|
||
|
|
offset = (uint32_t)NVIC_OFFSET_INC * ((interruptNum - 16U) / 4U);
|
||
|
|
shift = ((uint32_t)8U * (interruptNum & 0x3U)) + 5U;
|
||
|
|
|
||
|
|
status = (HWREG(NVIC_BASE + (uint32_t)NVIC_O_IPR0 + offset) >> shift) &
|
||
|
|
0xFFU;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
status = 0U;
|
||
|
|
}
|
||
|
|
return(status);
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// Interrupt_initRAMVectorTable()
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
Interrupt_initRAMVectorTable(void (*srcVectorTable[])(void),
|
||
|
|
void (*dstVectorTable[])(void))
|
||
|
|
{
|
||
|
|
uint32_t index;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Check whether dstVectorTable lies in RAM and is correctly aligned.
|
||
|
|
//
|
||
|
|
ASSERT((uint32_t)dstVectorTable >= 0x20000000U);
|
||
|
|
ASSERT(((uint32_t)dstVectorTable & 0x000003FFU) == 0U);
|
||
|
|
|
||
|
|
if(HWREG(NVIC_BASE + NVIC_O_VTOR) != (uint32_t)dstVectorTable)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Point the NVIC at the RAM vector table.
|
||
|
|
//
|
||
|
|
HWREG(NVIC_BASE + NVIC_O_VTOR) = (uint32_t)dstVectorTable;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Copy the ISRs from temp vector table to RAM vector table.
|
||
|
|
//
|
||
|
|
for(index = 0U; index < NUM_INTERRUPTS; index++)
|
||
|
|
{
|
||
|
|
dstVectorTable[index] = srcVectorTable[index];
|
||
|
|
}
|
||
|
|
}
|
||
|
|
//*****************************************************************************
|
||
|
|
//
|
||
|
|
// Interrupt_registerHandler()
|
||
|
|
//
|
||
|
|
//*****************************************************************************
|
||
|
|
void
|
||
|
|
Interrupt_registerHandler(uint32_t interruptNum, void (*intHandler)(void))
|
||
|
|
{
|
||
|
|
uint32_t index, value;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Check the arguments.
|
||
|
|
//
|
||
|
|
ASSERT(interruptNum < NUM_INTERRUPTS);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Make sure that the RAM vector table is correctly aligned.
|
||
|
|
// Check vector table alignment in device datasheet.
|
||
|
|
//
|
||
|
|
ASSERT(((uint32_t)vectorTableRAM & 0x000003FFU) == 0U);
|
||
|
|
|
||
|
|
//
|
||
|
|
// See if the RAM vector table has been initialized.
|
||
|
|
//
|
||
|
|
if(HWREG(NVIC_BASE + NVIC_O_VTOR) != (uint32_t)vectorTableRAM)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Copy the vector table from the beginning of FLASH to the RAM vector
|
||
|
|
// table.
|
||
|
|
//
|
||
|
|
value = HWREG(NVIC_BASE + NVIC_O_VTOR);
|
||
|
|
for(index = 0U; index < NUM_INTERRUPTS; index++)
|
||
|
|
{
|
||
|
|
vectorTableRAM[index] = (void (*)(void))HWREG((index * 4U) + value);
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Point the NVIC at the RAM vector table.
|
||
|
|
//
|
||
|
|
HWREG(NVIC_BASE + NVIC_O_VTOR) = (uint32_t)vectorTableRAM;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Save the interrupt handler.
|
||
|
|
//
|
||
|
|
vectorTableRAM[interruptNum] = intHandler;
|
||
|
|
}
|