/*
 * init.c
 *
 *  Created on: 21 авг. 2023 г.
 *      Author: seklyuts
 */


#include <pwm_init.h>
#include "f28x_project.h"
#include "pwm_interrupts.h"
#include "gpio_init.h"

#define COUNT_UP          1
#define COUNT_DOWN        0

volatile struct EPWM_REGS * EPwmRegs[17] = {NULL,  &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, &EPwm4Regs, &EPwm5Regs, &EPwm6Regs, &EPwm7Regs, &EPwm8Regs, &EPwm9Regs, &EPwm10Regs, &EPwm11Regs, &EPwm12Regs, &EPwm13Regs, &EPwm14Regs, &EPwm15Regs, &EPwm16Regs};
uint32_t EPwmTimerIntCount[17];
uint16_t EPwm_DB_Direction[17];
volatile uint16_t PwmBrake100 = PERIOD_BRAKE;
volatile uint16_t PwmMotor100 = PERIOD_MOTOR;





void PWM_ABC_StopAllClose(void)
{
    EALLOW;
    EPwm2Regs.TZCTL.bit.TZA = 2;
    EPwm2Regs.TZCTL.bit.TZB = 2;
    EPwm3Regs.TZCTL.bit.TZA = 2;
    EPwm3Regs.TZCTL.bit.TZB = 2;
    EPwm4Regs.TZCTL.bit.TZA = 2;
    EPwm4Regs.TZCTL.bit.TZB = 2;
    EDIS;
}

void PWM_ABC_StartOut(void)
{
    EALLOW;
    EPwm2Regs.TZCTL.bit.TZA = 3;
    EPwm2Regs.TZCTL.bit.TZB = 3;
    EPwm3Regs.TZCTL.bit.TZA = 3;
    EPwm3Regs.TZCTL.bit.TZB = 3;
    EPwm4Regs.TZCTL.bit.TZA = 3;
    EPwm4Regs.TZCTL.bit.TZB = 3;
    EDIS;
}

void PWMAllInit(void)
{
//
// Initialize the Device Peripherals:
//
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
    EDIS;


    PwmBrake100 = PERIOD_BRAKE;
    PwmMotor100 = PERIOD_MOTOR;

//    PWMInit(1, PwmMotor100, INDEPENDED);
    PWMInit(2, PwmMotor100, COMPLIMENTARY);
//    PWMInit(3, PwmMotor100, COMPLIMENTARY);
//    PWMInit(4, PwmMotor100, COMPLIMENTARY);
//    PWMInit(5, PwmBrake100, INDEPENDED);
//    PWMInit(6, PwmMotor100, COMPLIMENTARY);
//
//    PWMInit(11, PwmMotor100, INDEPENDED);
//    PWMInit(12, PwmMotor100, INDEPENDED);
//
//    EPwm11Regs.CMPC = SDFM_DELAY;
//    EPwm11Regs.CMPD = SDFM_DELAY;
//    EPwm12Regs.CMPC = SDFM_DELAY;
//    EPwm12Regs.CMPD = SDFM_DELAY;
//    EPwm11Regs.CMPA.bit.CMPA =  SDFM_DELAY;
//    EPwm11Regs.CMPB.bit.CMPB =  SDFM_DELAY;
//    EPwm12Regs.CMPA.bit.CMPA =  SDFM_DELAY;
//    EPwm12Regs.CMPB.bit.CMPB =  SDFM_DELAY;

    EALLOW;
    EPwm2Regs.TZCTL.bit.TZA = 2;
    EPwm2Regs.TZCTL.bit.TZB = 2;
//    EPwm3Regs.TZCTL.bit.TZA = 2;
//    EPwm3Regs.TZCTL.bit.TZB = 2;
//    EPwm4Regs.TZCTL.bit.TZA = 2;
//    EPwm4Regs.TZCTL.bit.TZB = 2;
    EDIS;

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
    EDIS;
}


void PWMGpioInit(void)
{
    InitEPwm2Gpio();
    InitEPwm3Gpio();
    InitEPwm4Gpio();
    InitEPwm5Gpio();
    InitEPwm6Gpio();
    InitEPwm11Gpio();
}

void PWMInitEnable(void)
{
//    CpuSysRegs.PCLKCR2.bit.EPWM1=1;
    CpuSysRegs.PCLKCR2.bit.EPWM2=1;
//    CpuSysRegs.PCLKCR2.bit.EPWM3=1;
//    CpuSysRegs.PCLKCR2.bit.EPWM4=1;
//    CpuSysRegs.PCLKCR2.bit.EPWM5=1;
//    CpuSysRegs.PCLKCR2.bit.EPWM6=1;
}

void PWMInitInterruptEn(void)
{
    // Interrupts that are used in this example are re-mapped to
    // ISR functions found within this file.
    //
        EALLOW; // This is needed to write to EALLOW protected registers

        PieVectTable.EPWM2_INT = &epwm2_isr;

        EDIS;   // This is needed to disable write to EALLOW protected registers


        // Enable CPU INT3 which is connected to EPWM1-3 INT:
        //
            IER |= M_INT3;

        //
        // Enable EPWM INTn in the PIE: Group 3 interrupt 1-3 (page 150)
        //
//            PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
            PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
//            PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
//            PieCtrlRegs.PIEIER3.bit.INTx4 = 1;
//            PieCtrlRegs.PIEIER3.bit.INTx5 = 1;
//            PieCtrlRegs.PIEIER3.bit.INTx6 = 1;
//            PieCtrlRegs.PIEIER3.bit.INTx11 = 1;
}

void PWMInit(uint16_t Num, uint16_t Period, uint16_t Independed)
{

    if( (Num < 11)||(Num > 12) ) EPwmRegs[Num]->TBPRD = Period;
    else EPwmRegs[Num]->TBPRD = Period*2-1;// Set timer period
    EPwmRegs[Num]->TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
    EPwmRegs[Num]->TBCTR = 0x0000;                     // Clear counter

    //
    // Setup TBCLK
    //
    if( (Num < 11)||(Num > 12) ) EPwmRegs[Num]->TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
    else EPwmRegs[Num]->TBCTL.bit.CTRMODE = TB_COUNT_UP;

    EPwmRegs[Num]->TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
    EPwmRegs[Num]->TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwmRegs[Num]->TBCTL.bit.CLKDIV = TB_DIV1;

    EPwmRegs[Num]->CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
    EPwmRegs[Num]->CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwmRegs[Num]->CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwmRegs[Num]->CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    //
    // Setup compare
    //
    EALLOW;
    EPwmRegs[Num]->TZCTL.bit.TZA = 3;
    EPwmRegs[Num]->TZCTL.bit.TZB = 3;


    EPwmRegs[Num]->TZFRC.all = 4;
    EDIS;  //Программно выставляем TZ-событие
    //
    // Set actions
    //
    if( (Num < 11)||(Num > 12) )
    {
        EPwmRegs[Num]->AQCTLA.bit.CAU = AQ_SET;            // Set PWM1A on Zero
        EPwmRegs[Num]->AQCTLA.bit.CAD = AQ_CLEAR;
        EPwmRegs[Num]->AQCTLB.bit.CAU = AQ_CLEAR;          // Set PWM1A on Zero
        EPwmRegs[Num]->AQCTLB.bit.CAD = AQ_SET;
    }
    else
    {
        EPwmRegs[Num]->AQCTLA.bit.ZRO = AQ_SET;
        EPwmRegs[Num]->AQCTLA.bit.CAU = AQ_CLEAR;
        EPwmRegs[Num]->AQCTLB.bit.ZRO = AQ_SET;
        EPwmRegs[Num]->AQCTLB.bit.CBU = AQ_CLEAR;
    }
    //
    // Active Low PWMs - Setup Deadband
    //
    EPwmRegs[Num]->DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    if(Independed)
    {
        EPwmRegs[Num]->CMPA.bit.CMPA = Period;
        EPwmRegs[Num]->DBCTL.bit.POLSEL = DB_ACTV_HI; //DB_ACTV_HI - independ
        EPwmRegs[Num]->DBRED.bit.DBRED = 0;
        EPwmRegs[Num]->DBFED.bit.DBFED = 0;
    }
    else
    {
        EPwmRegs[Num]->CMPA.bit.CMPA = Period/2;
        EPwmRegs[Num]->DBCTL.bit.POLSEL = DB_ACTV_HIC;
        EPwmRegs[Num]->DBRED.bit.DBRED = EPWM_DB;
        EPwmRegs[Num]->DBFED.bit.DBFED = EPWM_DB;
    }
    EPwmRegs[Num]->DBCTL.bit.IN_MODE = DBA_ALL;

//    EPwm1_DB_Direction = COUNT_UP;

    //
    //
    if( (Num < 11)||(Num > 12) ) EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTR_ZERO;    // Select INT on Zero event
    else EPwmRegs[Num]->ETSEL.bit.INTSEL = ET_CTRU_CMPA;

    EPwmRegs[Num]->ETSEL.bit.INTEN = 1;               // Enable INT
    EPwmRegs[Num]->ETPS.bit.INTPRD = ET_1ST;          // Generate INT on 1 event
}




