MEMORY
{
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
   BEGIN            : origin = 0x000000, length = 0x000002 // CPU1 IPC SERVER
   BOOT_RSVD        : origin = 0x000002, length = 0x0001AF     /* Part of M0, BOOT rom will use this for stack */
   RAMM0            : origin = 0x0001B1, length = 0x00024F // CPU1 IPC SERVER
   RAMM1            : origin = 0x000400, length = 0x0003F8 // CPU1 IPC SERVER
//   RAMM1_RSVD       : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD0            : origin = 0x00C000, length = 0x000800 // CPU1 IPC SERVER
   RAMD1            : origin = 0x00C800, length = 0x000800 // CPU1 IPC SERVER
   RAMLS0           : origin = 0x008000, length = 0x000800 // CPU1 IPC SERVER
   RAMLS1           : origin = 0x008800, length = 0x000800 // CPU1 IPC SERVER
   RAMLS2           : origin = 0x009000, length = 0x000800 // CPU1 IPC SERVER
   RAMLS3           : origin = 0x009800, length = 0x000800 // CPU1 IPC SERVER
   RAMLS4           : origin = 0x00A000, length = 0x000800 // CPU1 IPC SERVER
   RAMLS5           : origin = 0x00A800, length = 0x000800 // CPU1 IPC BOOTLOADER
   RAMLS6           : origin = 0x00B000, length = 0x000800 // CPU1 IPC BOOTLOADER
   RAMLS7           : origin = 0x00B800, length = 0x000800 // CPU1 IPC BOOTLOADER
   RAMGS0           : origin = 0x00D000, length = 0x001000 // CPU1 IPC BOOTLOADER
   RAMGS1           : origin = 0x00E000, length = 0x001000 // CPU1 IPC SERVER
   RAMGS2           : origin = 0x00F000, length = 0x001000 // CPU2 IPC SERVER
   RAMGS3           : origin = 0x010000, length = 0x001000 // CPU2 IPC SERVER
   RAMGS4           : origin = 0x011000, length = 0x001000 // CPU1 IPC SERVER
   RAMGS5           : origin = 0x012000, length = 0x001000 // CM IPC BOOTLOADER
   USB_CM_FIRMWARE  : origin = 0x013000, length = 0x00A000 // CM USB SERVER
//   RAMGS15_RSVD     : origin = 0x01CFF8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   /* Flash sectors */
   FLASH0           : origin = 0x080000, length = 0x002000  /* on-chip Flash */
   FLASH1           : origin = 0x082000, length = 0x002000  /* on-chip Flash */
   FLASH2           : origin = 0x084000, length = 0x002000  /* on-chip Flash */
   FLASH3           : origin = 0x086000, length = 0x002000  /* on-chip Flash */
   FLASH4           : origin = 0x088000, length = 0x008000  /* on-chip Flash */
   FLASH5           : origin = 0x090000, length = 0x008000  /* on-chip Flash */
   FLASH6           : origin = 0x098000, length = 0x008000  /* on-chip Flash */
   FLASH7           : origin = 0x0A0000, length = 0x008000  /* on-chip Flash */
   FLASH8           : origin = 0x0A8000, length = 0x008000  /* on-chip Flash */
   FLASH9           : origin = 0x0B0000, length = 0x008000  /* on-chip Flash */
   FLASH10          : origin = 0x0B8000, length = 0x002000  /* on-chip Flash */
   FLASH11          : origin = 0x0BA000, length = 0x002000  /* on-chip Flash */
   FLASH12          : origin = 0x0BC000, length = 0x002000  /* on-chip Flash */
   FLASH13          : origin = 0x0BE000, length = 0x002000  /* on-chip Flash */

   CPU1TOCPU2RAM    : origin = 0x03A000, length = 0x000800
   CPU2TOCPU1RAM    : origin = 0x03B000, length = 0x000800

   CPUTOCMRAM       : origin = 0x039000, length = 0x000800
   CMTOCPURAM       : origin = 0x038000, length = 0x000800

   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
   RESET            : origin = 0x3FFFC0, length = 0x000002
}

SECTIONS
{
   codestart        : > BEGIN
   .text            : >> RAMM0 | RAMM1 | RAMD0 | RAMD1 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3
   .cinit           : > RAMGS4
   .switch          : > RAMLS3
   .reset           : > RAMLS3, TYPE = DSECT /* not used, */

   .stack           : > RAMLS4
#if defined(__TI_EABI__)
   .bss             : >> RAMLS4 | RAMGS1
   .bss:output      : > RAMLS4
   .init_array	    : > RAMLS4
   .const           : > RAMLS4
   .data			: > RAMLS4
   .sysmem			: > RAMLS4
#else
   .pinit           : > RAMLS4
   .ebss            : > RAMLS4
   .econst          : > RAMLS4
   .esysmem         : > RAMLS4
#endif

   MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
   MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
   MSGRAM_CPU_TO_CM   > CPUTOCMRAM, type=NOINIT
   MSGRAM_CM_TO_CPU   > CMTOCPURAM, type=NOINIT

      /* The following section definition are for SDFM examples */


    .TI.ramfunc : {} > RAMGS1

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/
