MEMORY
{
PAGE 0:
	BEGIN: origin = 0x000000, length = 0x000002
	BOOT_RSVD: origin = 0x000002, length = 0x0001AE     /* Part of M0, BOOT rom will use this for stack */

	RAM_M: 			origin = 0x0001B0, length = 0x000650
	RAM_D:			origin = 0x00C000, length = 0x001000
	RAM_LS:			origin = 0x008000, length = 0x004000

	CPU1TOCPU2RAM    : origin = 0x03A000, length = 0x000800
	CPU2TOCPU1RAM    : origin = 0x03B000, length = 0x000800

	CPUTOCMRAM       : origin = 0x039000, length = 0x000800
	CMTOCPURAM       : origin = 0x038000, length = 0x000800

	CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
	CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800

PAGE 1:

	RAM_GS: 		origin = 0x00D000, length = 0x010000

}


SECTIONS
{
   codestart        : > BEGIN

   .text            : > RAM_GS

   .cinit           : > RAM_D
   .switch          : > RAM_D

   .reset           : > BEGIN, TYPE = DSECT /* not used, */

   .stack           : > RAM_M

   .bss             : > RAM_D
   .bss:output      : > RAM_D
   .init_array      : > RAM_D
   .const           : > RAM_D
   .data            : > RAM_D
   .sysmem          : > RAM_LS

   MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
   MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
   MSGRAM_CPU_TO_CM   > CPUTOCMRAM, type=NOINIT
   MSGRAM_CM_TO_CPU   > CMTOCPURAM, type=NOINIT

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/