/*
 * frm_uart.c
 *
 *  Created on: 21 ���. 2023 �.
 *      Author: seklyuts
 */
#include "f28x_project.h"
//#include "f2838x_pinmux.h"
#include "frm_uart.h"

#define LSPCLK_HZ   50000000.0
//#define BAUD        57600.0
#define BAUD        4000000.0
#define BRR         LSPCLK_HZ/(BAUD*8) + 1

uint16_t frmEn = 0;


uint16_t FMSTRIsEnable(void)
{
    return frmEn;
}

void FMSTREnableClr(void)
{
    frmEn = 0;
}

void FMSTREnableSet(void)
{
    frmEn = 1;
}



void FRMUartInit(void)
{
    FMSTR_Init();
    EALLOW;
    CpuSysRegs.PCLKCR7.bit.SCI_A = 1;
    EDIS;


#ifdef REF0
       EALLOW;
       GpioDataRegs.GPADAT.bit.GPIO21 = 1;
       GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
       EDIS;
#else
       EALLOW;
       GpioDataRegs.GPEDAT.bit.GPIO133 = 1;
       GpioDataRegs.GPEDAT.bit.GPIO145 = 0;
       EDIS;

#endif


    EALLOW;
    SciaRegs.SCICCR.all = 0x0007;   // 1 stop bit,  No loopback
                                    // No parity,8 char bits,
                                    // async mode, idle-line protocol
    SciaRegs.SCICTL1.all = 0x0003;  // enable TX, RX, internal SCICLK,
                                    // Disable RX ERR, SLEEP, TXWAKE
    SciaRegs.SCICTL2.all = 0x0003;
    SciaRegs.SCICTL2.bit.TXINTENA = 0;
    SciaRegs.SCICTL2.bit.RXBKINTENA = 0;

    uint16_t Brr = BRR;

    SciaRegs.SCIHBAUD.all = 0xFF & (Brr>>8);//0x0002;
    SciaRegs.SCILBAUD.all = 0xFF & Brr;//0x008B;

    SciaRegs.SCICTL1.all = 0x0023;  // Relinquish SCI from Reset

    SciaRegs.SCICTL1.bit.RXENA = 1;
    SciaRegs.SCICTL1.bit.TXENA = 1;

    EDIS;
    FMSTREnableSet();
}




void FMSTR_SCI_PUTCHAR(char _data)
{
    SciaRegs.SCITXBUF.all =  _data;
}

char FMSTR_SCI_GETCHAR()
{
    return SciaRegs.SCIRXBUF.all;
}

void FMSTR_SCI_RE(void)
{
//    GpioDataRegs.GPCDAT.bit.GPIO83 = 0;
    SciaRegs.SCICTL1.bit.RXENA = 1;
}

void FMSTR_SCI_RD(void)
{
//    GpioDataRegs.GPCDAT.bit.GPIO83 = 1;
    SciaRegs.SCICTL1.bit.RXENA = 0;
}

void FMSTR_SCI_TE(void)
{
//    GpioDataRegs.GPADAT.bit.GPIO21 = 1;
    SciaRegs.SCICTL1.bit.TXENA = 1;
}

void FMSTR_SCI_TD(void)
{
//    GpioDataRegs.GPADAT.bit.GPIO21 = 0;
    SciaRegs.SCICTL1.bit.TXENA = 0;
}


FMSTR_SCISR FMSTR_SCI_RDCLRSR(void)
{
    FMSTR_SCISR SciSR = 0;

    if (SciaRegs.SCIRXST.bit.RXRDY)         // UART receive buffer full
    {
        SciSR = FMSTR_SCISR_RDRF;
    }

//    if (SciaRegs.SCIRXST.bit.RXWAKE)         // UART receive buffer full
//    {
//        SciSR = FMSTR_SCISR_RDRF;
//    }

    if(SciaRegs.SCICTL2.bit.TXEMPTY)       // UART is transmitting data or transmit register full (UART busy)
    {
        SciSR |= FMSTR_SCISR_TDRE;
    }

    return SciSR;
}