447 lines
14 KiB
C
447 lines
14 KiB
C
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//###########################################################################
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//
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// FILE: Example_2833xHRPWM_slider.c
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//
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// TITLE: High Resolution PWM with slider Example
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//
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//! \addtogroup f2833x_example_list
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//! <h1>High Resolution PWM with slider(hrpwm_slider)</h1>
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//!
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//! This example modifies the MEP control registers to show edge displacement
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//! due to HRPWM control blocks of the respective ePWM module, ePWM1A, 2A, 3A,
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//! and 4A channels (GPIO0, GPIO2, GPIO4, and GPIO6) will have fine edge
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//! movement due to HRPWM logic.
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//!
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//! \b Running \b the \b Application
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//! -# Launch the target configuration and connect to the target first
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//! -# Load the program and set it up to run in real time mode. Do not run yet!
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//! -# Load the Example_2833xHRPWM_slider.gel file (provded in the folder)
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//! -# Select the HRPWM FineDutySlider from the GEL menu. A FineDuty slider
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//! graphics will show up in CCS.
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//! -# Add "DutyFine" variable to the watch window
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//! -# Load the program and run. Use the Slider to and observe the epwm edge
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//! displacement for each slider step change. \n
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//!
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//! This explains the MEP control on the ePWMxA channels,
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//! -# 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT),\n
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//! ePWM1A toggle low/high with MEP control on rising edge \n
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//! ePWM1B toggle low/high with NO HRPWM control
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//! -# 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT),\n
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//! ePWM2A toggle low/high with MEP control on rising edge \n
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//! ePWM2B toggle low/high with NO HRPWM control
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//! -# 15MHz PWM (for 150 MHz SYSCLKOUT) or 10MHz PWM (for 100MHz SYSCLKOUT),\n
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//! ePWM3A toggle as high/low with MEP control on falling edge \n
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//! ePWM3B toggle low/high with NO HRPWM control
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//! -# 7.5MHz PWM (for 150 MHz SYSCLKOUT) or 5MHz PWM (for 100MHz SYSCLKOUT),\n
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//! ePWM4A toggle as high/low with MEP control on falling edge \n
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//! ePWM4B toggle low/high with NO HRPWM control
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//!
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//! \b External \b Connections \n
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//! - EPWM1A is on GPIO0
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//! - EPWM1B is on GPIO1
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//! - EPWM2A is on GPIO2
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//! - EPWM2B is on GPIO3
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//! - EPWM3A is on GPIO4
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//! - EPWM3B is on GPIO5
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//!
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//! \b Watch \b Variables \n
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//! - DutyFine
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//
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//###########################################################################
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// $TI Release: $
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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//
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// Included Files
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//
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#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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#include "DSP2833x_EPwm_defines.h" // useful defines for initialization
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//
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// Function prototypes
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//
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void HRPWM1_Config(int);
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void HRPWM2_Config(int);
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void HRPWM3_Config(int);
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void HRPWM4_Config(int);
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//
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// General System nets - Useful for debug
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//
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Uint16 i,j, duty, DutyFine, n,update;
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Uint32 temp;
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//
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// Main
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//
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void main(void)
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{
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//
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// Step 1. Initialize System Control:
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// PLL, WatchDog, enable Peripheral Clocks
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// This example function is found in the DSP2833x_SysCtrl.c file.
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//
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InitSysCtrl();
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//
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// Step 2. Initialize GPIO:
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// This example function is found in the DSP2833x_Gpio.c file and
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// illustrates how to set the GPIO to it's default state.
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//
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// InitGpio(); // Skipped for this example
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// For this case, just init GPIO for ePWM1-ePWM4
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//
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// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3, ePWM4
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// These functions are in the DSP2833x_EPwm.c file
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//
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InitEPwm1Gpio();
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InitEPwm2Gpio();
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InitEPwm3Gpio();
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InitEPwm4Gpio();
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//
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// Step 3. Clear all interrupts and initialize PIE vector table:
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// Disable CPU interrupts
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//
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DINT;
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//
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// Initialize the PIE control registers to their default state.
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// The default state is all PIE interrupts disabled and flags
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// are cleared.
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// This function is found in the DSP2833x_PieCtrl.c file.
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//
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InitPieCtrl();
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//
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// Disable CPU interrupts and clear all CPU interrupt flags
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//
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IER = 0x0000;
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IFR = 0x0000;
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//
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// Initialize the PIE vector table with pointers to the shell Interrupt
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// Service Routines (ISR).
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// This will populate the entire table, even if the interrupt
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// is not used in this example. This is useful for debug purposes.
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// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
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// This function is found in DSP2833x_PieVect.c.
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//
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InitPieVectTable();
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//
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// Step 4. Initialize all the Device Peripherals:
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// This function is found in DSP2833x_InitPeripherals.c
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//
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// InitPeripherals(); // Not required for this example
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//
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// For this example, only initialize the ePWM
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// Step 5. User specific code, enable interrupts
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//
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update =1;
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DutyFine =0;
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
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EDIS;
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//
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// Some useful Period vs Frequency values
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// SYSCLKOUT = 150MHz 100 MHz
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// -----------------------------------------
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// Period Frequency Frequency
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// 1000 150 kHz 100 KHz
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// 800 187 kHz 125 KHz
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// 600 250 kHz 167 KHz
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// 500 300 kHz 200 KHz
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// 250 600 kHz 400 KHz
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// 200 750 kHz 500 KHz
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// 100 1.5 MHz 1.0 MHz
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// 50 3.0 MHz 2.0 MHz
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// 25 6.0 MHz 4.0 MHz
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// 20 7.5 MHz 5.0 MHz
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// 12 12.5 MHz 8.33 MHz
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// 10 15.0 MHz 10.0 MHz
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// 9 16.7 MHz 11.1 MHz
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// 8 18.8 MHz 12.5 MHz
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// 7 21.4 MHz 14.3 MHz
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// 6 25.0 MHz 16.7 MHz
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// 5 30.0 MHz 20.0 MHz
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//
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//
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// ePWM and HRPWM register initialization
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//
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//
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// ePWM1 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz)
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//
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HRPWM1_Config(10);
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//
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// ePWM2 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz)
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//
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HRPWM2_Config(20);
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//
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// ePWM3 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz)
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//
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HRPWM3_Config(10);
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//
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// ePWM4 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz)
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//
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HRPWM4_Config(20);
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
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EDIS;
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while (update ==1)
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{
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//
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//for(DutyFine =1; DutyFine <256 ;DutyFine ++)
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//
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{
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//
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// Example, write to the HRPWM extension of CMPA
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//
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//
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// Left shift by 8 to write into MSB bits
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//
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EPwm1Regs.CMPA.half.CMPAHR = DutyFine << 8;
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//
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// Left shift by 8 to write into MSB bits
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//
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EPwm2Regs.CMPA.half.CMPAHR = DutyFine << 8;
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//
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// Example, 32-bit write to CMPA:CMPAHR
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//
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EPwm3Regs.CMPA.all = ((Uint32)EPwm3Regs.CMPA.half.CMPA << 16) +
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(DutyFine << 8);
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EPwm4Regs.CMPA.all = ((Uint32)EPwm4Regs.CMPA.half.CMPA << 16) +
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(DutyFine << 8);
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//
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// Dummy delay between MEP changes
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//
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//for (i=0;i<10000;i++)
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//{
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//
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//}
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}
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}
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}
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//
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// HRPWM1_Config -
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//
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void
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HRPWM1_Config(period)
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{
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//
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// ePWM1 register configuration with HRPWM
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// ePWM1A toggle low/high with MEP control on Rising edge
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//
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EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
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EPwm1Regs.TBPRD = period - 1; // PWM frequency = 1 / period
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EPwm1Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
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EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
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EPwm1Regs.CMPB = period / 2; // set duty 50% initially
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EPwm1Regs.TBPHS.all = 0;
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EPwm1Regs.TBCTR = 0;
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EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
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EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master
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EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
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EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
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EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
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EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
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EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
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EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
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EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
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EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high
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EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
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EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR;
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EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;
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EALLOW;
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EPwm1Regs.HRCNFG.all = 0x0;
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EPwm1Regs.HRCNFG.bit.EDGMODE = HR_REP; // MEP control on Rising edge
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EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;
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EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
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EDIS;
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}
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//
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// HRPWM2_Config -
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//
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void
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HRPWM2_Config(period)
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{
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//
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// ePWM2 register configuration with HRPWM
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// ePWM2A toggle low/high with MEP control on Rising edge
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//
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EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
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EPwm2Regs.TBPRD = period - 1; // PWM frequency = 1 / period
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EPwm2Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
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EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
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EPwm2Regs.CMPB = period / 2; // set duty 50% initially
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EPwm2Regs.TBPHS.all = 0;
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EPwm2Regs.TBCTR = 0;
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EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
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EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM2 is the Master
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EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
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EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
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EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
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EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
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EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
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EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
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EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
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EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle low/high
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EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;
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EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR;
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EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;
|
||
|
|
|
||
|
|
EALLOW;
|
||
|
|
EPwm2Regs.HRCNFG.all = 0x0;
|
||
|
|
EPwm2Regs.HRCNFG.bit.EDGMODE = HR_REP; // MEP control on Rising edge
|
||
|
|
EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP;
|
||
|
|
EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
|
||
|
|
|
||
|
|
EDIS;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// HRPWM3_Config -
|
||
|
|
//
|
||
|
|
void
|
||
|
|
HRPWM3_Config(period)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// ePWM3 register configuration with HRPWM
|
||
|
|
// ePWM3A toggle high/low with MEP control on falling edge
|
||
|
|
//
|
||
|
|
EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
|
||
|
|
EPwm3Regs.TBPRD = period - 1; // PWM frequency = 1 / period
|
||
|
|
EPwm3Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
|
||
|
|
EPwm3Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
|
||
|
|
EPwm3Regs.CMPB = period / 2; // set duty 50% initially
|
||
|
|
EPwm3Regs.TBPHS.all = 0;
|
||
|
|
EPwm3Regs.TBCTR = 0;
|
||
|
|
|
||
|
|
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
|
||
|
|
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM3 is the Master
|
||
|
|
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
|
||
|
|
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
|
||
|
|
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
|
||
|
|
|
||
|
|
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
|
||
|
|
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
|
||
|
|
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
|
||
|
|
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
|
||
|
|
|
||
|
|
EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low
|
||
|
|
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;
|
||
|
|
EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;
|
||
|
|
EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR;
|
||
|
|
|
||
|
|
EALLOW;
|
||
|
|
EPwm3Regs.HRCNFG.all = 0x0;
|
||
|
|
EPwm3Regs.HRCNFG.bit.EDGMODE = HR_FEP; // MEP control on falling edge
|
||
|
|
EPwm3Regs.HRCNFG.bit.CTLMODE = HR_CMP;
|
||
|
|
EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
|
||
|
|
EDIS;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// HRPWM4_Config -
|
||
|
|
//
|
||
|
|
void
|
||
|
|
HRPWM4_Config(period)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// ePWM4 register configuration with HRPWM
|
||
|
|
// ePWM4A toggle high/low with MEP control on falling edge
|
||
|
|
//
|
||
|
|
EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
|
||
|
|
EPwm4Regs.TBPRD = period - 1; // PWM frequency = 1 / period
|
||
|
|
EPwm4Regs.CMPA.half.CMPA = period / 2; // set duty 50% initially
|
||
|
|
EPwm4Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM extension
|
||
|
|
EPwm4Regs.CMPB = period / 2; // set duty 50% initially
|
||
|
|
EPwm4Regs.TBPHS.all = 0;
|
||
|
|
EPwm4Regs.TBCTR = 0;
|
||
|
|
|
||
|
|
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
|
||
|
|
EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // ePWM4 is the Master
|
||
|
|
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
|
||
|
|
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
|
||
|
|
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
|
||
|
|
|
||
|
|
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
|
||
|
|
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
|
||
|
|
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
|
||
|
|
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
|
||
|
|
|
||
|
|
EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle high/low
|
||
|
|
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;
|
||
|
|
EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET;
|
||
|
|
EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR;
|
||
|
|
|
||
|
|
EALLOW;
|
||
|
|
EPwm4Regs.HRCNFG.all = 0x0;
|
||
|
|
EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP; // MEP control on falling edge
|
||
|
|
EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP;
|
||
|
|
EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
|
||
|
|
EDIS;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// End of File
|
||
|
|
//
|
||
|
|
|