284 lines
7.8 KiB
C
284 lines
7.8 KiB
C
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//###########################################################################
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//
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// FILE: Example_2833xAdcToDMA.c
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//
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// TITLE: ADC to DMA Example
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//
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//! \addtogroup f2833x_example_list
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//! <h1> ADC to DMA (adc_dma)</h1>
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//!
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//! This ADC example uses ADC to convert 4 channels for each SOC received,
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//! with total of 10 SOCs.
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//! Each SOC initiates 4 conversions.
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//! DMA is used to capture the data on each SEQ1_INT. DMA will re-sort
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//! the data by channel sequentially, i.e. all channel0 data will be
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//! together and all channel1 data will be together.
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//!
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//! \b Watch \b Variables \n
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//! - DMABuf1 - DMA Buffer
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//
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//###########################################################################
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// $TI Release: $
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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//
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// Included Files
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//
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#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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//
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// Defines for ADC start parameters
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//
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#if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT
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//
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// HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz
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//
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#define ADC_MODCLK 0x3
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#endif
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#if (CPU_FRQ_100MHZ)
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//
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// HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz
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//
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#define ADC_MODCLK 0x2
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#endif
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//
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// ADC module clock = HSPCLK/2*ADC_CKPS = 25.0MHz/(1*2) = 12.5MHz
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//
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#define ADC_CKPS 0x1
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#define ADC_SHCLK 0xf // S/H width in ADC module periods = 16 ADC clocks
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#define AVG 1000 // Average sample limit
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#define ZOFFSET 0x00 // Average Zero offset
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#define BUF_SIZE 40 // Sample buffer size
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//
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// Globals
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//
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Uint16 j=0;
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#pragma DATA_SECTION(DMABuf1,"DMARAML4");
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volatile Uint16 DMABuf1[40];
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volatile Uint16 *DMADest;
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volatile Uint16 *DMASource;
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__interrupt void local_DINTCH1_ISR(void);
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//
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// Main
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//
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void main(void)
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{
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Uint16 i;
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//
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// Step 1. Initialize System Control:
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// PLL, WatchDog, enable Peripheral Clocks
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// This example function is found in the DSP2833x_SysCtrl.c file.
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//
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InitSysCtrl();
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//
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// Specific clock setting for this example
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//
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EALLOW;
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SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK
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EDIS;
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//
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// Step 2. Initialize GPIO:
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// This example function is found in the DSP2833x_Gpio.c file and
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// illustrates how to set the GPIO to it's default state.
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//
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// InitGpio(); // Skipped for this example
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//
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// Step 3. Clear all interrupts and initialize PIE vector table:
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// Disable CPU interrupts
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//
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DINT;
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//
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// Initialize the PIE control registers to their default state.
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// The default state is all PIE interrupts disabled and flags
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// are cleared.
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// This function is found in the DSP2833x_PieCtrl.c file.
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//
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InitPieCtrl();
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//
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// Disable CPU interrupts and clear all CPU interrupt flags:
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//
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IER = 0x0000;
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IFR = 0x0000;
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//
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// Initialize the PIE vector table with pointers to the shell Interrupt
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// Service Routines (ISR).
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// This will populate the entire table, even if the interrupt
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// is not used in this example. This is useful for debug purposes.
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// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
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// This function is found in DSP2833x_PieVect.c.
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//
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InitPieVectTable();
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//
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// Interrupts that are used in this example are re-mapped to
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// ISR functions found within this file.
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//
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EALLOW; // Allow access to EALLOW protected registers
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PieVectTable.DINTCH1= &local_DINTCH1_ISR;
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EDIS; // Disable access to EALLOW protected registers
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IER = M_INT7 ; //Enable INT7 (7.1 DMA Ch1)
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EnableInterrupts();
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//
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// Step 4. Initialize all the Device Peripherals:
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// This function is found in DSP2833x_InitPeripherals.c
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//
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// InitPeripherals(); // Not required for this example
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InitAdc(); // For this example, init the ADC
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//
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// Specific ADC setup for this example:
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//
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AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK;
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AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;
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AdcRegs.ADCTRL1.bit.SEQ_CASC = 0; // 0 Non-Cascaded Mode
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AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1;
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AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;
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AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;
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AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1;
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AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2;
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AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3;
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AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x0;
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AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x1;
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AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x2;
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AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x3;
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//
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// Set up ADC to perform 4 conversions for every SOC
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//
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AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 3;
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//
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// Step 5. User specific code, enable interrupts:
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//
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//
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// Initialize DMA
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//
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DMAInitialize();
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//
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// Clear Table
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//
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for (i=0; i<BUF_SIZE; i++)
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{
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DMABuf1[i] = 0;
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}
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//
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// Configure DMA Channel
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//
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//
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// Point DMA destination to the beginning of the array
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//
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DMADest = &DMABuf1[0];
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//
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// Point DMA source to ADC result register base
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//
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DMASource = &AdcMirror.ADCRESULT0;
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DMACH1AddrConfig(DMADest,DMASource);
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DMACH1BurstConfig(3,1,10);
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DMACH1TransferConfig(9,1,0);
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DMACH1WrapConfig(1,0,0,1);
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DMACH1ModeConfig(DMA_SEQ1INT,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,
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SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,
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CHINT_END,CHINT_ENABLE);
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StartDMACH1();
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//
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// Start SEQ1
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//
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AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x1;
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//
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// For this example will re-start manually
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//
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for(i=0;i<10;i++)
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{
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for(j=0;j<1000;j++)
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{
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}
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//
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// Normally ADC will be tied to ePWM, or timed routine
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//
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AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1;
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}
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}
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//
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// local_DINTCH1_ISR - INT7.1(DMA Channel 1)
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//
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__interrupt void
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local_DINTCH1_ISR(void)
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{
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//
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// To receive more interrupts from this PIE group, acknowledge this
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// interrupt
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//
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;
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//
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// Next two lines for debug only to halt the processor here
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// Remove after inserting ISR Code
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//
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__asm (" ESTOP0");
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for(;;);
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}
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//
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// End of File
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//
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