431 lines
12 KiB
C
431 lines
12 KiB
C
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//###########################################################################
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//
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// FILE: Example_2833xEPwmTimerInt.c
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//
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// TITLE: ePWM Timer Interrupt Example
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//
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//! \addtogroup f2833x_example_list
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//! <h1>ePWM Timer Interrupt (epwm_timer_interrupts)</h1>
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//!
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//! This example configures the ePWM Timers and increments a counter each
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//! time an interrupt is taken. \n
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//! In this example:
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//! - All ePWM's are initialized.
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//! - All timers have the same period.
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//! - The timers are started sync'ed.
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//! - An interrupt is taken on a zero event for each ePWM timer.
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//! - ePWM1: takes an interrupt every event.
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//! - ePWM2: takes an interrupt every 2nd event.
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//! - ePWM3: takes an interrupt every 3rd event.
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//! - ePWM4-ePWM6: takes an interrupt every event.
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//!
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//! Thus the Interrupt count for ePWM1, ePWM4, ePWM5, and ePWM6 should be
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//! equal.The interrupt count for ePWM2 should be about half that of ePWM1
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//! and the interrupt count for ePWM3 should be about 1/3 that of ePWM1.
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//!
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//! \b Watch \b Variables \n
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//! - EPwm1TimerIntCount
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//! - EPwm2TimerIntCount
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//! - EPwm3TimerIntCount
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//! - EPwm4TimerIntCount
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//! - EPwm5TimerIntCount
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//! - EPwm6TimerIntCount
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//
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//
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//###########################################################################
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// $TI Release: $
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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//
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// Included Files
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//
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#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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//
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// Defines that configure which ePWM timer interrupts are enabled at the
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// PIE level: 1 = enabled, 0 = disabled
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//
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#define PWM1_INT_ENABLE 1
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#define PWM2_INT_ENABLE 1
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#define PWM3_INT_ENABLE 1
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#define PWM4_INT_ENABLE 1
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#define PWM5_INT_ENABLE 1
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#define PWM6_INT_ENABLE 1
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//
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// Defines that configure the period for each timer
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//
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#define PWM1_TIMER_TBPRD 0x1FFF
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#define PWM2_TIMER_TBPRD 0x1FFF
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#define PWM3_TIMER_TBPRD 0x1FFF
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#define PWM4_TIMER_TBPRD 0x1FFF
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#define PWM5_TIMER_TBPRD 0x1FFF
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#define PWM6_TIMER_TBPRD 0x1FFF
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//
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// Function Prototypes
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//
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__interrupt void epwm1_timer_isr(void);
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__interrupt void epwm2_timer_isr(void);
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__interrupt void epwm3_timer_isr(void);
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__interrupt void epwm4_timer_isr(void);
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__interrupt void epwm5_timer_isr(void);
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__interrupt void epwm6_timer_isr(void);
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void InitEPwmTimer(void);
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//
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// Globals
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//
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Uint32 EPwm1TimerIntCount;
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Uint32 EPwm2TimerIntCount;
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Uint32 EPwm3TimerIntCount;
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Uint32 EPwm4TimerIntCount;
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Uint32 EPwm5TimerIntCount;
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Uint32 EPwm6TimerIntCount;
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void main(void)
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{
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int i;
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//
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// Step 1. Initialize System Control:
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// PLL, WatchDog, enable Peripheral Clocks
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// This example function is found in the DSP2833x_SysCtrl.c file.
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//
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InitSysCtrl();
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//
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// Step 2. Initialize GPIO:
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// This example function is found in the DSP2833x_Gpio.c file and
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// illustrates how to set the GPIO to it's default state.
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//
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// InitGpio(); // Skipped for this example
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//
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// Step 3. Clear all interrupts and initialize PIE vector table:
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// Disable CPU interrupts
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//
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DINT;
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//
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// Initialize the PIE control registers to their default state.
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// The default state is all PIE interrupts disabled and flags
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// are cleared.
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// This function is found in the DSP2833x_PieCtrl.c file.
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//
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InitPieCtrl();
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//
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// Disable CPU interrupts and clear all CPU interrupt flags:
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//
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IER = 0x0000;
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IFR = 0x0000;
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//
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// Initialize the PIE vector table with pointers to the shell Interrupt
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// Service Routines (ISR).
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// This will populate the entire table, even if the interrupt
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// is not used in this example. This is useful for debug purposes.
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// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
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// This function is found in DSP2833x_PieVect.c.
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//
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InitPieVectTable();
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//
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// Interrupts that are used in this example are re-mapped to
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// ISR functions found within this file.
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//
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EALLOW; // This is needed to write to EALLOW protected registers
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PieVectTable.EPWM1_INT = &epwm1_timer_isr;
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PieVectTable.EPWM2_INT = &epwm2_timer_isr;
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PieVectTable.EPWM3_INT = &epwm3_timer_isr;
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PieVectTable.EPWM4_INT = &epwm4_timer_isr;
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PieVectTable.EPWM5_INT = &epwm5_timer_isr;
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PieVectTable.EPWM6_INT = &epwm6_timer_isr;
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EDIS; // This is needed to disable write to EALLOW protected registers
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//
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// Step 4. Initialize all the Device Peripherals:
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// This function is found in DSP2833x_InitPeripherals.c
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//
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// InitPeripherals(); // Not required for this example
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InitEPwmTimer(); // For this example, only initialize the ePWM Timers
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//
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// Step 5. User specific code, enable interrupts
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//
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//
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// Initialize counters
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//
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EPwm1TimerIntCount = 0;
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EPwm2TimerIntCount = 0;
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EPwm3TimerIntCount = 0;
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EPwm4TimerIntCount = 0;
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EPwm5TimerIntCount = 0;
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EPwm6TimerIntCount = 0;
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//
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// Enable CPU INT3 which is connected to EPWM1-6 INT
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//
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IER |= M_INT3;
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//
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// Enable EPWM INTn in the PIE: Group 3 interrupt 1-6
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//
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PieCtrlRegs.PIEIER3.bit.INTx1 = PWM1_INT_ENABLE;
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PieCtrlRegs.PIEIER3.bit.INTx2 = PWM2_INT_ENABLE;
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PieCtrlRegs.PIEIER3.bit.INTx3 = PWM3_INT_ENABLE;
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PieCtrlRegs.PIEIER3.bit.INTx4 = PWM4_INT_ENABLE;
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PieCtrlRegs.PIEIER3.bit.INTx5 = PWM5_INT_ENABLE;
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PieCtrlRegs.PIEIER3.bit.INTx6 = PWM6_INT_ENABLE;
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//
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// Enable global Interrupts and higher priority real-time debug events
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//
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EINT; // Enable Global interrupt INTM
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ERTM; // Enable Global realtime interrupt DBGM
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//
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// Step 6. IDLE loop. Just sit and loop forever (optional)
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//
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for(;;)
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{
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__asm(" NOP");
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for(i=1;i<=10;i++)
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{
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}
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}
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}
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//
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// InitEPwmTimer -
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//
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void
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InitEPwmTimer()
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{
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks
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EDIS;
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//
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// Setup Sync
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//
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EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through
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EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through
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EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through
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EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through
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EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through
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EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through
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//
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// Allow each timer to be sync'ed
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//
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EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;
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EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
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EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;
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EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;
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EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE;
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EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE;
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EPwm1Regs.TBPHS.half.TBPHS = 100;
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EPwm2Regs.TBPHS.half.TBPHS = 200;
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EPwm3Regs.TBPHS.half.TBPHS = 300;
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EPwm4Regs.TBPHS.half.TBPHS = 400;
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EPwm5Regs.TBPHS.half.TBPHS = 500;
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EPwm6Regs.TBPHS.half.TBPHS = 600;
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EPwm1Regs.TBPRD = PWM1_TIMER_TBPRD;
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EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
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EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
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EPwm1Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // Enable INT
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EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
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EPwm2Regs.TBPRD = PWM2_TIMER_TBPRD;
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EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
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EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event
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EPwm2Regs.ETSEL.bit.INTEN = PWM2_INT_ENABLE; // Enable INT
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EPwm2Regs.ETPS.bit.INTPRD = ET_2ND; // Generate INT on 2nd event
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EPwm3Regs.TBPRD = PWM3_TIMER_TBPRD;
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EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
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EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event
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EPwm3Regs.ETSEL.bit.INTEN = PWM3_INT_ENABLE; // Enable INT
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EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
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EPwm4Regs.TBPRD = PWM4_TIMER_TBPRD;
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EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
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EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event
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EPwm4Regs.ETSEL.bit.INTEN = PWM4_INT_ENABLE; // Enable INT
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EPwm4Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
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EPwm5Regs.TBPRD = PWM5_TIMER_TBPRD;
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EPwm5Regs.TBCTL.bit.CTRMODE= TB_COUNT_UP; // Count up
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EPwm5Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event
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EPwm5Regs.ETSEL.bit.INTEN = PWM5_INT_ENABLE; // Enable INT
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EPwm5Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
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EPwm6Regs.TBPRD = PWM6_TIMER_TBPRD;
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EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
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EPwm6Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event
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EPwm6Regs.ETSEL.bit.INTEN = PWM6_INT_ENABLE; // Enable INT
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EPwm6Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced
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EDIS;
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}
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//
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// epwm1_timer_isr - Interrupt routines uses in this example
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//
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__interrupt void
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epwm1_timer_isr(void)
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{
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EPwm1TimerIntCount++;
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//
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// Clear INT flag for this timer
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//
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EPwm1Regs.ETCLR.bit.INT = 1;
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//
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// Acknowledge this interrupt to receive more interrupts from group 3
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//
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
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}
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//
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// epwm2_timer_isr -
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//
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__interrupt void
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epwm2_timer_isr(void)
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{
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EPwm2TimerIntCount++;
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//
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// Clear INT flag for this timer
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//
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EPwm2Regs.ETCLR.bit.INT = 1;
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//
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// Acknowledge this interrupt to receive more interrupts from group 3
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//
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// epwm3_timer_isr -
|
||
|
|
//
|
||
|
|
__interrupt void
|
||
|
|
epwm3_timer_isr(void)
|
||
|
|
{
|
||
|
|
EPwm3TimerIntCount++;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Clear INT flag for this timer
|
||
|
|
//
|
||
|
|
EPwm3Regs.ETCLR.bit.INT = 1;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Acknowledge this interrupt to receive more interrupts from group 3
|
||
|
|
//
|
||
|
|
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// epwm4_timer_isr -
|
||
|
|
//
|
||
|
|
__interrupt void
|
||
|
|
epwm4_timer_isr(void)
|
||
|
|
{
|
||
|
|
EPwm4TimerIntCount++;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Clear INT flag for this timer
|
||
|
|
//
|
||
|
|
EPwm4Regs.ETCLR.bit.INT = 1;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Acknowledge this interrupt to receive more interrupts from group 3
|
||
|
|
//
|
||
|
|
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// epwm5_timer_isr -
|
||
|
|
//
|
||
|
|
__interrupt void
|
||
|
|
epwm5_timer_isr(void)
|
||
|
|
{
|
||
|
|
EPwm5TimerIntCount++;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Clear INT flag for this timer
|
||
|
|
//
|
||
|
|
EPwm5Regs.ETCLR.bit.INT = 1;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Acknowledge this interrupt to receive more interrupts from group 3
|
||
|
|
//
|
||
|
|
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// epwm6_timer_isr -
|
||
|
|
//
|
||
|
|
__interrupt void
|
||
|
|
epwm6_timer_isr(void)
|
||
|
|
{
|
||
|
|
EPwm6TimerIntCount++;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Clear INT flag for this timer
|
||
|
|
//
|
||
|
|
EPwm6Regs.ETCLR.bit.INT = 1;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Acknowledge this interrupt to receive more interrupts from group 3
|
||
|
|
//
|
||
|
|
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// End of File
|
||
|
|
//
|
||
|
|
|