371 lines
9.9 KiB
C
371 lines
9.9 KiB
C
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//###########################################################################
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//
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// FILE: Example_2833xCodeRunFromXintf.c
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//
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// TITLE: Code Run from XINTF Example
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//
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//! \addtogroup f2833x_example_list
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//! <h1>Code Run from XINTF (xintf_run_from)</h1>
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//!
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//! This example configures CPU Timer0 and increments
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//! a counter each time the timer asserts an interrupt.
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//!
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//! The code is loaded into SARAM. The XINTF Zone 7 is
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//! configured for x16-bit data bus. A portion of the code
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//! is copied to XINTF for execution there.
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//!
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//! \b Watch \b Variables \n
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//! - CpuTimer0.InterruptCount
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//! - CpuTimer1.InterruptCount
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//! - CpuTimer2.InterruptCount
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//
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//###########################################################################
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// $TI Release: $
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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//
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// Included Files
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//
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#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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#include <string.h>
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//
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// These two functions will be loaded into SARAM and copied to XINTF zone 7 for
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// execution
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//
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#pragma CODE_SECTION(cpu_timer0_isr,"xintffuncs");
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#pragma CODE_SECTION(cpu_timer1_isr,"xintffuncs");
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//
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// Function Prototypes
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//
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void init_zone7(void);
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__interrupt void cpu_timer0_isr(void);
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__interrupt void cpu_timer1_isr(void);
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__interrupt void cpu_timer2_isr(void);
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//
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// Main
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//
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void main(void)
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{
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//
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// Step 1. Initialize System Control:
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// PLL, WatchDog, enable Peripheral Clocks
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// This example function is found in the DSP2833x_SysCtrl.c file.
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//
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InitSysCtrl();
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//
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// Step 2. Initialize GPIO:
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// This example function is found in the DSP2833x_Gpio.c file and
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// illustrates how to set the GPIO to it's default state.
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//
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// InitGpio(); // Skipped for this example
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//
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// Step 3. Clear all interrupts and initialize PIE vector table:
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// Disable CPU interrupts
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//
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DINT;
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//
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// Initialize the PIE control registers to their default state.
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// The default state is all PIE interrupts disabled and flags
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// are cleared.
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// This function is found in the DSP2833x_PieCtrl.c file.
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//
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InitPieCtrl();
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//
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// Disable CPU interrupts and clear all CPU interrupt flags
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//
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IER = 0x0000;
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IFR = 0x0000;
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//
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// Initialize the PIE vector table with pointers to the shell Interrupt
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// Service Routines (ISR).
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// This will populate the entire table, even if the interrupt
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// is not used in this example. This is useful for debug purposes.
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// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
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// This function is found in DSP2833x_PieVect.c.
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//
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InitPieVectTable();
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//
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// Interrupts that are used in this example are re-mapped to
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// ISR functions found within this file.
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//
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EALLOW; // This is needed to write to EALLOW protected registers
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PieVectTable.TINT0 = &cpu_timer0_isr;
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PieVectTable.XINT13 = &cpu_timer1_isr;
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PieVectTable.TINT2 = &cpu_timer2_isr;
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EDIS; // This is needed to disable write to EALLOW protected registers
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//
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// Step 4. Initialize the Device Peripheral. This function can be
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// found in DSP2833x_CpuTimers.c
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//
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InitCpuTimers(); // For this example, only initialize the Cpu Timers
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#if (CPU_FRQ_150MHZ)
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//
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// Configure CPU-Timer 0, 1, and 2 to interrupt every second:
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// 150MHz CPU Freq, 1 second Period (in uSeconds)
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//
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ConfigCpuTimer(&CpuTimer0, 150, 1000000);
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ConfigCpuTimer(&CpuTimer1, 150, 1000000);
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ConfigCpuTimer(&CpuTimer2, 150, 1000000);
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#endif
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#if (CPU_FRQ_100MHZ)
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//
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// Configure CPU-Timer 0, 1, and 2 to interrupt every second:
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// 100MHz CPU Freq, 1 second Period (in uSeconds)
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//
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ConfigCpuTimer(&CpuTimer0, 100, 1000000);
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ConfigCpuTimer(&CpuTimer1, 100, 1000000);
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ConfigCpuTimer(&CpuTimer2, 100, 1000000);
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#endif
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//
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// To ensure precise timing, use write-only instructions to write to the
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// entire register. Therefore, if any of the configuration bits are changed
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// in ConfigCpuTimer and InitCpuTimers (in DSP2833x_CpuTimers.h), the
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// below settings must also be updated.
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//
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//
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// Use write-only instruction to set TSS bit = 0
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//
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CpuTimer0Regs.TCR.all = 0x4000;
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//
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// Use write-only instruction to set TSS bit = 0
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//
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CpuTimer1Regs.TCR.all = 0x4000;
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//
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// Use write-only instruction to set TSS bit = 0
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//
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CpuTimer2Regs.TCR.all = 0x4000;
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//
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// Step 5. User specific code, enable interrupts:
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//
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//
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// Initialize XINTF Zone 7
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//
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init_zone7();
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//
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// Copy non-time critical code to XINTF
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// This includes the following ISR functions: cpu_timer0_isr(),
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// cpu_timer1_isr(). The XintffuncsLoadStart, XintffuncsLoadEnd,
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// and XintffuncsRunStart symbols are created by the linker. Refer to the
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// F28335_ram_xintf.cmd file.
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//
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memcpy(&XintffuncsRunStart, &XintffuncsLoadStart,
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(Uint32)&XintffuncsLoadSize);
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//
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// Enable CPU int1 which is connected to CPU-Timer 0, CPU int13
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// which is connected to CPU-Timer 1, and CPU int 14, which is connected
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// to CPU-Timer 2:
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//
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IER |= M_INT1;
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IER |= M_INT13;
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IER |= M_INT14;
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//
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// Enable TINT0 in the PIE: Group 1 interrupt 7
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//
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PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
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//
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// Enable global Interrupts and higher priority real-time debug events
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//
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EINT; // Enable Global interrupt INTM
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ERTM; // Enable Global realtime interrupt DBGM
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//
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// Step 6. IDLE loop. Just sit and loop forever (optional)
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//
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for(;;);
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}
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//
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// cpu_timer0_isr -
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//
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__interrupt void
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cpu_timer0_isr(void)
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{
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CpuTimer0.InterruptCount++;
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//
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// Acknowledge this interrupt to receive more interrupts from group 1
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//
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
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}
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//
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// cpu_timer1_isr -
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//
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__interrupt void
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cpu_timer1_isr(void)
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{
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CpuTimer1.InterruptCount++;
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//
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// The CPU acknowledges the interrupt.
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//
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EDIS;
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}
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//
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// cpu_timer2_isr -
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//
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__interrupt void
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cpu_timer2_isr(void)
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{
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EALLOW;
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CpuTimer2.InterruptCount++;
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//
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// The CPU acknowledges the interrupt.
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//
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EDIS;
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}
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//
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// init_zone7 - Configure the timing parameters for Zone 7.
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// Notes: This function should not be executed from XINTF. Adjust the timing
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// based on the data manual and external device requirements.
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//
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void
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init_zone7(void)
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{
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//
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// Make sure the XINTF clock is enabled
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//
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EALLOW;
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SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1;
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EDIS;
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//
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// Configure the GPIO for XINTF with a 16-bit data bus
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// This function is in DSP2833x_Xintf.c
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//
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InitXintf16Gpio();
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EALLOW;
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//
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// All Zones
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// Timing for all zones based on XTIMCLK = SYSCLKOUT
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//
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XintfRegs.XINTCNF2.bit.XTIMCLK = 0;
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//
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// Buffer up to 3 writes
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//
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XintfRegs.XINTCNF2.bit.WRBUFF = 3;
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//
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// XCLKOUT is enabled
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//
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XintfRegs.XINTCNF2.bit.CLKOFF = 0;
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//
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// XCLKOUT = XTIMCLK
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//
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XintfRegs.XINTCNF2.bit.CLKMODE = 0;
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//
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// Disable XHOLD to prevent XINTF bus from going into high impedance state
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// whenever TZ3 signal goes low. This occurs because TZ3 on GPIO14 is
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// shared with HOLD of XINTF
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//
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XintfRegs.XINTCNF2.bit.HOLD = 1;
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//
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// Zone 7
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// When using ready, ACTIVE must be 1 or greater. Lead must always be 1 or
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// greater. Zone write timing
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//
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XintfRegs.XTIMING7.bit.XWRLEAD = 1;
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XintfRegs.XTIMING7.bit.XWRACTIVE = 2;
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XintfRegs.XTIMING7.bit.XWRTRAIL = 1;
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//
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// Zone read timing
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//
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XintfRegs.XTIMING7.bit.XRDLEAD = 1;
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XintfRegs.XTIMING7.bit.XRDACTIVE = 3;
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XintfRegs.XTIMING7.bit.XRDTRAIL = 0;
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//
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// don't double all Zone read/write lead/active/trail timing
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//
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XintfRegs.XTIMING7.bit.X2TIMING = 0;
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//
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// Zone will not sample XREADY signal
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//
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XintfRegs.XTIMING7.bit.USEREADY = 0;
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XintfRegs.XTIMING7.bit.READYMODE = 0;
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//
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// 1,1 = x16 data bus
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// 0,1 = x32 data bus
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// other values are reserved
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//
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XintfRegs.XTIMING7.bit.XSIZE = 3;
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EDIS;
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//
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// Force a pipeline flush to ensure that the write to
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// the last register configured occurs before returning.
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//
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__asm(" RPT #7 || NOP");
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}
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//
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// End of File
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//
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