610 lines
17 KiB
C
610 lines
17 KiB
C
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//###########################################################################
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//
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// FILE: Example_2833xI2C_eeprom.c
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//
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// TITLE: I2C EEPROM Example
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//
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//! \addtogroup f2833x_example_list
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//! <h1>I2C EEPROM (i2c_eeprom)</h1>
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//!
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//! This program requires an external I2C EEPROM connected to
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//! the I2C bus at address 0x50. \n
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//! This program will write 1-14 words to EEPROM and read them back.
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//! The data written and the EEPROM address written to are contained
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//! in the message structure, \b I2cMsgOut1. The data read back will be
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//! contained in the message structure \b I2cMsgIn1.
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//!
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//! \b Watch \b Variables \n
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//! - I2cMsgIn1
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//! - I2cMsgOut1
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//
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//###########################################################################
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// $TI Release: $
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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//
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// Included Files
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//
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#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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//
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// Note: I2C Macros used in this example can be found in the
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// DSP2833x_I2C_defines.h file
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//
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//
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// Function Prototypes
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//
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void I2CA_Init(void);
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Uint16 I2CA_WriteData(struct I2CMSG *msg);
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Uint16 I2CA_ReadData(struct I2CMSG *msg);
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__interrupt void i2c_int1a_isr(void);
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void pass(void);
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void fail(void);
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//
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// Defines
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//
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#define I2C_SLAVE_ADDR 0x50
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#define I2C_NUMBYTES 4
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#define I2C_EEPROM_HIGH_ADDR 0x00
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#define I2C_EEPROM_LOW_ADDR 0x30
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//
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// Globals
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//
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//
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// Two bytes will be used for the outgoing address, thus only setup 14 bytes
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// maximum
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//
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struct I2CMSG I2cMsgOut1=
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{
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I2C_MSGSTAT_SEND_WITHSTOP,
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I2C_SLAVE_ADDR,
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I2C_NUMBYTES,
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I2C_EEPROM_HIGH_ADDR,
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I2C_EEPROM_LOW_ADDR,
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0x12, // Msg Byte 1
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0x34, // Msg Byte 2
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0x56, // Msg Byte 3
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0x78, // Msg Byte 4
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0x9A, // Msg Byte 5
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0xBC, // Msg Byte 6
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0xDE, // Msg Byte 7
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0xF0, // Msg Byte 8
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0x11, // Msg Byte 9
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0x10, // Msg Byte 10
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0x11, // Msg Byte 11
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0x12, // Msg Byte 12
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0x13, // Msg Byte 13
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0x12 // Msg Byte 14
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};
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struct I2CMSG I2cMsgIn1=
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{ I2C_MSGSTAT_SEND_NOSTOP,
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I2C_SLAVE_ADDR,
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I2C_NUMBYTES,
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I2C_EEPROM_HIGH_ADDR,
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I2C_EEPROM_LOW_ADDR
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};
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//
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// Globals
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//
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struct I2CMSG *CurrentMsgPtr; // Used in interrupts
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Uint16 PassCount;
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Uint16 FailCount;
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//
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// Main
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//
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void main(void)
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{
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Uint16 Error;
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Uint16 i;
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CurrentMsgPtr = &I2cMsgOut1;
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//
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// Step 1. Initialize System Control:
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// PLL, WatchDog, enable Peripheral Clocks
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// This example function is found in the DSP2833x_SysCtrl.c file.
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//
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InitSysCtrl();
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//
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// Step 2. Initialize GPIO:
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// This example function is found in the DSP2833x_Gpio.c file and
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// illustrates how to set the GPIO to it's default state.
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//
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// InitGpio();
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//
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// Setup only the GP I/O only for I2C functionality
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//
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InitI2CGpio();
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//
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// Step 3. Clear all interrupts and initialize PIE vector table
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// Disable CPU interrupts
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//
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DINT;
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//
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// Initialize PIE control registers to their default state.
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// The default state is all PIE interrupts disabled and flags
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// are cleared.
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// This function is found in the DSP2833x_PieCtrl.c file.
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//
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InitPieCtrl();
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//
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// Disable CPU interrupts and clear all CPU interrupt flags
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//
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IER = 0x0000;
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IFR = 0x0000;
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//
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// Initialize the PIE vector table with pointers to the shell Interrupt
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// Service Routines (ISR).
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// This will populate the entire table, even if the interrupt
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// is not used in this example. This is useful for debug purposes.
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// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
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// This function is found in DSP2833x_PieVect.c.
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//
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InitPieVectTable();
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//
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// Interrupts that are used in this example are re-mapped to
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// ISR functions found within this file.
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//
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EALLOW; // This is needed to write to EALLOW protected registers
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PieVectTable.I2CINT1A = &i2c_int1a_isr;
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EDIS; // This is needed to disable write to EALLOW protected registers
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//
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// Step 4. Initialize all the Device Peripherals:
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// This function is found in DSP2833x_InitPeripherals.c
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//
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// InitPeripherals(); // Not required for this example
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I2CA_Init();
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//
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// Step 5. User specific code
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//
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//
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// Clear Counters
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//
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PassCount = 0;
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FailCount = 0;
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//
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// Clear incoming message buffer
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//
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for (i = 0; i < I2C_MAX_BUFFER_SIZE; i++)
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{
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I2cMsgIn1.MsgBuffer[i] = 0x0000;
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}
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//
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// Enable interrupts required for this example
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//
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//
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// Enable I2C interrupt 1 in the PIE: Group 8 interrupt 1
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//
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PieCtrlRegs.PIEIER8.bit.INTx1 = 1;
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//
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// Enable CPU INT8 which is connected to PIE group 8
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//
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IER |= M_INT8;
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EINT;
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//
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// Application loop
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//
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for(;;)
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{
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//
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// Write data to EEPROM section
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//
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//
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// Check the outgoing message to see if it should be sent.
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// In this example it is initialized to send with a stop bit.
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//
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if(I2cMsgOut1.MsgStatus == I2C_MSGSTAT_SEND_WITHSTOP)
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{
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Error = I2CA_WriteData(&I2cMsgOut1);
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//
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// If communication is correctly initiated, set msg status to busy
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// and update CurrentMsgPtr for the interrupt service routine.
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// Otherwise, do nothing and try again next loop. Once message is
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// initiated, the I2C interrupts will handle the rest. Search for
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// ICINTR1A_ISR in the i2c_eeprom_isr.c file.
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//
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if (Error == I2C_SUCCESS)
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{
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CurrentMsgPtr = &I2cMsgOut1;
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I2cMsgOut1.MsgStatus = I2C_MSGSTAT_WRITE_BUSY;
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}
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} // end of write section
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//
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// Read data from EEPROM section
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//
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//
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// Check outgoing message status. Bypass read section if status is
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// not inactive.
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//
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if (I2cMsgOut1.MsgStatus == I2C_MSGSTAT_INACTIVE)
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{
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//
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// Check incoming message status.
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//
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if(I2cMsgIn1.MsgStatus == I2C_MSGSTAT_SEND_NOSTOP)
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{
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//
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// EEPROM address setup portion
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//
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while(I2CA_ReadData(&I2cMsgIn1) != I2C_SUCCESS)
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{
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//
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// Maybe setup an attempt counter to break an infinite
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// while loop. The EEPROM will send back a NACK while it is
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// performing a write operation. Even though the write
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// communique is complete at this point, the EEPROM could
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// still be busy programming the data. Therefore, multiple
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// attempts are necessary.
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//
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}
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//
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// Update current message pointer and message status
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//
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CurrentMsgPtr = &I2cMsgIn1;
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I2cMsgIn1.MsgStatus = I2C_MSGSTAT_SEND_NOSTOP_BUSY;
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}
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//
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// Once message has progressed past setting up the internal address
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// of the EEPROM, send a restart to read the data bytes from the
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// EEPROM. Complete the communique with a stop bit. MsgStatus is
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// updated in the interrupt service routine.
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//
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else if(I2cMsgIn1.MsgStatus == I2C_MSGSTAT_RESTART)
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{
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//
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// Read data portion
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//
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while(I2CA_ReadData(&I2cMsgIn1) != I2C_SUCCESS)
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{
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//
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// Maybe setup an attempt counter to break an infinite
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// while loop.
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//
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}
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//
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// Update current message pointer and message status
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//
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CurrentMsgPtr = &I2cMsgIn1;
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I2cMsgIn1.MsgStatus = I2C_MSGSTAT_READ_BUSY;
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}
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} // end of read section
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} // end of for(;;)
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} // end of main
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//
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// I2CA_Init -
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//
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void
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I2CA_Init(void)
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{
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//
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// Initialize I2C
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//
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I2caRegs.I2CSAR = 0x0050; // Slave address - EEPROM control code
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#if (CPU_FRQ_150MHZ) // Default - For 150MHz SYSCLKOUT
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//
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// Prescaler - need 7-12 Mhz on module clk (150/15 = 10MHz)
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//
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I2caRegs.I2CPSC.all = 14;
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#endif
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#if (CPU_FRQ_100MHZ) // For 100 MHz SYSCLKOUT
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//
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// Prescaler - need 7-12 Mhz on module clk (100/10 = 10MHz)
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//
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I2caRegs.I2CPSC.all = 9;
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#endif
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I2caRegs.I2CCLKL = 10; // NOTE: must be non zero
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I2caRegs.I2CCLKH = 5; // NOTE: must be non zero
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I2caRegs.I2CIER.all = 0x24; // Enable SCD & ARDY interrupts
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//
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// Take I2C out of reset
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// Stop I2C when suspended
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//
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I2caRegs.I2CMDR.all = 0x0020;
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I2caRegs.I2CFFTX.all = 0x6000; // Enable FIFO mode and TXFIFO
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I2caRegs.I2CFFRX.all = 0x2040; // Enable RXFIFO, clear RXFFINT,
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return;
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}
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//
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// I2CA_WriteData -
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//
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Uint16
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I2CA_WriteData(struct I2CMSG *msg)
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{
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Uint16 i;
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//
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// Wait until the STP bit is cleared from any previous master communication
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// Clearing of this bit by the module is delayed until after the SCD bit is
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// set. If this bit is not checked prior to initiating a new message, the
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// I2C could get confused.
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//
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if (I2caRegs.I2CMDR.bit.STP == 1)
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{
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|
|
return I2C_STP_NOT_READY_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Setup slave address
|
||
|
|
//
|
||
|
|
I2caRegs.I2CSAR = msg->SlaveAddress;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Check if bus busy
|
||
|
|
//
|
||
|
|
if (I2caRegs.I2CSTR.bit.BB == 1)
|
||
|
|
{
|
||
|
|
return I2C_BUS_BUSY_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Setup number of bytes to send MsgBuffer + Address
|
||
|
|
//
|
||
|
|
I2caRegs.I2CCNT = msg->NumOfBytes+2;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Setup data to send
|
||
|
|
//
|
||
|
|
I2caRegs.I2CDXR = msg->MemoryHighAddr;
|
||
|
|
I2caRegs.I2CDXR = msg->MemoryLowAddr;
|
||
|
|
|
||
|
|
for (i=0; i<msg->NumOfBytes; i++)
|
||
|
|
{
|
||
|
|
I2caRegs.I2CDXR = *(msg->MsgBuffer+i);
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Send start as master transmitter
|
||
|
|
//
|
||
|
|
I2caRegs.I2CMDR.all = 0x6E20;
|
||
|
|
|
||
|
|
return I2C_SUCCESS;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// I2CA_ReadData -
|
||
|
|
//
|
||
|
|
Uint16
|
||
|
|
I2CA_ReadData(struct I2CMSG *msg)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Wait until the STP bit is cleared from any previous master communication.
|
||
|
|
// Clearing of this bit by the module is delayed until after the SCD bit is
|
||
|
|
// set. If this bit is not checked prior to initiating a new message, the
|
||
|
|
// I2C could get confused.
|
||
|
|
//
|
||
|
|
if (I2caRegs.I2CMDR.bit.STP == 1)
|
||
|
|
{
|
||
|
|
return I2C_STP_NOT_READY_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
I2caRegs.I2CSAR = msg->SlaveAddress;
|
||
|
|
|
||
|
|
if(msg->MsgStatus == I2C_MSGSTAT_SEND_NOSTOP)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Check if bus busy
|
||
|
|
//
|
||
|
|
if (I2caRegs.I2CSTR.bit.BB == 1)
|
||
|
|
{
|
||
|
|
return I2C_BUS_BUSY_ERROR;
|
||
|
|
}
|
||
|
|
I2caRegs.I2CCNT = 2;
|
||
|
|
I2caRegs.I2CDXR = msg->MemoryHighAddr;
|
||
|
|
I2caRegs.I2CDXR = msg->MemoryLowAddr;
|
||
|
|
I2caRegs.I2CMDR.all = 0x2620; // Send data to setup EEPROM address
|
||
|
|
}
|
||
|
|
else if(msg->MsgStatus == I2C_MSGSTAT_RESTART)
|
||
|
|
{
|
||
|
|
I2caRegs.I2CCNT = msg->NumOfBytes; // Setup how many bytes to expect
|
||
|
|
I2caRegs.I2CMDR.all = 0x2C20; // Send restart as master receiver
|
||
|
|
}
|
||
|
|
|
||
|
|
return I2C_SUCCESS;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// i2c_int1a_isr - I2C-A
|
||
|
|
//
|
||
|
|
__interrupt void
|
||
|
|
i2c_int1a_isr(void)
|
||
|
|
{
|
||
|
|
Uint16 IntSource, i;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Read interrupt source
|
||
|
|
//
|
||
|
|
IntSource = I2caRegs.I2CISRC.all;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Interrupt source = stop condition detected
|
||
|
|
//
|
||
|
|
if(IntSource == I2C_SCD_ISRC)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// If completed message was writing data, reset msg to inactive state
|
||
|
|
//
|
||
|
|
if (CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_WRITE_BUSY)
|
||
|
|
{
|
||
|
|
CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_INACTIVE;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// If a message receives a NACK during the address setup portion
|
||
|
|
// of the EEPROM read, the code further below included in the
|
||
|
|
// register access ready interrupt source code will generate a stop
|
||
|
|
// condition. After the stop condition is received (here), set the
|
||
|
|
// message status to try again. User may want to limit the number
|
||
|
|
// of retries before generating an error.
|
||
|
|
//
|
||
|
|
if(CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_SEND_NOSTOP_BUSY)
|
||
|
|
{
|
||
|
|
CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_SEND_NOSTOP;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// If completed message was reading EEPROM data, reset msg
|
||
|
|
// to inactive state and read data from FIFO.
|
||
|
|
//
|
||
|
|
else if (CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_READ_BUSY)
|
||
|
|
{
|
||
|
|
CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_INACTIVE;
|
||
|
|
for(i=0; i < I2C_NUMBYTES; i++)
|
||
|
|
{
|
||
|
|
CurrentMsgPtr->MsgBuffer[i] = I2caRegs.I2CDRR;
|
||
|
|
}
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Check received data
|
||
|
|
//
|
||
|
|
for(i=0; i < I2C_NUMBYTES; i++)
|
||
|
|
{
|
||
|
|
if(I2cMsgIn1.MsgBuffer[i] == I2cMsgOut1.MsgBuffer[i])
|
||
|
|
{
|
||
|
|
PassCount++;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
FailCount++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if(PassCount == I2C_NUMBYTES)
|
||
|
|
{
|
||
|
|
pass();
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
fail();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
} // end of stop condition detected
|
||
|
|
|
||
|
|
//
|
||
|
|
// Interrupt source = Register Access Ready
|
||
|
|
// This interrupt is used to determine when the EEPROM address setup
|
||
|
|
// portion of the read data communication is complete. Since no stop bit is
|
||
|
|
// commanded, this flag tells us when the message has been sent instead of
|
||
|
|
// the SCD flag. If a NACK is received, clear the NACK bit and command a
|
||
|
|
// stop. Otherwise, move on to the read data portion of the communication.
|
||
|
|
//
|
||
|
|
else if(IntSource == I2C_ARDY_ISRC)
|
||
|
|
{
|
||
|
|
if(I2caRegs.I2CSTR.bit.NACK == 1)
|
||
|
|
{
|
||
|
|
I2caRegs.I2CMDR.bit.STP = 1;
|
||
|
|
I2caRegs.I2CSTR.all = I2C_CLR_NACK_BIT;
|
||
|
|
}
|
||
|
|
else if(CurrentMsgPtr->MsgStatus == I2C_MSGSTAT_SEND_NOSTOP_BUSY)
|
||
|
|
{
|
||
|
|
CurrentMsgPtr->MsgStatus = I2C_MSGSTAT_RESTART;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
else
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Generate some error due to invalid interrupt source
|
||
|
|
//
|
||
|
|
__asm(" ESTOP0");
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Enable future I2C (PIE Group 8) interrupts
|
||
|
|
//
|
||
|
|
PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// pass -
|
||
|
|
//
|
||
|
|
void pass()
|
||
|
|
{
|
||
|
|
__asm(" ESTOP0");
|
||
|
|
for(;;);
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// fail -
|
||
|
|
//
|
||
|
|
void fail()
|
||
|
|
{
|
||
|
|
__asm(" ESTOP0");
|
||
|
|
for(;;);
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// End of File
|
||
|
|
//
|
||
|
|
|