599 lines
17 KiB
C
599 lines
17 KiB
C
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//###########################################################################
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//
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// FILE: Example_2833xEPwmUpAQ.c
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//
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// TITLE: ePWM Action Qualifier Module using Upcount mode Example
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//
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//! \addtogroup f2833x_example_list
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//! <h1>ePWM Action Qualifier Module using Upcount mode (epwm_up_aq)</h1>
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//!
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//! This example configures ePWM1, ePWM2, ePWM3 to produce a waveform with
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//! independent modulation on EPWMxA and EPWMxB. The compare values CMPA
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//! and CMPB are modified within the ePWM's ISR. The TB counter is in upmode.
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//!
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//! Monitor the ePWM1 - ePWM3 pins on an oscilloscope.
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//!
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//! \b External \b Connections \n
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//! - EPWM1A is on GPIO0
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//! - EPWM1B is on GPIO1
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//! - EPWM2A is on GPIO2
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//! - EPWM2B is on GPIO3
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//! - EPWM3A is on GPIO4
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//! - EPWM3B is on GPIO5
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//
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//###########################################################################
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// $TI Release: $
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// $Release Date: $
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// $Copyright:
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// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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//
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// Included Files
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//
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#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
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//
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// Typedefs
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//
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typedef struct
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{
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volatile struct EPWM_REGS *EPwmRegHandle;
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Uint16 EPwm_CMPA_Direction;
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Uint16 EPwm_CMPB_Direction;
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Uint16 EPwmTimerIntCount;
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Uint16 EPwmMaxCMPA;
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Uint16 EPwmMinCMPA;
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Uint16 EPwmMaxCMPB;
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Uint16 EPwmMinCMPB;
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} EPWM_INFO;
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//
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// Function Prototypes
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//
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void InitEPwm1Example(void);
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void InitEPwm2Example(void);
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void InitEPwm3Example(void);
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__interrupt void epwm1_isr(void);
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__interrupt void epwm2_isr(void);
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__interrupt void epwm3_isr(void);
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void update_compare(EPWM_INFO*);
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//
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// Globals
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//
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EPWM_INFO epwm1_info;
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EPWM_INFO epwm2_info;
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EPWM_INFO epwm3_info;
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//
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// Defines that configure the period for each timer
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//
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#define EPWM1_TIMER_TBPRD 2000 // Period register
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#define EPWM1_MAX_CMPA 1950
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#define EPWM1_MIN_CMPA 50
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#define EPWM1_MAX_CMPB 1950
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#define EPWM1_MIN_CMPB 50
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#define EPWM2_TIMER_TBPRD 2000 // Period register
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#define EPWM2_MAX_CMPA 1950
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#define EPWM2_MIN_CMPA 50
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#define EPWM2_MAX_CMPB 1950
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#define EPWM2_MIN_CMPB 50
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#define EPWM3_TIMER_TBPRD 2000 // Period register
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#define EPWM3_MAX_CMPA 950
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#define EPWM3_MIN_CMPA 50
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#define EPWM3_MAX_CMPB 1950
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#define EPWM3_MIN_CMPB 1050
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//
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// Defines that keep track of which way the compare value is moving
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//
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#define EPWM_CMP_UP 1
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#define EPWM_CMP_DOWN 0
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//
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// Main
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//
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void main(void)
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{
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//
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// Step 1. Initialize System Control:
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// PLL, WatchDog, enable Peripheral Clocks
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// This example function is found in the DSP2833x_SysCtrl.c file.
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//
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InitSysCtrl();
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//
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// Step 2. Initialize GPIO:
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// This example function is found in the DSP2833x_Gpio.c file and
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// illustrates how to set the GPIO to it's default state.
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//
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// InitGpio(); // Skipped for this example
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//
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// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
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// These functions are in the DSP2833x_EPwm.c file
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//
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InitEPwm1Gpio();
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InitEPwm2Gpio();
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InitEPwm3Gpio();
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//
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// Step 3. Clear all interrupts and initialize PIE vector table:
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// Disable CPU interrupts
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//
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DINT;
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//
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// Initialize the PIE control registers to their default state.
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// The default state is all PIE interrupts disabled and flags
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// are cleared.
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// This function is found in the DSP2833x_PieCtrl.c file.
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//
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InitPieCtrl();
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//
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// Disable CPU interrupts and clear all CPU interrupt flags:
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//
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IER = 0x0000;
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IFR = 0x0000;
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//
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// Initialize the PIE vector table with pointers to the shell Interrupt
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// Service Routines (ISR).
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// This will populate the entire table, even if the interrupt
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// is not used in this example. This is useful for debug purposes.
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// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
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// This function is found in DSP2833x_PieVect.c.
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//
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InitPieVectTable();
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//
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// Interrupts that are used in this example are re-mapped to
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// ISR functions found within this file.
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//
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EALLOW; // This is needed to write to EALLOW protected registers
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PieVectTable.EPWM1_INT = &epwm1_isr;
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PieVectTable.EPWM2_INT = &epwm2_isr;
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PieVectTable.EPWM3_INT = &epwm3_isr;
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EDIS; // This is needed to disable write to EALLOW protected registers
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//
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// Step 4. Initialize all the Device Peripherals:
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// This function is found in DSP2833x_InitPeripherals.c
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//
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// InitPeripherals(); // Not required for this example
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//
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// For this example, only initialize the ePWM
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//
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
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EDIS;
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InitEPwm1Example();
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InitEPwm2Example();
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InitEPwm3Example();
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
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EDIS;
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//
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// Step 5. User specific code, enable interrupts
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//
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//
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// Enable CPU INT3 which is connected to EPWM1-3 INT
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//
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IER |= M_INT3;
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//
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// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
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//
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PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
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PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
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PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
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//
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// Enable global Interrupts and higher priority real-time debug events
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//
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EINT; // Enable Global interrupt INTM
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ERTM; // Enable Global realtime interrupt DBGM
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//
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// Step 6. IDLE loop. Just sit and loop forever (optional)
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//
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for(;;)
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{
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__asm(" NOP");
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}
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}
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//
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// epwm1_isr -
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//
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__interrupt void
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epwm1_isr(void)
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{
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//
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// Update the CMPA and CMPB values
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//
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update_compare(&epwm1_info);
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//
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// Clear INT flag for this timer
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//
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EPwm1Regs.ETCLR.bit.INT = 1;
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//
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// Acknowledge this interrupt to receive more interrupts from group 3
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//
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
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}
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//
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// epwm2_isr -
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//
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__interrupt void
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epwm2_isr(void)
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{
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//
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// Update the CMPA and CMPB values
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//
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update_compare(&epwm2_info);
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//
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// Clear INT flag for this timer
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//
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EPwm2Regs.ETCLR.bit.INT = 1;
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//
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// Acknowledge this interrupt to receive more interrupts from group 3
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//
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
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}
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//
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// epwm3_isr -
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//
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__interrupt void
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epwm3_isr(void)
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{
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//
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// Update the CMPA and CMPB values
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//
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update_compare(&epwm3_info);
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//
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// Clear INT flag for this timer
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//
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EPwm3Regs.ETCLR.bit.INT = 1;
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//
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// Acknowledge this interrupt to receive more interrupts from group 3
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//
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PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
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}
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//
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// InitEPwm1Example -
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//
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void
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InitEPwm1Example()
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{
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//
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// Setup TBCLK
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//
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EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
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EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period
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EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
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EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
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EPwm1Regs.TBCTR = 0x0000; // Clear counter
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EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT
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EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2;
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//
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// Setup shadow register load on ZERO
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//
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EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
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EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
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EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
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EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
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//
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// Set Compare values
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//
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EPwm1Regs.CMPA.half.CMPA = EPWM1_MIN_CMPA; // Set compare A value
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EPwm1Regs.CMPB = EPWM1_MIN_CMPB; // Set Compare B value
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//
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// Set actions
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//
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EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A on Zero
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EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on event A, up count
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EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero
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EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B, up count
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//
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// Interrupt where we will change the Compare Values
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//
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EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
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EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
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EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
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//
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// Information this example uses to keep track of the direction the
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// CMPA/CMPB values are moving, the min and max allowed values and
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// a pointer to the correct ePWM registers
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//
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//
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// Start by increasing CMPA & CMPB
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//
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epwm1_info.EPwm_CMPA_Direction = EPWM_CMP_UP;
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epwm1_info.EPwm_CMPB_Direction = EPWM_CMP_UP;
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epwm1_info.EPwmTimerIntCount = 0; // Zero the interrupt counter
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epwm1_info.EPwmRegHandle = &EPwm1Regs; //Set the pointer to the ePWM module
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epwm1_info.EPwmMaxCMPA = EPWM1_MAX_CMPA; // Setup min/max CMPA/CMPB values
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epwm1_info.EPwmMinCMPA = EPWM1_MIN_CMPA;
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epwm1_info.EPwmMaxCMPB = EPWM1_MAX_CMPB;
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epwm1_info.EPwmMinCMPB = EPWM1_MIN_CMPB;
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}
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||
|
|
|
||
|
|
//
|
||
|
|
// InitEPwm2Example -
|
||
|
|
//
|
||
|
|
void
|
||
|
|
InitEPwm2Example()
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Setup TBCLK
|
||
|
|
//
|
||
|
|
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
|
||
|
|
EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period
|
||
|
|
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
|
||
|
|
EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
|
||
|
|
EPwm2Regs.TBCTR = 0x0000; // Clear counter
|
||
|
|
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT
|
||
|
|
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV2;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Setup shadow register load on ZERO
|
||
|
|
//
|
||
|
|
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
|
||
|
|
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
|
||
|
|
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
|
||
|
|
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Set Compare values
|
||
|
|
//
|
||
|
|
EPwm2Regs.CMPA.half.CMPA = EPWM2_MIN_CMPA; // Set compare A value
|
||
|
|
EPwm2Regs.CMPB = EPWM2_MAX_CMPB; // Set Compare B value
|
||
|
|
|
||
|
|
//
|
||
|
|
// Set actions
|
||
|
|
//
|
||
|
|
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR; // Clear PWM2A on Period
|
||
|
|
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count
|
||
|
|
|
||
|
|
EPwm2Regs.AQCTLB.bit.PRD = AQ_CLEAR; // Clear PWM2B on Period
|
||
|
|
EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM2B on event B, up count
|
||
|
|
|
||
|
|
//
|
||
|
|
// Interrupt where we will change the Compare Values
|
||
|
|
//
|
||
|
|
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
|
||
|
|
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
|
||
|
|
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
|
||
|
|
|
||
|
|
//
|
||
|
|
// Information this example uses to keep track of the direction the
|
||
|
|
// CMPA/CMPB values are moving, the min and max allowed values and
|
||
|
|
// a pointer to the correct ePWM registers
|
||
|
|
//
|
||
|
|
epwm2_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA
|
||
|
|
epwm2_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; // and decreasing CMPB
|
||
|
|
epwm2_info.EPwmTimerIntCount = 0; // Zero the interrupt counter
|
||
|
|
epwm2_info.EPwmRegHandle = &EPwm2Regs; //Set the pointer to the ePWM module
|
||
|
|
epwm2_info.EPwmMaxCMPA = EPWM2_MAX_CMPA; // Setup min/max CMPA/CMPB values
|
||
|
|
epwm2_info.EPwmMinCMPA = EPWM2_MIN_CMPA;
|
||
|
|
epwm2_info.EPwmMaxCMPB = EPWM2_MAX_CMPB;
|
||
|
|
epwm2_info.EPwmMinCMPB = EPWM2_MIN_CMPB;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// InitEPwm3Example -
|
||
|
|
//
|
||
|
|
void
|
||
|
|
InitEPwm3Example(void)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Setup TBCLK
|
||
|
|
//
|
||
|
|
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
|
||
|
|
EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD; // Set timer period
|
||
|
|
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
|
||
|
|
EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
|
||
|
|
EPwm3Regs.TBCTR = 0x0000; // Clear counter
|
||
|
|
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
|
||
|
|
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Setup shadow register load on ZERO
|
||
|
|
//
|
||
|
|
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
|
||
|
|
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
|
||
|
|
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
|
||
|
|
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Set Compare values
|
||
|
|
//
|
||
|
|
EPwm3Regs.CMPA.half.CMPA = EPWM3_MIN_CMPA; // Set compare A value
|
||
|
|
EPwm3Regs.CMPB = EPWM3_MAX_CMPB; // Set Compare B value
|
||
|
|
|
||
|
|
//
|
||
|
|
// Set Actions
|
||
|
|
//
|
||
|
|
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on event B, up count
|
||
|
|
EPwm3Regs.AQCTLA.bit.CBU = AQ_CLEAR; // Clear PWM3A on event B, up count
|
||
|
|
|
||
|
|
EPwm3Regs.AQCTLB.bit.ZRO = AQ_TOGGLE; // Toggle EPWM3B on Zero
|
||
|
|
|
||
|
|
//
|
||
|
|
// Interrupt where we will change the Compare Values
|
||
|
|
//
|
||
|
|
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
|
||
|
|
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
|
||
|
|
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
|
||
|
|
|
||
|
|
//
|
||
|
|
// Start by increasing the compare A and decreasing compare B
|
||
|
|
//
|
||
|
|
epwm3_info.EPwm_CMPA_Direction = EPWM_CMP_UP;
|
||
|
|
epwm3_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Start the count at 0
|
||
|
|
//
|
||
|
|
epwm3_info.EPwmTimerIntCount = 0;
|
||
|
|
|
||
|
|
epwm3_info.EPwmRegHandle = &EPwm3Regs;
|
||
|
|
epwm3_info.EPwmMaxCMPA = EPWM3_MAX_CMPA;
|
||
|
|
epwm3_info.EPwmMinCMPA = EPWM3_MIN_CMPA;
|
||
|
|
epwm3_info.EPwmMaxCMPB = EPWM3_MAX_CMPB;
|
||
|
|
epwm3_info.EPwmMinCMPB = EPWM3_MIN_CMPB;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// update_compare -
|
||
|
|
//
|
||
|
|
void
|
||
|
|
update_compare(EPWM_INFO *epwm_info)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
// Every 10'th interrupt, change the CMPA/CMPB values
|
||
|
|
//
|
||
|
|
if(epwm_info->EPwmTimerIntCount == 10)
|
||
|
|
{
|
||
|
|
epwm_info->EPwmTimerIntCount = 0;
|
||
|
|
|
||
|
|
//
|
||
|
|
// If we were increasing CMPA, check to see if we reached the max value
|
||
|
|
// If not, increase CMPA else, change directions and decrease CMPA
|
||
|
|
//
|
||
|
|
if(epwm_info->EPwm_CMPA_Direction == EPWM_CMP_UP)
|
||
|
|
{
|
||
|
|
if(epwm_info->EPwmRegHandle->CMPA.half.CMPA <
|
||
|
|
epwm_info->EPwmMaxCMPA)
|
||
|
|
{
|
||
|
|
epwm_info->EPwmRegHandle->CMPA.half.CMPA++;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
epwm_info->EPwm_CMPA_Direction = EPWM_CMP_DOWN;
|
||
|
|
epwm_info->EPwmRegHandle->CMPA.half.CMPA--;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// If we were decreasing CMPA, check to see if we reached the min value
|
||
|
|
// If not, decrease CMPA else, change directions and increase CMPA
|
||
|
|
//
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if(epwm_info->EPwmRegHandle->CMPA.half.CMPA ==
|
||
|
|
epwm_info->EPwmMinCMPA)
|
||
|
|
{
|
||
|
|
epwm_info->EPwm_CMPA_Direction = EPWM_CMP_UP;
|
||
|
|
epwm_info->EPwmRegHandle->CMPA.half.CMPA++;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
epwm_info->EPwmRegHandle->CMPA.half.CMPA--;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// If we were increasing CMPB, check to see if we reached the max value
|
||
|
|
// If not, increase CMPB else, change directions and decrease CMPB
|
||
|
|
//
|
||
|
|
if(epwm_info->EPwm_CMPB_Direction == EPWM_CMP_UP)
|
||
|
|
{
|
||
|
|
if(epwm_info->EPwmRegHandle->CMPB < epwm_info->EPwmMaxCMPB)
|
||
|
|
{
|
||
|
|
epwm_info->EPwmRegHandle->CMPB++;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
epwm_info->EPwm_CMPB_Direction = EPWM_CMP_DOWN;
|
||
|
|
epwm_info->EPwmRegHandle->CMPB--;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// If we were decreasing CMPB, check to see if we reached the min value
|
||
|
|
// If not, decrease CMPB else, change directions and increase CMPB
|
||
|
|
//
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if(epwm_info->EPwmRegHandle->CMPB == epwm_info->EPwmMinCMPB)
|
||
|
|
{
|
||
|
|
epwm_info->EPwm_CMPB_Direction = EPWM_CMP_UP;
|
||
|
|
epwm_info->EPwmRegHandle->CMPB++;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
epwm_info->EPwmRegHandle->CMPB--;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
else
|
||
|
|
{
|
||
|
|
epwm_info->EPwmTimerIntCount++;
|
||
|
|
}
|
||
|
|
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// End of File
|
||
|
|
//
|
||
|
|
|