ac2f4d1789
- toolkit V2.8.0.1@14806 - BSL V1.8.0.0@14590 - tcpserver: V1.4.3.0@14676 (marshaller V2.4.0.1@14551)
104 lines
3.6 KiB
C
104 lines
3.6 KiB
C
/**************************************************************************************
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Copyright (c) Hilscher Gesellschaft fuer Systemautomation mbH. All Rights Reserved.
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***************************************************************************************
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$Id: netx90_4x00_romloader_dpm.h 14189 2021-08-31 10:49:31Z RMayer $:
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Description:
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netX90 and netX4000 ROM Loader DPM layout
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Changes:
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Date Description
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-----------------------------------------------------------------------------------
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2021-08-31 added some comments
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2018-11-30 initial version
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**************************************************************************************/
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#ifndef __NETX90_4X00_ROMLOADER_DPM_H__
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#define __NETX90_4X00_ROMLOADER_DPM_H__
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/*-----------------------------------------------*/
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/* netX90 chip identifier definitions */
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/*-----------------------------------------------*/
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#define HBOOT_DPM_NETX90_COOKIE 0x0900000D
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#define MSK_HBOOT_DPM_NETX90_TYPE 0x00FF0000
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#define MSK_HBOOT_DPM_NETX90_ROMSTEP 0x0000FF00
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/*-----------------------------------------------*/
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/* netX4000 chip identifier definitions */
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/*-----------------------------------------------*/
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#define HBOOT_DPM_NETX4000_COOKIE 0x84524C0B
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#define HBOOT_DPM_NETX4100_COOKIE 0x93615B0B
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/*-----------------------------------------------*/
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/* netX ROM code definitions */
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/*-----------------------------------------------*/
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/* The 'NXBL' DPM boot identifier ('NXBL') is shown when the ROM code is running. */
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#define HBOOT_V2_DPM_ID 0x4c42584e
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#define HBOOT_V2_DPM_ID_ADR 0x100
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/* Definition of the ROM code DPM layout and functions */
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#define HBOOT_V2_DPM_NETX_TO_HOST_BUFFERSIZE 0x0200
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#define HBOOT_V2_DPM_HOST_TO_NETX_BUFFERSIZE 0x0400
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#define HBOOT_V2_DPM_BITFLIP_BUFFERSIZE 0xf800
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#define DPM_BOOT_NETX_RECEIVED_CMD 0x01
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#define DPM_BOOT_NETX_SEND_CMD 0x02
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#define DPM_BOOT_HOST_SEND_CMD 0x01
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#define DPM_BOOT_HOST_RECEIVED_CMD 0x02
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#define SRT_HANDSHAKE_REG_ARM_DATA 16
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#define SRT_HANDSHAKE_REG_PC_DATA 24
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#define HBOOT_MSK_SYS_STA_BITFLIP 0x80
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#define MSK_HBOOT_dpm_sys_sta_NETX_STA_CODE_ro 0x00ff0000U
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#define SRT_HBOOT_dpm_sys_sta_NETX_STA_CODE_ro 8
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#define MSK_HBOOT_dpm_status_unlocked 0x00000001U
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#define SRT_HBOOT_dpm_status_unlocked 0
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typedef struct HBOOT_V2_DPM_CFG_AREA_STRUCT
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{
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volatile uint32_t aulReserved0[7];
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volatile uint32_t ulDpm_status;
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volatile uint32_t aulReserved1[46];
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volatile uint32_t ulDpm_sys_sta;
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volatile uint32_t ulDpm_reset_request;
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volatile uint32_t aulReserved5[7];
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volatile uint32_t ulDpm_netx_version;
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} HBOOT_V2_DPM_CFG_AREA_T;
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typedef struct HBOOT_V2_DPM_BLOCKS_STRUCTURE
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{
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volatile uint32_t ulDpmBootId;
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volatile uint32_t ulDpmByteSize;
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volatile uint32_t aulReserved_08[28];
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volatile uint32_t ulNetxToHostDataSize;
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volatile uint32_t ulHostToNetxDataSize;
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volatile uint32_t ulHandshake;
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volatile uint32_t aulReserved_84[31];
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volatile uint8_t aucNetxToHostData[HBOOT_V2_DPM_NETX_TO_HOST_BUFFERSIZE];
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volatile uint8_t aucHostToNetxData[HBOOT_V2_DPM_HOST_TO_NETX_BUFFERSIZE];
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} HBOOT_V2_DPM_BLOCKS_T;
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typedef struct HBOOT_V2_DPM_AREA_STRUCTURE
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{
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HBOOT_V2_DPM_CFG_AREA_T tConfigurationRegisters;
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HBOOT_V2_DPM_BLOCKS_T tDpmBlocks;
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volatile uint8_t aucBitflipArea[HBOOT_V2_DPM_BITFLIP_BUFFERSIZE];
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} HBOOT_V2_DPM_AREA_T;
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#endif /* __NETX90_4X00_ROMLOADER_DPM_H__ */
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