135 lines
4.7 KiB
C
135 lines
4.7 KiB
C
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/**************************************************************************************
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Copyright (c) Hilscher Gesellschaft fuer Systemautomation mbH. All Rights Reserved.
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***************************************************************************************
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$Id: netx51_romloader_dpm.h 6614 2014-10-08 13:24:44Z stephans $:
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Description:
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netX51 ROM Loader DPM layout
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Changes:
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Date Description
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-----------------------------------------------------------------------------------
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2014-01-10 initial version
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**************************************************************************************/
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#ifndef __NETX51_ROMLOADER_DPM__H
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#define __NETX51_ROMLOADER_DPM__H
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#define NETX51_DETECT_OFFSET1 (0xD9)
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#define NETX51_DETECT_VALUE1 (0xF2)
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#define NETX51_DETECT_OFFSET2 (0xCC)
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#define NETX51_DETECT_VALUE2 (0xF2)
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#define NETX51_BOOTID_OFFSET (0x100)
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#define NETX51_BOOTID_DPM 0x4C42584E /*!< 'NXBL' DPM boot identifier ('NXBL') */
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#define NETX51_BOOTID_DPM_STRING "NXBL" /*!< 'NXBL' DPM boot identifier ('NXBL') */
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#define NETX51_DPM_TONETXMBX_MSK 0x01
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#define NETX51_DPM_TOHOSTMBX_MSK 0x02
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typedef struct NETX51_HBOOT_HSK_AREA_Ttag
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{
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volatile uint32_t ulHandshakeFlag;
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uint32_t aulReserved[31];
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} NETX51_HBOOT_HSK_AREA_T;
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typedef struct NETX51_HBOOT_CFG_AREA_Ttag
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{
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volatile uint32_t ulDpmBootId;
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volatile uint32_t ulDpmByteSize;
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volatile uint32_t ulSdramGeneralCtrl;
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volatile uint32_t ulSdramTimingCtrl;
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volatile uint32_t ulSdramByteSize;
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volatile uint32_t aulReserved[25];
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volatile uint32_t ulNetXToHostDataSize;
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volatile uint32_t ulHostToNetxDataSize;
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} NETX51_HBOOT_CFG_AREA_T;
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#define MSK_NX56_dpm_rdy_cfg_rdy_pol (0x00000001)
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#define SRT_NX56_dpm_rdy_cfg_rdy_drv_mode (1)
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#define MSK_NX56_dpm_netx_version_step (0x000000FF)
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#define SRT_NX56_dpm_netx_version_step (0)
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#define MSK_NX56_dpm_netx_version_license (0x00000100)
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#define SRT_NX56_dpm_netx_version_license (8)
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#define MSK_NX56_dpm_netx_version_valid (0x00000200)
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#define SRT_NX56_dpm_netx_version_valid (9)
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#define MSK_NX56_dpm_netx_version_chiptype (0x00000c00)
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#define SRT_NX56_dpm_netx_version_chiptype (10)
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typedef struct NETX51_DPM_CONFIG_AREA_Ttag
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{
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volatile uint32_t ulDpmCfg0x0;
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volatile uint32_t ulDpmIfCfg;
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volatile uint32_t ulDpmPioCfg0;
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volatile uint32_t ulDpmPioCfg1;
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volatile uint32_t ulDpmAddrCfg;
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volatile uint32_t ulDpmTimingCfg;
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volatile uint32_t ulDpmRdyCfg;
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volatile uint32_t ulDpmStatus;
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volatile uint32_t ulDpmStatusErrReset;
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volatile uint32_t ulDpmStatusErrAddr;
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volatile uint32_t ulDpmMiscCfg;
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volatile uint32_t ulDpmIoCfgMisc;
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uint32_t aulReserved1[2];
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volatile uint32_t ulDpmTunnelCfg;
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volatile uint32_t ulDpmItbaddr;
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volatile uint32_t ulDpmWin1End;
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volatile uint32_t ulDpmWin1Map;
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volatile uint32_t ulDpmWin2End;
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volatile uint32_t ulDpmWin2Map;
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volatile uint32_t ulDpmWin3End;
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volatile uint32_t ulDpmWin3Map;
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volatile uint32_t ulDpmWin4End;
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volatile uint32_t ulDpmWin4Map;
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uint32_t aulReserved2[8];
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volatile uint32_t ulDpmIrqRaw;
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volatile uint32_t ulDpmIrqArmMaskSet;
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volatile uint32_t ulDpmIrqArmMaskReset;
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volatile uint32_t ulDpmIrqArmMasked;
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volatile uint32_t ulDpmIrqXpicMaskSet;
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volatile uint32_t ulDpmIrqXpicMaskReset;
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volatile uint32_t ulDpmIrqXpicMasked;
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volatile uint32_t ulDpmIrqFiqMaskSet;
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volatile uint32_t ulDpmIrqFiqMaskReset;
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volatile uint32_t ulDpmIrqFiqMasked;
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volatile uint32_t ulDpmIrqIrqMaskSet;
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volatile uint32_t ulDpmIrqIrqMaskReset;
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volatile uint32_t ulDpmIrqIrqMasked;
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uint32_t ulReserved3;
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volatile uint32_t ulDpmSwIrq;
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uint32_t ulReserved4;
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volatile uint32_t ulDpmReservedNetx50WgdHostTimeout;
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volatile uint32_t ulDpmReservedNetx50WgdHostTrigger;
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volatile uint32_t ulDpmReservedNetx50WgdNetxTimeout;
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volatile uint32_t ulDpmSysStaBigend16;
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volatile uint32_t ulDpmReservedNetx50TimerCtrl;
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volatile uint32_t ulDpmReservedNetx50TimerStartVal;
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volatile uint32_t ulDpmSysSta;
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volatile uint32_t ulDpmResetRequest;
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volatile uint32_t ulDpmFirmwareIrqRaw;
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uint32_t ulReserved5;
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volatile uint32_t ulDpmFirmwareIrqRaw2;
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uint32_t ulReserved6;
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volatile uint32_t ulDpmFirmwareIrqMask;
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volatile uint32_t ulDpmNetxVersionBigend16;
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volatile uint32_t ulDpmFirmwareIrqMask2;
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volatile uint32_t ulDpmNetxVersion;
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}NETX51_DPM_CONFIG_AREA_T;
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typedef struct NETX51_ROMLOADER_DPMtag
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{
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NETX51_DPM_CONFIG_AREA_T tDpmConfig;
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NETX51_HBOOT_CFG_AREA_T tHBootConfig;
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NETX51_HBOOT_HSK_AREA_T tHandshake;
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volatile uint8_t abNetxToHostData[512];
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volatile uint8_t abHostToNetxData[1024];
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} NETX51_ROMLOADER_DPM, *PNETX51_ROMLOADER_DPM;
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#endif /* __NETX51_ROMLOADER_DPM__H */
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