202 lines
8.2 KiB
C
202 lines
8.2 KiB
C
/*
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* Copyright (C) 2023 Texas Instruments Incorporated
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SDFM_H_
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#define _SDFM_H_
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#include <stdint.h>
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#include <drivers/pruicss.h>
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#include "current_sense/sdfm/include/sdfm_api.h"
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/* Status codes */
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#define SDFM_ERR_NERR ( 0 ) /* no error */
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#define SDFM_ERR_CFG_PIN_MUX ( -1 ) /* pin mux configuration error */
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#define SDFM_ERR_CFG_ICSSG_CLKCFG ( -2 ) /* ICSSG clock configuration error */
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#define SDFM_ERR_INIT_ICSSG ( -3 ) /* initialize ICSSG error */
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#define SDFM_ERR_CFG_MCU_INTR ( -4 ) /* interrupt configuration error */
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#define SDFM_ERR_INIT_PRU_SDFM ( -5 ) /* initialize PRU for SDFM error */
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#define SDFM_ERR_INIT_SDFM ( -6 ) /* initialize SDFM error */
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/* Bit for SDFM configuration mask */
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#define SDFM_CFG_CLK ( 1<<0 )
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#define SDFM_CFG_OSR ( 1<<1 )
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#define SDFM_CFG_TRIG_SAMP_TIME ( 1<<2 )
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#define SDFM_CFG_TRIG_SAMP_CNT ( 1<<3 )
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#define SDFM_CFG_CH_EN ( 1<<4 )
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#define SDFM_CFG_FD ( 1<<5 )
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#define SDFM_CFG_TRIG_OUT_SAMP_BUF ( 1<<6 )
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/* SDFM mode */
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#define SDFM_MODE_TRIG ( 0 )
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#define SDFM_MODE_CONT ( 1 )
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/* ICSSG Core clock source selection options */
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#define CORE_CLK_SEL_ICSSGn_CORE_CLK ( 0 ) /* Mux Output */
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#define CORE_CLK_SEL_ICSSGn_ICLK ( 1 ) /* ICSSGn_ICLK = MAIN_SYSCLK0/2 = 250 MHz */
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/* ICSSG Core clock selections in case Mux Output selected */
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#define ICSSGn_CORE_CLK_SEL_MAIN_PLL2_HSDIV0_CLKOUT ( 0 ) /* 225 or 300 MHz, default 225 MHz */
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#define ICSSGn_CORE_CLK_SEL_MAIN_PLL0_HSDIV9_CLKOUT ( 1 ) /* 200, 250, or 333 MHz, default 200 MHz */
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#define ICSSGn_CORE_CLK_SEL_NUMSEL ( 2 )
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/* ICSSG Core clock frequency in case Mux Output selected.
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Set to 0 in case clock frequency configuration not desired. */
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#define ICSSGn_CORE_CLK_FREQ_225MHZ ( 225000000UL ) /* MAIN PLL2 HSDIV0, 225 MHz */
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#define ICSSGn_CORE_CLK_FREQ_300MHZ ( 300000000UL ) /* MAIN PLL2 HSDIV0, 300 MHz */
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#define ICSSGn_CORE_CLK_FREQ_200MHZ ( 200000000UL ) /* MAIN PLL0 HSDIV9, 200 MHz */
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#define ICSSGn_CORE_CLK_FREQ_250MHZ ( 250000000UL ) /* MAIN PLL0 HSDIV9, 250 MHz */
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#define ICSSGn_CORE_CLK_FREQ_333MHZ ( 333333333UL ) /* MAIN PLL0 HSDIV9, 333 MHz */
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#define ICSSGn_CORE_CLK_FREQ_NOCFG ( 0UL ) /* No clock frequency reconfig */
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//#define ICSSGn_CORE_CLK_FREQ ( ICSSGn_CORE_CLK_FREQ_NOCFG )
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#define ICSSGn_CORE_CLK_FREQ ( ICSSGn_CORE_CLK_FREQ_300MHZ )
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//#define ICSSGn_CORE_CLK_FREQ ( ICSSGn_CORE_CLK_FREQ_333MHZ )
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/* ICSSG IEP clock source selection options */
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#define IEP_CLK_SEL_ICSSGn_IEP_CLK ( 0 ) /* Mux Output */
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#define IEP_CLK_SEL_CORE_CLK ( 1 ) /* CORE_CLK */
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/* ICSSG IEP clock selections in case Mux output selected */
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#define ICSSGn_IEP_CLK_SEL_MAIN_PLL2_HSDIV5_CLKOUT ( 0 ) /* Default 225 MHz */
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#define ICSSGn_IEP_CLK_SEL_MAIN_PLL0_HSDIV6_CLKOUT ( 1 ) /* 200 or 250 MHz, default 200 MHz */
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#define ICSSGn_IEP_CLK_SEL_CPSW0_CPTS_RFT_CLK ( 2 )
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#define ICSSGn_IEP_CLK_SEL_CPTS_RFT_CLK ( 3 )
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#define ICSSGn_IEP_CLK_SEL_MCU_EXT_REFCLK0 ( 4 )
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#define ICSSGn_IEP_CLK_SEL_EXT_REFCLK1 ( 5 )
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#define ICSSGn_IEP_CLK_SEL_SERDES0_IP1_LN0_TXMCLK ( 6 )
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#define ICSSGn_IEP_CLK_SEL_SYSCLK0 ( 7 )
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#define ICSSGn_IEP_CLK_SEL_NUMSEL ( 8 )
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/* ICSSG IEP clock frequency in case Mux Output selected.
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Set to 0 in case clock frequency configuration not desired. */
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#define ICSSGn_IEP_CLK_FREQ_200MHZ ( 200000000UL ) /* MAIN PLL0 HSDIV6, 200 MHz */
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#define ICSSGn_IEP_CLK_FREQ_250MHZ ( 250000000UL ) /* MAIN PLL0 HSDIV6, 250 MHz */
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#define ICSSGn_IEP_CLK_FREQ_NOCFG ( 0UL ) /* No clock frequency reconfig */
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#define ICSSGn_IEP_CLK_FREQ ( ICSSGn_IEP_CLK_FREQ_NOCFG )
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/* Default ICSS pin mux setting */
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#define PRUICSS_G_MUX_EN_DEF ( 0x0 ) /* ICSSG_SA_MX_REG:G_MUX_EN */
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/* Translate the TCM local view addr to SoC view addr */
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#define CPU0_ATCM_SOCVIEW(x) (CSL_R5FSS0_CORE0_ATCM_BASE+(x))
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#define CPU1_ATCM_SOCVIEW(x) (CSL_R5FSS1_CORE0_ATCM_BASE+(x))
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#define CPU0_BTCM_SOCVIEW(x) (CSL_R5FSS0_CORE0_BTCM_BASE+(x - CSL_R5FSS0_BTCM_BASE))
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#define CPU1_BTCM_SOCVIEW(x) (CSL_R5FSS1_CORE0_BTCM_BASE+(x - CSL_R5FSS1_BTCM_BASE))
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#define ICSSG_SLICE_ID_0 ( 0 ) /* ICSSG slide ID 0 */
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#define ICSSG_SLICE_ID_1 ( 1 ) /* ICSSG slide ID 1 */
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#define ICSSG_NUM_SLICE ( 2 ) /* ICSSG number of slices */
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#define NUM_FD_FIELD ( 3 )
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/* SDFM Channel IDs*/
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#define SDFM_CH0 (0)
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#define SDFM_CH1 (1)
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#define SDFM_CH2 (2)
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#define SDFM_CH3 (3)
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#define SDFM_CH4 (4)
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#define SDFM_CH5 (5)
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#define SDFM_CH6 (6)
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#define SDFM_CH7 (7)
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#define SDFM_CH8 (8)
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/*!
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* @brief PRUICSS Instance IDs
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*/
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typedef enum PRUICSS_MaxInstances_s
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{
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PRUICSS_INSTANCE_ONE=0,
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PRUICSS_INSTANCE_TWO=1,
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PRUICSS_INSTANCE_MAX=2
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} PRUICSS_MaxInstances;
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/* SDFM configuration parameters */
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typedef struct SdfmPrms_s
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{
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uint8_t loadShare;
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/**<PRU core instance ID*/
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uint8_t pruInsId;
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/**<ICSSG pru Slice ID*/
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uint8_t icssgSliceId;
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/**< PRU_CORE_CLOCK*/
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uint32_t pruClock;
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/**< IEP clock value */
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uint32_t iepClock[2];
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/**< Sigma delta input clock value */
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uint32_t sdClock;
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/**< double update enable field */
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uint8_t enSecondUpdate;
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/**< First normal current sample trigger time */
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float firstSampTrigTime;
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/**< First normal current sample trigger time */
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float secondSampTrigTime;
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/**< output freq. of EPWM0 */
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uint32_t epwmOutFreq;
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/**< Over current threshold parameters */
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SDFM_ThresholdParms thresholdParms[NUM_CH_SUPPORTED_PER_AXIS];
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/**< SD clock source and clock inversion */
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SDFM_ClkSourceParms clkPrms[3];
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/**< Over current OSR */
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uint16_t comFilterOsr;
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/**< Normal current OSR */
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uint16_t filterOsr;
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/**< over current enable field */
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uint8_t enComparator;
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/**< output samples base address*/
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uint32_t samplesBaseAddress;
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/**<enable fast detect*/
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uint8_t enFastDetect;
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/**<Fast detect configuration field*/
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uint8_t fastDetect[NUM_SD_CH][NUM_FD_FIELD];
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/**<Phase delay enbale */
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uint8_t phaseDelay;
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/**<Zero Cross enable field*/
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uint8_t enZeroCross;
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/**<Zero cross threshold*/
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uint32_t zcThr[NUM_CH_SUPPORTED_PER_AXIS];
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} SdfmPrms;
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/* Initialize ICSSG */
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int32_t initIcss(
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uint8_t icssInstId,
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uint8_t sliceId,
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uint8_t saMuxMode,
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uint8_t loadShareMode,
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PRUICSS_Handle *pPruIcssHandle
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);
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/* Initialize PRU core for SDFM */
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int32_t initPruSdfm(
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PRUICSS_Handle pruIcssHandle,
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uint8_t pruInstId,
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SdfmPrms *pSdfmPrms,
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sdfm_handle *pHSdfm
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);
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#endif /* _SDFM_H_ */
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