c5bc321959
- Align to coding guidelines - Remove am243x-evm examples Fixes: PINDSW-5479 Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
132 lines
5.8 KiB
C
132 lines
5.8 KiB
C
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; Copyright (C) 2023 Texas Instruments Incorporated
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the
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; distribution.
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;
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; Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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;************************************************************************************
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;* File: bissc_params.h *
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;* *
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;* Brief: Defining Register usage and setting BissC specific parameters *
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;************************************************************************************
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; register usage
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; R1-R6 - flipflops for otf crc.
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; R7 - holds received crc for position data and used as ex for otf calculation.
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; R8.b0 - valid bit,rx enable, rx valid, R8.b1 - holds channel mask, R8.w2 - stores raw data length (pos_data_length + ew_length + pos_crc_length).
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; R9.b0 - holds fifo bit index(middle bit) of oversampled data, R9.b1 - holds base offset for channel in use, R9.w2 - holds CFG0 offset for channel in use.
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; R10 - flipflops for control communication otf crc.
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; R11.b1 - holds 4-bit control communication crc, R11.b2 - holds cds data, R11.b3 - holds ctrl otf crc.
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; R12.b0 - control command bit pointer, R12.b1 - control cycle counter.
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; R12.b2 - holds the channel number for channel in use, R12.b3 - holds encoder offset for encoder connected in daisy chain.
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; R13-R14 - holds raw data for channel 0, R15-R16 - holds raw data for channel 1, R17-R18 - holds raw data for channel 2.
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; R19 - holds cds backup for one biss-c cycle.
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; R20 - Used as flag register.
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; R21 - holds hex equivalent control command.
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; R22 - holds daisy chain configurations.
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; R23.b0 - used for execution status for each PRU in load share. R23.b1 - holds primary core mask.
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; R23.w2 -it is used as status register.
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; R24-R27 - scratch.
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; R29 - holds call and return (branch) address.
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; unused Register: R11.b0, R28
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.asg R1, FF0
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.asg R2, FF1
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.asg R3, FF2
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.asg R4, FF3
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.asg R5, FF4
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.asg R6, FF5
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.asg R7, EX
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.asg R7, BISSC_RCV_CRC
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.asg R8.b0, VALID_BIT_IDX
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.asg R8.b0, BISSC_RX_EN
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.asg R8.b0, BISSC_RX_VALID
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.asg R8.b1, CH_MASK
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.asg R8.w2, RAW_DATA_LEN ;length(used for data loop) including ew and crc
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.asg R9.b0, FIFO_BIT_IDX
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.asg R9.b1, BASE_OFFSET
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.asg R9.w2, BISSC_ICSSG_CHx_CFG0
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.asg R10, BISSC_CTRL_FF
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.asg R11.b1, BISSC_CTRL_CRC
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.asg R11.b2, BISSC_CTRL_CMD_RES
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.asg R11.b3, BISSC_CTRL_OTF_CRC
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.asg R12.b0, BISSC_CMD_BIT_PTR
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.asg R12.b1, BISSC_CTRL_CYCLE_CNTR
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.asg R12.b2, BISSC_ENABLE_CHx_IN_USE
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.asg R12.b3, ENCODER_OFFSET
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.asg R13, RAW_DATA1_0 ;Includes Position data, ew and CRC
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.asg R14, RAW_DATA2_0
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.asg R15, RAW_DATA1_1 ;Includes Position data, ew and CRC
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.asg R16, RAW_DATA2_1
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.asg R17, RAW_DATA1_2 ;Includes Position data, ew and CRC
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.asg R18, RAW_DATA2_2
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.asg R19, BISSC_CDS_BACKUP
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.asg R20, BISSC_FLAGS_REG
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.asg R21, BISSC_CTRL_CMD
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.asg R22, DAISY_CHAIN
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.asg R23.b0, LS_SYNC_STATE
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.asg R23.b1, PRIMARY_CORE
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.asg R23.b2, STATUS_REG1
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.asg R23.b3, STATUS_REG2
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.asg R24, SCRATCH
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.asg R25, SCRATCH1
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.asg R26, SCRATCH2
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.asg R27, SCRATCH3
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.asg R29, LINK_REG
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BISSC_RX_CRCBITS .set 6 ;Pos data CRC len
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BISSC_SB_CDS_LEN .set 2 ;Start bit + CDS bit len
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BISSC_EW_LEN .set 2 ;Error warning len
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; Time units below in nano sec
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BISSC_MAX_TBISS_TIMEOUT .set 40000 ;max biss timeout
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BISSC_MIN_TBISS_TIMEOUT .set 12500 ;min biss timeout
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BISSC_TLINEDELAY .set 40000 ;max Line delay
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BISSC_BUSY_TBUSY_S .set 40000 ;max processing time for single cycle data
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BISSC_BUSY_TbUSY_R .set 20000000 ;max processing time for register access
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BISSC_CONFIG_CH0 .set 0x1 ;Config Endat channel 0
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BISSC_CONFIG_CH1 .set (0x1 << 1) ;Config Endat channel 1
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BISSC_CONFIG_CH2 .set (0x1 << 2) ;Config Endat channel 2
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BISSC_CH0_RX_VALID_BIT_OFFSET .set 24 ;RX valid bit offset channel 0
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BISSC_CH1_RX_VALID_BIT_OFFSET .set 25 ;RX valid bit offset channel 1
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BISSC_CH2_RX_VALID_BIT_OFFSET .set 26 ;RX valid bit offset channel 2
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BISSC_CH0_VALID_BIT_IDX .set 24 ;RX valid bit index channel 0
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BISSC_CH1_VALID_BIT_IDX .set 25 ;RX valid bit index channel 1
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BISSC_CH2_VALID_BIT_IDX .set 26 ;RX valid bit index channel 2
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BISSC_MAX_FRAME_SIZE .set 256 ;Max frame size for Processing delay measurement
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BISSC_MAX_WAIT_FOR_ENC_DETECT .set 10000 ;Max wait count for encoder detected |