5f968b0bf2
Initial commit for motor control sdk Fixes: PINDSW-5635 Signed-off-by: Naresh A <nareshk@ti.com>
307 lines
11 KiB
C
307 lines
11 KiB
C
/*
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* Copyright (C) 2023 Texas Instruments Incorporated
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdint.h>
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#include <math.h>
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#include <drivers/epwm.h>
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#include "epwm_drv_aux.h"
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#include "epwm_mod.h"
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#include "epwm_dc.h"
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Epwm_Handle epwmInit(
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EPwmCfgPrms_t *pEpwmCfgPrms,
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EPwmObj_t *pEpwmObj
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)
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{
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Epwm_Handle hEpwm; /* EPWM handle */
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uint32_t epwmBaseAddr; /* EPWM base address */
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uint32_t epwmOutChEn; /* EPWM output channel (A/B) enable bit mask */
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uint32_t epwmTbFreq; /* EPWM time base clock */
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uint32_t epwmOutFreq; /* EPWM output frequency */
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uint32_t epwmTbCounterDir; /* EPWM TB counter direction */
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uint32_t epwmPrdVal;
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uint32_t epwmCmpAVal, epwmCmpBVal;
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/* Get configuration parameters */
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epwmBaseAddr = pEpwmCfgPrms->epwmBaseAddr;
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epwmOutChEn = pEpwmCfgPrms->epwmOutChEn;
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epwmTbFreq = pEpwmCfgPrms->epwmTbFreq;
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epwmOutFreq = pEpwmCfgPrms->epwmOutFreq;
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epwmTbCounterDir = pEpwmCfgPrms->epwmTbCounterDir;
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/* Configure Time Base submodule */
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writeTbClkDiv(epwmBaseAddr, pEpwmCfgPrms->hspClkDiv, pEpwmCfgPrms->clkDiv);
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tbPwmFreqCfg(epwmBaseAddr, epwmTbFreq, epwmOutFreq,
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epwmTbCounterDir, EPWM_SHADOW_REG_CTRL_ENABLE, &epwmPrdVal);
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/* Configure TB Sync In Mode */
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if (pEpwmCfgPrms->cfgTbSyncIn == FALSE) {
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EPWM_tbSyncDisable(epwmBaseAddr);
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}
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else {
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EPWM_tbSyncEnable(epwmBaseAddr, pEpwmCfgPrms->tbPhsValue, pEpwmCfgPrms->tbSyncInCounterDir);
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}
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/* Configure TB Sync Out Mode */
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if (pEpwmCfgPrms->cfgTbSyncOut == FALSE) {
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EPWM_tbSetSyncOutMode(epwmBaseAddr, EPWM_TB_SYNC_OUT_EVT_DISABLE );
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}
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else {
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EPWM_tbSetSyncOutMode(epwmBaseAddr, pEpwmCfgPrms->tbSyncOutMode);
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}
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/* Configure emulation mode */
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EPWM_tbSetEmulationMode(epwmBaseAddr, EPWM_TB_EMU_MODE_FREE_RUN);
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if ((epwmOutChEn >> 0) & 0x1) {
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/*
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* COMPA value - this determines the duty cycle
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* COMPA = (PRD - ((dutycycle * PRD) / 100)
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*/
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epwmCmpAVal = (epwmPrdVal - ((pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_A] * epwmPrdVal) / 100U));
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//epwmCmpAVal = 1; // FL: force max duty cycle just before 100% DC to see where EPWM period occurs
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/* Configure counter compare submodule */
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EPWM_counterComparatorCfg(epwmBaseAddr, EPWM_CC_CMP_A,
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epwmCmpAVal, EPWM_SHADOW_REG_CTRL_ENABLE,
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EPWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO, TRUE);
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/* Configure Action Qualifier Submodule */
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EPWM_aqActionOnOutputCfg(epwmBaseAddr, EPWM_OUTPUT_CH_A,
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&pEpwmCfgPrms->aqCfg[EPWM_OUTPUT_CH_A]);
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}
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if ((epwmOutChEn >> 1) & 0x1) {
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/*
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* COMPB value - this determines the duty cycle
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* COMPB = (PRD - ((dutycycle * PRD) / 100)
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*/
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epwmCmpBVal = (epwmPrdVal - ((pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_B] * epwmPrdVal) / 100U));
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/* Configure counter compare submodule */
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EPWM_counterComparatorCfg(epwmBaseAddr, EPWM_CC_CMP_B,
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epwmCmpBVal, EPWM_SHADOW_REG_CTRL_ENABLE,
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EPWM_CC_CMP_LOAD_MODE_CNT_EQ_ZERO, TRUE);
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/* Configure Action Qualifier Submodule */
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EPWM_aqActionOnOutputCfg(epwmBaseAddr, EPWM_OUTPUT_CH_B,
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&pEpwmCfgPrms->aqCfg[EPWM_OUTPUT_CH_B]);
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}
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if (pEpwmCfgPrms->cfgDb == TRUE) {
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/* Configure Dead Band Submodule */
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EPWM_deadbandCfg(epwmBaseAddr, &pEpwmCfgPrms->dbCfg);
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}
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else {
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/* Configure Dead Band Submodule */
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EPWM_deadbandBypass(epwmBaseAddr);
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}
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/* Configure Chopper Submodule */
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EPWM_chopperEnable(epwmBaseAddr, FALSE);
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/* Configure trip zone Submodule */
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EPWM_tzTripEventDisable(epwmBaseAddr, EPWM_TZ_EVENT_ONE_SHOT, 0U);
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EPWM_tzTripEventDisable(epwmBaseAddr, EPWM_TZ_EVENT_CYCLE_BY_CYCLE, 0U);
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if (pEpwmCfgPrms->cfgEt == TRUE) {
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/* Configure event trigger Submodule */
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EPWM_etIntrCfg(epwmBaseAddr, pEpwmCfgPrms->intSel,
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pEpwmCfgPrms->intPrd);
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EPWM_etIntrEnable(epwmBaseAddr);
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}
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/* Init PWM object */
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hEpwm = (Epwm_Handle)pEpwmObj;
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hEpwm->epwmId = pEpwmCfgPrms->epwmId;
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hEpwm->epwmBaseAddr = pEpwmCfgPrms->epwmBaseAddr;
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hEpwm->epwmOutChEn = pEpwmCfgPrms->epwmOutChEn;
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hEpwm->hspClkDiv = pEpwmCfgPrms->hspClkDiv;
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hEpwm->clkDiv = pEpwmCfgPrms->clkDiv;
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hEpwm->epwmTbFreq = pEpwmCfgPrms->epwmTbFreq;
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hEpwm->epwmOutFreq = pEpwmCfgPrms->epwmOutFreq;
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hEpwm->epwmPrdVal = epwmPrdVal;
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hEpwm->toggleEpwmPrd = FALSE;
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hEpwm->toggleEpwmPrdState = 0;
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hEpwm->epwmPrdValL = 0;
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hEpwm->epwmPrdValU = 0;
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if ((epwmOutChEn >> 0) & 0x1) {
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hEpwm->epwmDutyCycle[EPWM_OUTPUT_CH_A] = pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_A];
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hEpwm->cmpAVal = epwmCmpAVal;
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hEpwm->cmpANzToZ = FALSE;
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hEpwm->cmpAZToNz = FALSE;
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}
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if ((epwmOutChEn >> 1) & 0x1) {
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hEpwm->epwmDutyCycle[EPWM_OUTPUT_CH_B] = pEpwmCfgPrms->epwmDutyCycle[EPWM_OUTPUT_CH_B];
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hEpwm->cmpBVal = epwmCmpBVal;
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hEpwm->cmpBNzToZ = FALSE;
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hEpwm->cmpBZToNz = FALSE;
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}
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return hEpwm;
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}
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/* Update EPWM period */
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int32_t epwmUpdatePrd(
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Epwm_Handle hEpwm,
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uint32_t epwmOutFreqSet
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)
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{
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float epwmPrdVal_f;
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uint32_t epwmPrdVal;
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uint32_t rem;
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/* Check for EPWM period toggle */
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if (hEpwm->toggleEpwmPrd == TRUE) {
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hEpwm->epwmPrdVal = (hEpwm->toggleEpwmPrdState == 0) ? hEpwm->epwmPrdValL : hEpwm->epwmPrdValU;
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hEpwm->toggleEpwmPrdState ^= 0x1;
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/* Write next period count */
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writeTbPrd(hEpwm->epwmBaseAddr, hEpwm->epwmPrdVal);
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}
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/* Check for PWM frequency change */
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if (hEpwm->epwmOutFreq != epwmOutFreqSet) {
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epwmPrdVal_f = (float)hEpwm->epwmTbFreq / epwmOutFreqSet;
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epwmPrdVal_f = roundf(epwmPrdVal_f);
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epwmPrdVal = (uint32_t)epwmPrdVal_f;
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rem = epwmPrdVal - epwmPrdVal/2*2;
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if (rem == 0) {
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/* Period is divisible by 2,
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alternating period not employed */
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hEpwm->toggleEpwmPrd = FALSE;
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hEpwm->toggleEpwmPrdState = 0;
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hEpwm->epwmPrdValL = 0;
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hEpwm->epwmPrdValU = 0;
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hEpwm->epwmPrdVal = epwmPrdVal/2;
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} else {
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/* Period is not divisible by 2,
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alternating period employed to provide correct average EPWM frequency:
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EPWM period 2*n : TBPRD <- 'Lower' period
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EPWM period 2*n+1 : TBPRD <- 'Upper' period
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*/
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hEpwm->toggleEpwmPrd = TRUE;
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hEpwm->toggleEpwmPrdState = 1;
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hEpwm->epwmPrdValL = epwmPrdVal/2;
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hEpwm->epwmPrdValU = epwmPrdVal/2+1;
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hEpwm->epwmPrdVal = hEpwm->epwmPrdValL;
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}
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/* Write next period count */
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writeTbPrd(hEpwm->epwmBaseAddr, hEpwm->epwmPrdVal);
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hEpwm->epwmOutFreq = epwmOutFreqSet;
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}
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return EPWM_DC_SOK;
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}
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/* Update EPWM A/B outputs */
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int32_t epwmUpdateOut(
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Epwm_Handle hEpwm,
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float VrefA,
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float VrefB
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)
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{
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float dcVal; /* EPWM duty cycle value */
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uint16_t cmpVal; /* EPWM CMP value */
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if ((hEpwm->epwmOutChEn >> 0) & 0x1) {
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/* Compute next Duty Cycle and CMP values */
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computeCmpx(VrefA, hEpwm->epwmPrdVal, &dcVal, &cmpVal);
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/* Write next CMPA value */
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writeCmpA(hEpwm->epwmBaseAddr, cmpVal);
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/* EPWM 100% Duty Cycle */
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/* Handle transition to 100% Duty Cycle */
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if (hEpwm->cmpANzToZ == TRUE) {
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/* restore original AQ */
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cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING);
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hEpwm->cmpANzToZ = FALSE;
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}
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if ((hEpwm->cmpAVal != 0) && (cmpVal == 0)) {
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/* set AQ to set for next period */
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cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_HIGH);
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hEpwm->cmpANzToZ = TRUE;
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}
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/* Handle transition from 100% Duty Cycle */
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if (hEpwm->cmpAZToNz == TRUE) {
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/* restore original AQ */
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cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING);
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hEpwm->cmpAZToNz = FALSE;
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}
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if ((hEpwm->cmpAVal == 0) && (cmpVal != 0)) {
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/* set AQ to clear for next period */
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cfgOutChAAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_LOW);
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hEpwm->cmpAZToNz = TRUE;
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}
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hEpwm->cmpAVal = cmpVal;
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}
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if ((hEpwm->epwmOutChEn >> 1) & 0x1) {
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/* Compute next Duty Cycle and CMP values */
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computeCmpx(VrefB, hEpwm->epwmPrdVal, &dcVal, &cmpVal);
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/* Write next CMPB value */
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writeCmpB(hEpwm->epwmBaseAddr, cmpVal);
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/* EPWM 100% Duty Cycle */
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/* Handle transition to 100% Duty Cycle */
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if (hEpwm->cmpBNzToZ == TRUE) {
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/* restore original AQ */
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cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING);
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hEpwm->cmpBNzToZ = FALSE;
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}
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if ((hEpwm->cmpBVal != 0) && (cmpVal == 0)) {
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/* set AQ to set for next period */
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cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_HIGH);
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hEpwm->cmpBNzToZ = TRUE;
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}
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/* Handle transition from 100% Duty Cycle */
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if (hEpwm->cmpBZToNz == TRUE) {
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/* restore original AQ */
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cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_DONOTHING);
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hEpwm->cmpBZToNz = FALSE;
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}
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if ((hEpwm->cmpBVal == 0) && (cmpVal != 0)) {
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/* set AQ to clear for next period */
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cfgOutChBAqZero(hEpwm->epwmBaseAddr, EPWM_AQ_ACTION_LOW);
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hEpwm->cmpBZToNz = TRUE;
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}
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hEpwm->cmpBVal = cmpVal;
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}
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return EPWM_DC_SOK;
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}
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