c71267b7fc
- For the tidep_01032_dual_motor_drive reference design, ICSSG0 core clock should be configured to 300 MHz and ICSSG1 core clock should be configured to 200 MHz. R5F_0_0 configures ICSSG0 first and then R5F_1_0 configures ICSSG1. - Because of MCUSDK-12117 bug, ICSSG1 clock configuration to 200 MHz causes ICSSG0 also to run at 200 MHz which is a problem for EnDat and SDFM firmwares. - To avoid this issue, the clock configuration of ICSSG1 should be done separately and not from SysConfig generated API. Fixes: PINDSW-7166 Signed-off-by: Dhaval Khandla <dhavaljk@ti.com> |
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| .. | ||
| current_sense | ||
| dcl | ||
| position_sense | ||
| pruicss_pwm | ||
| tidep_01032_dual_motor_drive/single_chip_servo | ||
| transforms/transforms_test | ||