c41804bd2e
- Add support for trigger based sampling by using IEP compare events - Add support for double update per PWM cycle - Fixed the IEP compare event hit value calculation - Tested with SDFM clock input from EPWM Fixes: PINDSW-5522, PINDSW-6544, PINDSW-6546 Signed-off-by: Achala Ram <a-ram@ti.com>
95 lines
4.6 KiB
Batchfile
95 lines
4.6 KiB
Batchfile
/****************************************************************************/
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/* ICSSG_PRU.cmd */
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/* Copyright (c) 2023 Texas Instruments Incorporated */
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/* */
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/* Description: This file is a linker command file that can be used for */
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/* linking PRU programs built with the C compiler and */
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/* the resulting .out file on an pru device. */
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/****************************************************************************/
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/* -cr */ /* Link using C conventions */
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/* -stack 0x100 */
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/* Specify the System Memory Map */
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MEMORY
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{
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PAGE 0:
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PRU_IMEM : org = 0x00000000 len = 0x00004000 /* 16kB ICSSG_PRU Instruction RAM */
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PAGE 1:
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/* RAM */
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PRU_FWREGS : org = 0x00000000 len = 0x00000080
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RTU_FWREGS : org = 0x00000080 len = 0x00000080
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PRU_DMEM_0_1_LOW : org = 0x00000200 len = 0x00000E00 /* 4kB ICSSG Data RAM 0_1 for PRU*/
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PRU_DMEM_0_1_HIGH : org = 0x00001000 len = 0x00001000 /* 4kB ICSSG Data RAM 0_1 for RTU*/
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PRU_DMEM_1_0 : org = 0x00002000 len = 0x00002000 /* 8kB ICSSG Data RAM 1_0 */
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PAGE 2:
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PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000 CREGISTER=28 /* 64kB Shared RAM */
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/* Peripherals */
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PRU_CFG : org = 0x00026000 len = 0x00000120 CREGISTER=4
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RSVD0 : org = 0x00020000 len = 0x00001504 CREGISTER=0
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RSVD1 : org = 0x48040000 len = 0x0000005C CREGISTER=1
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RSVD2 : org = 0x4802A000 len = 0x000000D8 CREGISTER=2
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RSVD3 : org = 0x00030000 len = 0x00000060 CREGISTER=3
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RSVD5 : org = 0x48060000 len = 0x00000300 CREGISTER=5
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RSVD6 : org = 0x48030000 len = 0x000001A4 CREGISTER=6
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RSVD7 : org = 0x00028000 len = 0x00000038 CREGISTER=7
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RSVD8 : org = 0x46000000 len = 0x00000100 CREGISTER=8
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RSVD9 : org = 0x4A100000 len = 0x0000128C CREGISTER=9
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RSVD10 : org = 0x48318000 len = 0x00000100 CREGISTER=10
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RSVD11 : org = 0x48022000 len = 0x00000088 CREGISTER=11
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RSVD12 : org = 0x48024000 len = 0x00000088 CREGISTER=12
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RSVD13 : org = 0x48310000 len = 0x00000100 CREGISTER=13
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RSVD14 : org = 0x481CC000 len = 0x000001E8 CREGISTER=14
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RSVD15 : org = 0x481D0000 len = 0x000001E8 CREGISTER=15
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RSVD16 : org = 0x481A0000 len = 0x000001A4 CREGISTER=16
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RSVD17 : org = 0x4819C000 len = 0x000000D8 CREGISTER=17
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RSVD18 : org = 0x48300000 len = 0x000002C4 CREGISTER=18
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RSVD19 : org = 0x48302000 len = 0x000002C4 CREGISTER=19
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RSVD20 : org = 0x48304000 len = 0x000002C4 CREGISTER=20
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RSVD21 : org = 0x00032400 len = 0x00000100 CREGISTER=21
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RSVD22 : org = 0x480C8000 len = 0x00000140 CREGISTER=22
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RSVD23 : org = 0x480CA000 len = 0x00000880 CREGISTER=23
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RSVD26 : org = 0x0002E000 len = 0x0000031C CREGISTER=26
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RSVD27 : org = 0x00032000 len = 0x00000100 CREGISTER=27
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RSVD29 : org = 0x49000000 len = 0x00001098 CREGISTER=29
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}
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/* Specify the sections allocation into memory */
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SECTIONS {
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/* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading
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an ELF file, but useful when loading a binary */
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/* .text:_c_int00* > 0x0, PAGE 0 */
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/* .text > PRU_IMEM, PAGE 0 */
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/* .stack > PRU_DMEM_0_1_LOW, PAGE 1 */
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/* .bss > PRU_DMEM_0_1_LOW, PAGE 1 */
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/* .cio > PRU_DMEM_0_1_LOW, PAGE 1 */
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/* .data > PRU_DMEM_0_1_LOW, PAGE 1 */
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/* .switch > PRU_DMEM_0_1_LOW, PAGE 1 */
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/* .sysmem > PRU_DMEM_0_1_LOW, PAGE 1 */
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/* .cinit > PRU_DMEM_0_1_LOW, PAGE 1 */
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/* .rodata > PRU_DMEM_0_1_LOW, PAGE 1 */
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/* .rofardata > PRU_DMEM_0_1_LOW, PAGE 1 */
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/* .farbss > PRU_DMEM_0_1_LOW, PAGE 1 */
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/* .fardata > PRU_DMEM_0_1_LOW, PAGE 1 */
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.text > PRU_IMEM, PAGE 0
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#if defined (SDFM_PRU_CORE)
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.fwRegs > PRU_FWREGS, PAGE 1
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.data > PRU_DMEM_0_1_LOW, PAGE 1
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.outSamps > PRU_DMEM_0_1_LOW, PAGE 1
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#else
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.fwRegs > RTU_FWREGS , PAGE 1
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.data > PRU_DMEM_0_1_HIGH, PAGE 1
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.outSamps > PRU_DMEM_0_1_HIGH, PAGE 1
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#endif
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.dbgBuf > PRU_SHAREDMEM, PAGE 2
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}
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