379 lines
14 KiB
C
379 lines
14 KiB
C
/*
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* Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <drivers/hw_include/tistdtypes.h>
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#include <drivers/hw_include/hw_types.h>
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#include <current_sense/sdfm/include/sdfm_drv.h>
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#include <current_sense/sdfm/include/sdfm_api.h>
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#include <current_sense/sdfm/firmware/icssg_sdfm.h>
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#include <drivers/hw_include/am64x_am243x/cslr_soc_baseaddress.h>
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#include <drivers/soc.h>
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#include <drivers/gpio.h>
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#include <kernel/dpl/AddrTranslateP.h>
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/* Internal structure for managing each PRU SD */
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SDFM g_sdfm[NUM_PRU] = {
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{PRU_ID_0,0,0,0,0, NULL},
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{PRU_ID_1,0,0,0,0, NULL},
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};
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/* Initialize SDFM instance */
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sdfm_handle SDFM_init(uint8_t pru_id, uint8_t coreId)
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{
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SDFM *p_sdfm;
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if (pru_id == PRU_ID_0)
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{
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/* Initialize PRU 0 SD */
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p_sdfm = &g_sdfm[pru_id];
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/* Initialize SDFM control address */
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if(coreId == PRUICSS_RTU_PRU0)
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{
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p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM0_SLV_RAM + RTUx_DMEM_BASE_ADD);
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}
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else if (coreId == PRUICSS_PRU0)
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{
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p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM0_SLV_RAM + PRUx_DMEM_BASE_ADD);
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}
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else if (coreId == PRUICSS_TX_PRU0)
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{
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p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM0_SLV_RAM + TXPRUx_DMEM_BASE_ADD);
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}
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else
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{
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p_sdfm->p_sdfm_interface = NULL;
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}
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/* Set FW PRU ID */
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p_sdfm->p_sdfm_interface->sdfm_ctrl.sdfm_pru_id = pru_id;
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}
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else if (pru_id == PRU_ID_1)
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{
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/* Initialize PRU 1 SD */
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p_sdfm = &g_sdfm[pru_id];
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/* Initialize SDFM control address */
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if(coreId == PRUICSS_RTU_PRU1)
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{
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p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM1_SLV_RAM + RTUx_DMEM_BASE_ADD);
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}
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else if (coreId == PRUICSS_PRU1)
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{
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p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM1_SLV_RAM + PRUx_DMEM_BASE_ADD);
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}
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else if (coreId == PRUICSS_TX_PRU1)
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{
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p_sdfm->p_sdfm_interface = (SDFM_Interface *)(PRU_ICSSG_DRAM1_SLV_RAM + TXPRUx_DMEM_BASE_ADD);
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}
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else
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{
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p_sdfm->p_sdfm_interface = NULL;
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}
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/* Set FW PRU ID */
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p_sdfm->p_sdfm_interface->sdfm_ctrl.sdfm_pru_id = pru_id;
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}
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else
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{
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p_sdfm = NULL;
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}
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return (sdfm_handle)p_sdfm;
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}
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/*Configuration of iep & pwm time period */
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void SDFM_configIepCount(sdfm_handle h_sdfm, uint32_t epwm_out_freq)
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{
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/*; IEP0 default increment=1*/
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h_sdfm->p_sdfm_interface->sdfm_cfg_iep_ptr.iep_inc_value = h_sdfm->iep_inc;
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/*
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IEP0 CMP0 count to simulate EPWM (FOC loop) period:
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- IEP frequency = 300 MHz
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- IEP Default Increment = 1
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- Simulated EPWM frequency = 8e3
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CMP0 = 300e6/1/8e3 = 37500 = 0x927C
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*/
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uint32_t cnt_epwm_prd = h_sdfm->iep_clock/epwm_out_freq;
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h_sdfm->p_sdfm_interface->sdfm_cfg_iep_ptr.cnt_epwm_prd = cnt_epwm_prd;
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}
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/*ecap configuration for SD clock*/
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void SDFM_configEcap(sdfm_handle h_sdfm, uint8_t ecap_divider)
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{
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/* SD_PRD_CLOCKS divider = 15; SDFM_CLOCK = IEP freq./SD_PRD_CLOCKS; 300/15 => 20 MHz, SD_CLK_INV==0 => No clock inversion*/
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h_sdfm->p_sdfm_interface->sd_clk.sd_prd_clocks = ecap_divider;
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h_sdfm->p_sdfm_interface->sd_clk.sd_clk_inv = 0;
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}
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/*sdfm Hw osr configuration */
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void SDFM_setCompFilterOverSamplingRatio(sdfm_handle h_sdfm, uint8_t ch_id, uint16_t osr)
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{
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/*Over current OSR*/
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].osr = osr;
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}
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/*sdfm high, low threshold config */
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void SDFM_setCompFilterThresholds(sdfm_handle h_sdfm, uint8_t ch_id, SDFM_ThresholdParms thresholdParms)
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{
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/* SD Over current high threshold = (Over current OSR)^(Over current SINC ORDER) = 14^3 = 2744*/
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].sdfm_threshold_parms.high_threshold = thresholdParms.high_threshold;
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/* SD Over current low threshold */
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].sdfm_threshold_parms.low_threshold = thresholdParms.low_threshold;
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}
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/*sdfm smapling time configuation */
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void SDFM_setSampleTriggerTime(sdfm_handle h_sdfm, float samp_trig_time)
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{ /*convert sample time into IEP count*/
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/*samp time in us */
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int32_t count = (h_sdfm->iep_clock /1000000)*((float)samp_trig_time);
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h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.first_samp_trig_time = count;
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}
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/*Second normal current sampling configuration*/
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void SDFM_enableDoubleSampling(sdfm_handle h_sdfm, float samp_trig_time)
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{
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/*Enable double normal current sampling*/
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h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.en_double_nc_sampling = 1;
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/*Second sample point*/
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int32_t count = (h_sdfm->iep_clock /1000000)*((float)samp_trig_time);
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h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.second_samp_trig_time = count;
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}
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/*Disable Double update*/
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void SDFM_disableDoubleSampling(sdfm_handle h_sdfm)
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{
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/*Enable double normal current sampling*/
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h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.en_double_nc_sampling = 0;
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}
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/* Enable the channel specified by the channel number parameter*/
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void SDFM_setEnableChannel(sdfm_handle h_sdfm, uint8_t channel_number)
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{
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uint32_t temp;
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temp = 1<< channel_number;
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if(temp & SDFM_CH_MASK_FOR_CH0_CH3_CH6)
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{
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h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.sdfm_ch_id |= (channel_number << SDFM_CFG_BF_SD_CH0_ID_SHIFT);
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[0].ch_id = channel_number;
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}
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else if(temp & SDFM_CH_MASK_FOR_CH1_CH4_CH7)
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{
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h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.sdfm_ch_id |= (channel_number<< SDFM_CFG_BF_SD_CH1_ID_SHIFT);
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[1].ch_id = channel_number;
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}
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else
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{
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h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.sdfm_ch_id |= (channel_number << SDFM_CFG_BF_SD_CH2_ID_SHIFT);
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[2].ch_id = channel_number;
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}
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}
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/* set SDFM channel acc source */
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void SDFM_configDataFilter(sdfm_handle h_sdfm, uint8_t ch_id, uint8_t filter)
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{
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].filter_type = filter;
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}
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/*set clock source & clock inversion for SDFM channel*/
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void SDFM_selectClockSource(sdfm_handle h_sdfm, uint8_t ch_id, SDFM_ClkSourceParms clkPrams)
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{
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].sdfm_clk_parms.clk_source = clkPrams.clk_source;
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch_id].sdfm_clk_parms.clk_inv = clkPrams.clk_inv;
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}
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/* Enable the comparator feature for a specified filter/channel */
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void SDFM_enableComparator(sdfm_handle h_sdfm, uint8_t ch)
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{
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/*It is setting bits for enable Over current: 0th bit for Over current enable & from 1st bits to 3rd bits are for ch0 to ch2.*/
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h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.enable_comparator |= ((1 << (ch+1))|(1));
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}
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/* Disable the comparator feature for a specified filter/channel */
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void SDFM_disableComparator(sdfm_handle h_sdfm, uint8_t ch)
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{
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h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.enable_comparator &= (0xFFFF ^ (1<<ch));
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}
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/*GPIO configuration*/
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void SDFM_configComparatorGpioPins(sdfm_handle h_sdfm, uint8_t ch,uint32_t gpio_base_addr, uint32_t pin_number, uint32_t threshold_type)
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{
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volatile CSL_GpioRegs* hGpio = (volatile CSL_GpioRegs*)((uintptr_t) gpio_base_addr);
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uint32_t reg_index = GPIO_GET_REG_INDEX(pin_number);
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uint32_t reg_val = GPIO_GET_BIT_MASK(pin_number);
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uint32_t clr_data_addr = (uint32_t)&hGpio->BANK_REGISTERS[reg_index].CLR_DATA;
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uint32_t set_data_addr = (uint32_t)&hGpio->BANK_REGISTERS[reg_index].SET_DATA;
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].sdfm_gpio_params[threshold_type].write_val = reg_val;
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].sdfm_gpio_params[threshold_type].set_val_addr = set_data_addr;
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].sdfm_gpio_params[threshold_type].clr_val_addr = clr_data_addr;
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}
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/* Get current (or latest) sample for the specified channel */
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uint32_t SDFM_getFilterData(sdfm_handle h_sdfm, uint8_t ch)
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{
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return h_sdfm->sampleOutputInterface->sampleOutput[ch];
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}
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/*Configure normal current OSR for data filter*/
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void SDFM_setFilterOverSamplingRatio(sdfm_handle h_sdfm, uint16_t nc_osr)
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{
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/*IEP0 counts in normal current sampling period*/
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uint16_t count;
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uint32_t iep_freq = h_sdfm->iep_clock;
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uint32_t sd_clock = h_sdfm->sdfm_clock;
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count = (int)((float)nc_osr*((float)iep_freq/(float)sd_clock));
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h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.nc_prd_iep_cnt = count;
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}
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/*return firmware version */
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uint64_t SDFM_getFirmwareVersion(sdfm_handle h_sdfm)
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{
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return h_sdfm->p_sdfm_interface->firmwareVersion;
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}
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/*Enable free run NC */
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void SDFM_enableContinuousNormalCurrent(sdfm_handle h_sdfm)
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{
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h_sdfm->p_sdfm_interface->sdfm_cfg_trigger.en_continuous_mode = 1;
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}
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/*FD block confiuration */
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void SDFM_configFastDetect(sdfm_handle h_sdfm, uint8_t ch, uint8_t *fdParms)
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{
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h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.enFastDetect |= 1<<ch;
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].fd_window = fdParms[0];
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].fd_zero_max = fdParms[1];
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].fd_zero_min = fdParms[2];
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/*Configure one max to window size + 1 and one min to 0, so they never get set*/
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].fd_one_max = (fdParms[0] + 1) * 4 + 1;
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h_sdfm->p_sdfm_interface->sdfm_cfg_ptr[ch].fd_one_min = 0;
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}
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/*return status of Trip status bit*/
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uint32_t SDFM_getPwmTripStatus(sdfm_handle h_sdfm, uint8_t pwmIns)
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{
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void *pruss_cfg = h_sdfm->pruss_cfg;
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uint32_t regval;
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regval = HW_RD_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_PWM0 + pwmIns * 4);
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regval = regval & CSL_ICSSCFG_PWM0_PWM0_TRIP_S_MASK;
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return regval>>CSL_ICSSCFG_PWM0_PWM0_TRIP_S_SHIFT;
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}
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/*Clear Trip status bit*/
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void SDFM_clearPwmTripStatus(sdfm_handle h_sdfm, uint8_t pwmIns)
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{
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void *pruss_cfg = h_sdfm->pruss_cfg;
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uint32_t regval;
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regval = HW_RD_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_PWM0 + pwmIns * 4);
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regval = regval | CSL_ICSSCFG_PWM0_PWM0_TRIP_RESET_MASK;
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HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_PWM0 + pwmIns * 4, regval);
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regval = HW_RD_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_PWM0 + pwmIns * 4);
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regval = regval & (~ CSL_ICSSCFG_PWM0_PWM0_TRIP_RESET_MASK);
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HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_PWM0 + pwmIns * 4, regval);
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}
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/*Enable Load share mode*/
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void SDFM_enableLoadShareMode(sdfm_handle h_sdfm, uint8_t sliceId)
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{
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void *pruss_cfg = h_sdfm->pruss_cfg;
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uint32_t rgval;
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if(sliceId)
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{
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rgval = HW_RD_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_SDPRU1CLKDIV);
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rgval |= CSL_ICSSCFG_SDPRU1CLKDIV_PRU1_SD_SHARE_EN_MASK;
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HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_SDPRU1CLKDIV, rgval);
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}
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else
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{
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rgval = HW_RD_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_SDPRU0CLKDIV);
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rgval |= CSL_ICSSCFG_SDPRU0CLKDIV_PRU0_SD_SHARE_EN_MASK;
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HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_SDPRU0CLKDIV, rgval);
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}
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}
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/*Measure Phase delay*/
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float SDFM_measureClockPhaseDelay(sdfm_handle h_sdfm, uint16_t clkEdg)
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{
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/*enable phase delay measurement*/
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h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.en_phase_delay = 1;
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/*waiting till measurment done */
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uint8_t ack = h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.en_phase_delay & SDFM_PHASE_DELAY_ACK_BIT_MASK;
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while(ack)
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{
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ack = h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.en_phase_delay & SDFM_PHASE_DELAY_ACK_BIT_MASK ;
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}
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uint16_t nEdge = h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_edge;
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float temp = h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_phase_delay;
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/*avg*/
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temp = temp/SDFM_PHASE_DELAY_CAL_LOOP_SIZE;
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/*check data reading edge(clk polarity) & nearest edge */
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if(nEdge == clkEdg)
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{
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/*PRU cycles for half SD clock period*/
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uint32_t pruCycles = ceil(((float)h_sdfm->pru_core_clk)/(2*h_sdfm->sdfm_clock));
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h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_phase_delay = pruCycles - temp;
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}
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else
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{
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/*PRU cycles for one SD clock period*/
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uint32_t pruCycles = ceil((float)(h_sdfm->pru_core_clk/(h_sdfm->sdfm_clock)));
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h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_phase_delay = pruCycles - temp;
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}
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/*conversion from PRU cycle to ns */
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float phaseDelay = ((float)h_sdfm->p_sdfm_interface->sdfm_ch_ctrl.clock_phase_delay * 1000000000)/h_sdfm->pru_core_clk;
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return phaseDelay;
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}
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/* SDFM global enable */
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void SDFM_enable(sdfm_handle h_sdfm)
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{
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uint8_t sdfm_en_ack;
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/*Enable SDFM */
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h_sdfm->p_sdfm_interface->sdfm_ctrl.sdfm_en = 1;
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/* wait for ACK */
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do {
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sdfm_en_ack = h_sdfm->p_sdfm_interface->sdfm_ctrl.sdfm_en_ack;
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} while (sdfm_en_ack != BF_SDFM_EN_ENABLE);
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}
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