5f968b0bf2
Initial commit for motor control sdk Fixes: PINDSW-5635 Signed-off-by: Naresh A <nareshk@ti.com>
88 lines
3.6 KiB
Plaintext
88 lines
3.6 KiB
Plaintext
/*
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* AM64x_TX_PRU0.cmd
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*
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* Example Linker command file for linking programs built with the TI-PRU-CGT
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* on AM64x TX_PRU0 cores
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*
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* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Specify the System Memory Map */
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MEMORY
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{
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PAGE 0:
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/* 6 KB PRU Instruction RAM */
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TX_PRU_IMEM : org = 0x00000000 len = 0x00001800
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PAGE 1:
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/* Data RAMs */
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/* 8 KB PRU Data RAM 0; use only the first 4 KB for PRU0 and reserve
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* the second 4 KB for RTU0 and Tx_PRU0 */
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PRU0_DMEM_0 : org = 0x00000000 len = 0x00001000
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/* 8 KB PRU Data RAM 1; reserved completely for Slice1 cores - PRU1,
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* RTU1 and Tx_PRU1; do not use for any Slice0 cores */
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PRU0_DMEM_1 : org = 0x00002000 len = 0x00001000
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/* NOTE: Custom split of the second 4 KB of ICSS Data RAMs 0 and 1
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* split equally between the corresponding RTU and Tx_PRU cores in
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* each slice */
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RTU_PRU0_DMEM_0 : org = 0x00001000 len = 0x00000800
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TX_PRU0_DMEM_0 : org = 0x00001800 len = 0x00000800
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RTU_PRU0_DMEM_1 : org = 0x00003000 len = 0x00000800
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TX_PRU0_DMEM_1 : org = 0x00003800 len = 0x00000800
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PAGE 2:
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/* C28 needs to be programmed to point to SHAREDMEM, default is 0 */
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/* 64 KB PRU Shared RAM */
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PRU_SHAREDMEM : org = 0x00010000 len = 0x00010000
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}
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/* Specify the sections allocation into memory */
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SECTIONS {
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/* Forces _c_int00 to the start of PRU IRAM. Not necessary when loading
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an ELF file, but useful when loading a binary */
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.text:_c_int00* > 0x0, PAGE 0
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.text > TX_PRU_IMEM, PAGE 0
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.stack > TX_PRU_IMEM, PAGE 0
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.bss > TX_PRU0_DMEM_0, PAGE 1
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/*
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.cio > TX_PRU0_DMEM_0, PAGE 1
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.data > TX_PRU0_DMEM_0, PAGE 1
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.switch > TX_PRU0_DMEM_0, PAGE 1
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.sysmem > TX_PRU0_DMEM_0, PAGE 1
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.cinit > TX_PRU0_DMEM_0, PAGE 1
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.rodata > TX_PRU0_DMEM_0, PAGE 1
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.rofardata > TX_PRU0_DMEM_0, PAGE 1
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.farbss > TX_PRU0_DMEM_0, PAGE 1
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.fardata > TX_PRU0_DMEM_0, PAGE 1
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*/
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}
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