c41804bd2e
- Add support for trigger based sampling by using IEP compare events - Add support for double update per PWM cycle - Fixed the IEP compare event hit value calculation - Tested with SDFM clock input from EPWM Fixes: PINDSW-5522, PINDSW-6544, PINDSW-6546 Signed-off-by: Achala Ram <a-ram@ti.com>
77 lines
2.7 KiB
C
77 lines
2.7 KiB
C
/*
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* Copyright (C) 2023 Texas Instruments Incorporated
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <drivers/pinmux.h>
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#include "cfg_pad.h"
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static Pinmux_PerCfg_t gPinMuxMainDomainCfgsdfm[] = {
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/* PRG0_ECAP0_IN_APWM_OUT,
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PRG0_PRU1_GPO15, PRG0_ECAP0_IN_APWM_OUT, U5, J2.C11 */
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{
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PIN_PRG0_PRU1_GPO15,
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( PIN_MODE(10) | PIN_PULL_DISABLE )
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},
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/* SD8_CLK,
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PRG0_PRU0_GPI16, SD8_CLK, U4, J2E:P9 */
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{
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PIN_PRG0_PRU0_GPO16,
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( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
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},
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/* SD0_D,
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PRG0_PRU0_GPI1, SD0_D, R4, J2E:P8 */
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{
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PIN_PRG0_PRU0_GPO1,
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( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
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},
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/* SD1_D,
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PRG0_PRU0_GPI3, SD1_D, V2, J2A:P9 */
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{
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PIN_PRG0_PRU0_GPO3,
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( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
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},
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/* SD2_D,
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PRG0_PRU0_GPI5, SD2_D, R3, J2C:P6 */
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{
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PIN_PRG0_PRU0_GPO5,
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( PIN_MODE(1) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
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},
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{PINMUX_END, PINMUX_END}
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};
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/* Configure SOC pads */
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void cfgPad(void)
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{
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Pinmux_config(gPinMuxMainDomainCfgsdfm, PINMUX_DOMAIN_ID_MAIN);
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}
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