2c4dd5bfc0
- Add support for single channel - Add support for multi channel using single PRU - Add support for multi channel using multiple PRUs with load share mode Fixes: PINDSW-5468, PINDSW-5479, PINDSW-5488, PINDSW-5494, PINDSW-5495 Signed-off-by: Dhaval Khandla <dhavaljk@ti.com>
528 lines
20 KiB
C
528 lines
20 KiB
C
/*
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* Copyright (C) 2023 Texas Instruments Incorporated
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <position_sense/bissc/include/bissc_drv.h>
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#include <kernel/dpl/ClockP.h>
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#include <drivers/hw_include/tistdtypes.h>
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#include <drivers/hw_include/hw_types.h>
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static struct bissc_priv bissc_priv;
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void bissc_command_send(struct bissc_priv *priv)
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{
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struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
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if(priv->load_share)
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{
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pruicss_xchg->cycle_trigger[0] = (pruicss_xchg->channel & 0x1)?0x1:0;
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pruicss_xchg->cycle_trigger[1] = (pruicss_xchg->channel & 0x2)?0x1:0;
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pruicss_xchg->cycle_trigger[2] = (pruicss_xchg->channel & 0x4)?0x1:0;
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}
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else
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{
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pruicss_xchg->cycle_trigger[0] = 0x1;
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}
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}
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int32_t bissc_command_wait(struct bissc_priv *priv)
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{
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struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
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uint32_t timeout;
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/*Wait for max of 5 ms*/
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timeout = BISSC_MAX_CYCLE_TIMEOUT;
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while(1)
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{
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if(priv->load_share){
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if((pruicss_xchg->cycle_trigger[0] == 0 ) && (pruicss_xchg->cycle_trigger[1] == 0) && (pruicss_xchg->cycle_trigger[2] == 0)){
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break;
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}
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}
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else if(pruicss_xchg->cycle_trigger[0] == 0)
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{
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break;
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}
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ClockP_usleep(1000);
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timeout--;
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if(timeout == 0)
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{
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return SystemP_FAILURE;
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}
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}
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return SystemP_SUCCESS;
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}
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int32_t bissc_command_process(struct bissc_priv *priv)
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{
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int32_t ret = SystemP_FAILURE;
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bissc_command_send(priv);
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ret = bissc_command_wait(priv);
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return ret;
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}
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int32_t bissc_get_pos_res(struct bissc_priv *priv)
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{
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uint32_t raw_data0, raw_data1, shift, sl_num, max, ch_num, numslaves, ls_ch;
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int32_t ch = 0;
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if(bissc_command_process(priv) < 0)
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{
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return SystemP_FAILURE;
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}
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for(ch_num = 0; ch_num < priv->totalchannels; ch_num++)
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{
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ch = priv->channel[ch_num];
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if(priv->load_share)
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{
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numslaves = priv->num_slaves[ch];
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ls_ch = ch;
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}
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else
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{
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numslaves = priv->num_slaves[0];
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ls_ch = 0;
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}
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for(sl_num = 0; sl_num < numslaves; sl_num++)
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{
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raw_data0 = priv->pruicss_xchg->pos_data_res[sl_num].raw_data[ch].pos_data_word0;
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raw_data1 = priv->pruicss_xchg->pos_data_res[sl_num].raw_data[ch].pos_data_word1;
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max = pow(2, priv->single_turn_len[ls_ch][sl_num]);
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if((priv->data_len[ls_ch][sl_num] + BISSC_POS_CRC_LEN + BISSC_EW_LEN) <= 32)
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{
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priv->raw_data = (uint64_t) raw_data0;
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priv->enc_pos_data[ch].position[sl_num] = (uint64_t) (raw_data0 >> (BISSC_POS_CRC_LEN + BISSC_EW_LEN));
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priv->enc_pos_data[ch].ew[sl_num] = ((raw_data0 >> (BISSC_POS_CRC_LEN )) & 0x03);
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priv->enc_pos_data[ch].num_of_turns[sl_num] = priv->enc_pos_data[ch].position[sl_num] >> priv->single_turn_len[ls_ch][sl_num];
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priv->enc_pos_data[ch].angle[sl_num] = (float)(priv->enc_pos_data[ch].position[sl_num] & (max - 1)) / max * (float)360;
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priv->enc_pos_data[ch].rcv_crc[sl_num] = raw_data0 & 0x3F;
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priv->enc_pos_data[ch].otf_crc[sl_num] = priv->pruicss_xchg->pos_data_res[sl_num].pos_data_otf_crc[ch];
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priv->pd_crc_err_cnt[ch][sl_num] = priv->pruicss_xchg->pos_data_res[sl_num].pd_crc_err_cnt[ch];
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}
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else
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{
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shift = ((priv->data_len[ls_ch][sl_num] + BISSC_POS_CRC_LEN + BISSC_EW_LEN) - 32);
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priv->raw_data = (uint64_t) raw_data0 << shift | raw_data1;
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priv->enc_pos_data[ch].position[sl_num] = (uint64_t) (priv->raw_data >> (BISSC_POS_CRC_LEN + BISSC_EW_LEN));
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priv->enc_pos_data[ch].ew[sl_num] = ((priv->raw_data >> (BISSC_POS_CRC_LEN )) & 0x03);
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priv->enc_pos_data[ch].num_of_turns[sl_num] = priv->enc_pos_data[ch].position[sl_num] >> priv->single_turn_len[ls_ch][sl_num];
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priv->enc_pos_data[ch].angle[sl_num] = (float)(priv->enc_pos_data[ch].position[sl_num] & (max - 1)) / max * (float)360;
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priv->enc_pos_data[ch].rcv_crc[sl_num] = priv->raw_data & 0x3F;
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priv->enc_pos_data[ch].otf_crc[sl_num] = priv->pruicss_xchg->pos_data_res[sl_num].pos_data_otf_crc[ch];
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priv->pd_crc_err_cnt[ch][sl_num] = priv->pruicss_xchg->pos_data_res[sl_num].pd_crc_err_cnt[ch];
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}
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}
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}
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return SystemP_SUCCESS;
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}
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void bissc_config_clock(struct bissc_priv *priv,
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struct bissc_clk_cfg *clk_cfg)
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{
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void *pruicss_cfg = priv->pruicss_cfg;
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struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
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/* Set PRU1_ED_RX_SB_POL polarity bit to 0 for bissc, required for ICSSG (don't care for ICSSM) */
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if(priv->pruicss_slicex)
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{
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HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU1RXCFGREGISTER, ((clk_cfg->rx_div << 16) |
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(clk_cfg->is_ocp << 4) | (clk_cfg->rx_div_attr)));
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HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, clk_cfg->tx_div << 16 |
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(clk_cfg->is_ocp << 4));
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}
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else
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{
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HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU0RXCFGREGISTER, ((clk_cfg->rx_div << 16) |
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(clk_cfg->is_ocp << 4) | (clk_cfg->rx_div_attr)));
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HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER, clk_cfg->tx_div << 16 |
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(clk_cfg->is_ocp << 4));
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}
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if(priv->load_share)
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bissc_enable_load_share_mode(priv);
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/* Clock configuration has changed - Indicate fw to measure the delay again */
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pruicss_xchg->measure_proc_delay = 1;
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}
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void bissc_config_channel(struct bissc_priv *priv, int32_t mask, int32_t totalch)
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{
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struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
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int32_t ch_num;
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pruicss_xchg->channel = mask;
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priv->totalchannels = totalch;
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for(ch_num = 0; ch_num < totalch; ch_num++){
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if((mask & 1) && ch_num == 0)
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priv->channel[ch_num] = 0;
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else if((mask & 2) && (ch_num == 0 || ch_num == 1))
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priv->channel[ch_num] = 1;
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else if((mask & 4))
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priv->channel[ch_num] = 2;
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}
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}
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void bissc_config_load_share(struct bissc_priv *priv, int32_t mask, int32_t loadshare)
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{
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priv->load_share = loadshare;
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bissc_config_primary_core_mask(priv, mask);
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bissc_enable_load_share_mode(priv);
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}
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void bissc_enable_load_share_mode(struct bissc_priv *priv)
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{
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void *pruss_cfg = priv->pruicss_cfg;
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//HW_WR_REG32(0x30026104) |= 0x0800;
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uint32_t rgval;
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if(priv->pruicss_slicex)
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{
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rgval = HW_RD_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER);
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rgval |= CSL_ICSSCFG_EDPRU1TXCFGREGISTER_PRU1_ENDAT_SHARE_EN_MASK;
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HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU1TXCFGREGISTER, rgval);
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}
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else
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{
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rgval = HW_RD_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER);
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rgval |= CSL_ICSSCFG_EDPRU0TXCFGREGISTER_PRU0_ENDAT_SHARE_EN_MASK;
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HW_WR_REG32((uint8_t *)pruss_cfg + CSL_ICSSCFG_EDPRU0TXCFGREGISTER, rgval);
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}
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}
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void bissc_config_primary_core_mask(struct bissc_priv *priv, uint8_t mask)
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{
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switch (mask)
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{
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case 1: /*only channel0 connected*/
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priv->pruicss_xchg->primary_core_mask=0x1;
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break;
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case 2: /*channel1 connected*/
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priv->pruicss_xchg->primary_core_mask=0x2;
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break;
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case 3: /*channel0 and channel1 connected*/
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priv->pruicss_xchg->primary_core_mask=0x1;
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break;
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case 4: /*channel2 connected*/
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priv->pruicss_xchg->primary_core_mask=0x4;
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break;
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case 5: /*channel0 and channel2 connnected*/
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priv->pruicss_xchg->primary_core_mask=0x4;
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break;
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case 6: /*channel1 and channel2 connected*/
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priv->pruicss_xchg->primary_core_mask=0X4;
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break;
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case 7: /*all three channel connected*/
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priv->pruicss_xchg->primary_core_mask=0x4;
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break;
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}
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}
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int32_t bissc_wait_for_fw_initialization(struct bissc_priv *priv, uint32_t timeout, uint8_t mask)
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{
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int32_t i;
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struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
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for(i = 0; i < timeout; i++)
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{
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if(priv->load_share) /* for loadshare mode*/
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{
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switch (mask) {
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case 1: /*channel 0 connected*/
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if((pruicss_xchg->status[0] & 1))
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return SystemP_SUCCESS;
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break;
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case 2: /*channel 1 connected*/
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if((pruicss_xchg->status[1] & 1))
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return SystemP_SUCCESS;
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break;
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case 3: /*channel 0 and 1 connected*/
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if((pruicss_xchg->status[0] & 1) && (pruicss_xchg->status[1] & 1))
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return SystemP_SUCCESS;
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break;
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case 4: /*channel 2 connected*/
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if((pruicss_xchg->status[2] & 1))
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return SystemP_SUCCESS;
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break;
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case 5: /*channel 0 and 2 connnected*/
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if((pruicss_xchg->status[0] & 1) && (pruicss_xchg->status[2] & 1))
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return SystemP_SUCCESS;
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break;
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case 6: /*channel 1 and 2 connected*/
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if((pruicss_xchg->status[1] & 1) && (pruicss_xchg->status[2] & 1))
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return SystemP_SUCCESS;
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break;
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case 7: /*all three channel connected*/
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if((pruicss_xchg->status[0] & 1) && (pruicss_xchg->status[1] & 1) && ( pruicss_xchg->status[2] & 1))
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return SystemP_SUCCESS;
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break;
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}
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ClockP_usleep(1000 * 1);
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}
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else if(pruicss_xchg->status[0] & 1)
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{
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break;
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}
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else
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{
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ClockP_usleep(1000 * 1);
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}
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}
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if(i == timeout)
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{
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return SystemP_FAILURE;
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}
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return SystemP_SUCCESS;
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}
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void bissc_config_clr_cfg0(struct bissc_priv *priv)
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{
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void *pruicss_cfg = priv->pruicss_cfg;
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if(priv->pruicss_slicex)
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{
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HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU1CH0CFG0REGISTER, 0);
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HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU1CH1CFG0REGISTER, 0);
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HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU1CH2CFG0REGISTER, 0);
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}
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else
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{
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HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU0CH0CFG0REGISTER, 0);
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HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU0CH1CFG0REGISTER, 0);
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HW_WR_REG32((uint8_t *)pruicss_cfg + CSL_ICSSCFG_EDPRU0CH2CFG0REGISTER, 0);
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}
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}
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void bissc_config_endat_mode(struct bissc_priv *priv)
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{
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void *pruicss_cfg = priv->pruicss_cfg;
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if(priv->pruicss_slicex)
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{
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HW_WR_REG8((uint8_t *)pruicss_cfg + CSL_ICSSCFG_GPCFG1 + 3, 4);
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}
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else
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{
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HW_WR_REG8((uint8_t *)pruicss_cfg + CSL_ICSSCFG_GPCFG0 + 3, 4);
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}
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}
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int32_t bissc_calc_clock(uint32_t freq, struct bissc_clk_cfg *clk_cfg)
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{
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clk_cfg->rx_div_attr = BISSC_RX_SAMPLE_SIZE;
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if((freq == 1) || (freq == 5))
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{
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freq = freq * 1000 * 1000;
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clk_cfg->tx_div = (BISSC_INPUT_CLOCK_OCP_FREQUENCY / freq) - 1;
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clk_cfg->rx_div = (BISSC_INPUT_CLOCK_OCP_FREQUENCY / (freq * 8)) - 1;
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clk_cfg->is_ocp = 1;
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}
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else if((freq == 2) || (freq == 8))
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{
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freq = freq * 1000 * 1000;
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clk_cfg->tx_div = (BISSC_INPUT_CLOCK_FREQUENCY_UART / freq) - 1;
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clk_cfg->rx_div = (BISSC_INPUT_CLOCK_FREQUENCY_UART / (freq * 8)) - 1;
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clk_cfg->is_ocp = 0;
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}
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else if(freq == 10)
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{
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freq = freq* 1000 * 1000;
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clk_cfg->tx_div = (BISSC_INPUT_CLOCK_OCP_FREQUENCY / freq) - 1;
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clk_cfg->rx_div = (BISSC_INPUT_CLOCK_OCP_FREQUENCY / (freq * 4)) - 1;
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clk_cfg->is_ocp = 1;
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clk_cfg->rx_div_attr = BISSC_RX_SAMPLE_SIZE_10MHZ;
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}
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else
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{
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return SystemP_FAILURE;
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}
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return SystemP_SUCCESS;
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}
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static void bissc_hw_init(struct bissc_priv *priv, uint32_t frequency)
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{
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struct bissc_clk_cfg clk_cfg;
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bissc_calc_clock(frequency, &clk_cfg);
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bissc_config_endat_mode(priv);
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bissc_config_clock(priv, &clk_cfg);
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bissc_config_clr_cfg0(priv);
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}
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struct bissc_priv *bissc_init(PRUICSS_Handle gPruIcssXHandle, int32_t slice, uint32_t frequency)
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{
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struct bissc_pruicss_xchg *pruicss_xchg;
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void *pruicss_cfg;
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pruicss_cfg = (void *)(((PRUICSS_HwAttrs *)(gPruIcssXHandle->hwAttrs))->cfgRegBase);
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if(slice)
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pruicss_xchg = (struct bissc_pruicss_xchg *)((PRUICSS_HwAttrs *)(gPruIcssXHandle->hwAttrs))->pru1DramBase;
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else
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pruicss_xchg = (struct bissc_pruicss_xchg *)((PRUICSS_HwAttrs *)(gPruIcssXHandle->hwAttrs))->pru0DramBase;
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bissc_priv.pruicss_xchg = pruicss_xchg;
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bissc_priv.pruicss_cfg = pruicss_cfg;
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bissc_priv.pruicss_slicex = slice;
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bissc_hw_init(&bissc_priv, frequency);
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return &bissc_priv;
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}
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void bissc_update_max_proc_delay(struct bissc_priv *priv, uint32_t frequency)
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{
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struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
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pruicss_xchg->fifo_bit_idx = 4; /* 8x over clock - middle bit*/
|
|
if(frequency == 1)
|
|
pruicss_xchg->max_proc_delay = BISSC_MAX_PROC_DELAY_1MHZ;
|
|
else if(frequency == 2)
|
|
pruicss_xchg->max_proc_delay = BISSC_MAX_PROC_DELAY_2MHZ;
|
|
else if(frequency == 5)
|
|
pruicss_xchg->max_proc_delay = BISSC_MAX_PROC_DELAY_5MHZ;
|
|
else if(frequency == 8)
|
|
pruicss_xchg->max_proc_delay = BISSC_MAX_PROC_DELAY_8MHZ;
|
|
else if(frequency == 10)
|
|
{
|
|
pruicss_xchg->max_proc_delay = BISSC_MAX_PROC_DELAY_10MHZ;
|
|
pruicss_xchg->fifo_bit_idx = 2; /* 4x over clock - middle bit*/
|
|
}
|
|
}
|
|
|
|
int32_t bissc_wait_measure_proc_delay(struct bissc_priv *priv, uint32_t timeout)
|
|
{
|
|
int32_t i;
|
|
struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
|
|
for(i = 0; i < timeout; i++)
|
|
{
|
|
if(pruicss_xchg->measure_proc_delay & 1)
|
|
{
|
|
break;
|
|
}
|
|
else
|
|
{
|
|
ClockP_usleep(1000);
|
|
}
|
|
}
|
|
if(i == timeout)
|
|
{
|
|
return SystemP_FAILURE;
|
|
}
|
|
return SystemP_SUCCESS;
|
|
}
|
|
|
|
void bissc_set_default_initialization(struct bissc_priv *priv, uint32_t frequency, uint64_t icssgclk)
|
|
{
|
|
int8_t pru_num, totalprus, ls_ch;
|
|
struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
|
|
/* Initialize parameters to default values */
|
|
if(priv->load_share)
|
|
totalprus = priv->totalchannels;
|
|
else
|
|
totalprus = 1;
|
|
for( pru_num = 0; pru_num < totalprus; pru_num++)
|
|
{
|
|
if(priv->load_share)
|
|
ls_ch = priv->channel[pru_num];
|
|
else
|
|
ls_ch = 0;
|
|
pruicss_xchg->enc_len[ls_ch].data_len[0] = BISSC_POS_DATA_LEN_DEFAULT;
|
|
priv->data_len[ls_ch][0] = BISSC_POS_DATA_LEN_DEFAULT;
|
|
priv->single_turn_len[ls_ch][0] = BISSC_POS_DATA_LEN_DEFAULT;
|
|
pruicss_xchg->enc_len[ls_ch].num_slaves = 1;
|
|
priv->num_slaves[ls_ch] = 1;
|
|
priv->multi_turn_len[ls_ch][0] = 0;
|
|
pruicss_xchg->ctrl_cmd[ls_ch] = 0;
|
|
}
|
|
pruicss_xchg->pos_crc_len = BISSC_POS_CRC_LEN;
|
|
pruicss_xchg->ctrl_cmd_crc_len = BISSC_CTRL_CMD_CRC_LEN;
|
|
pruicss_xchg->rx_clk_freq = frequency;
|
|
bissc_update_max_proc_delay(priv, frequency);
|
|
pruicss_xchg->delay_40us = ((icssgclk*40)/1000000);
|
|
pruicss_xchg->delay_100ms = (icssgclk / 10); /*((icssgclk*100000) / 1000000)*/
|
|
pruicss_xchg->icssg_clk = icssgclk;
|
|
pruicss_xchg->valid_bit_idx = 24;
|
|
pruicss_xchg->measure_proc_delay = 1;
|
|
pruicss_xchg->execution_state[0] = 0;
|
|
pruicss_xchg->execution_state[1] = 0;
|
|
pruicss_xchg->execution_state[2] = 0;
|
|
}
|
|
|
|
void bissc_update_data_len(struct bissc_priv *priv, uint32_t single_turn_len[], uint32_t multi_turn_len[], int32_t pru_num)
|
|
{
|
|
struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
|
|
uint32_t sl_num, ls_ch;
|
|
if(priv->load_share)
|
|
ls_ch = priv->channel[pru_num];
|
|
else
|
|
ls_ch = 0;
|
|
for( sl_num = 0; sl_num < NUM_SLAVE_MAX; sl_num++)
|
|
{
|
|
if(single_turn_len[sl_num])
|
|
{
|
|
priv->single_turn_len[ls_ch][sl_num] = single_turn_len[sl_num];
|
|
priv->multi_turn_len[ls_ch][sl_num] = multi_turn_len[sl_num];
|
|
priv->data_len[ls_ch][sl_num] = single_turn_len[sl_num] + multi_turn_len[sl_num];
|
|
pruicss_xchg->enc_len[ls_ch].data_len[sl_num] = single_turn_len[sl_num] + multi_turn_len[sl_num];
|
|
priv->num_slaves[ls_ch]++;
|
|
}
|
|
}
|
|
pruicss_xchg->enc_len[0].num_slaves = priv->num_slaves[0];
|
|
pruicss_xchg->enc_len[1].num_slaves = priv->num_slaves[1];
|
|
pruicss_xchg->enc_len[2].num_slaves = priv->num_slaves[2];
|
|
}
|
|
|
|
int32_t bissc_set_ctrl_cmd_and_process(struct bissc_priv *priv, uint32_t ctrl_cmd[])
|
|
{
|
|
struct bissc_pruicss_xchg *pruicss_xchg = priv->pruicss_xchg;
|
|
pruicss_xchg->ctrl_cmd[0] = ctrl_cmd[0];
|
|
pruicss_xchg->ctrl_cmd[1] = ctrl_cmd[1];
|
|
pruicss_xchg->ctrl_cmd[2] = ctrl_cmd[2];
|
|
int32_t ch = 0, ch_num;
|
|
if(priv->load_share){
|
|
pruicss_xchg->ctrl_cmd_status[0] = (pruicss_xchg->channel & 0x1)?1:0;
|
|
pruicss_xchg->ctrl_cmd_status[1] = (pruicss_xchg->channel & 0x2)?1:0;
|
|
pruicss_xchg->ctrl_cmd_status[2] = (pruicss_xchg->channel & 0x4)?1:0;
|
|
while(pruicss_xchg->ctrl_cmd_status[0] + pruicss_xchg->ctrl_cmd_status[1] + pruicss_xchg->ctrl_cmd_status[2])
|
|
{
|
|
if(bissc_command_process(priv) < 0)
|
|
{
|
|
return SystemP_FAILURE;
|
|
}
|
|
ClockP_usleep(1000);
|
|
}
|
|
}
|
|
else{
|
|
pruicss_xchg->ctrl_cmd_status[0] = 1;
|
|
while(pruicss_xchg->ctrl_cmd_status[0] & 1)
|
|
{
|
|
if(bissc_command_process(priv) < 0)
|
|
{
|
|
return SystemP_FAILURE;
|
|
}
|
|
ClockP_usleep(1000);
|
|
}
|
|
}
|
|
/*supplying 2 extra cycles for ctrl communication stop bit */
|
|
bissc_command_process(priv);
|
|
ClockP_usleep(1000);
|
|
bissc_command_process(priv);
|
|
ClockP_usleep(1000);
|
|
for(ch_num = 0; ch_num < priv->totalchannels; ch_num++)
|
|
{
|
|
ch = priv->channel[ch_num];
|
|
priv->enc_ctrl_data[ch].cmd_result = pruicss_xchg->ctrl_res[ch].ctrl_cds_res;
|
|
priv->enc_ctrl_data[ch].cmd_rcv_crc = pruicss_xchg->ctrl_res[ch].ctrl_rcvd_crc;
|
|
priv->enc_ctrl_data[ch].cmd_otf_crc = pruicss_xchg->ctrl_res[ch].ctrl_otf_crc;
|
|
priv->ctrl_crc_err_cnt[ch] = pruicss_xchg->ctrl_res[ch].ctrl_crc_err_cnt;
|
|
}
|
|
return SystemP_SUCCESS;
|
|
}
|