206f344bd1
remove motor_control folder from the repository Fixes: PINDSW-5635 Signed-off-by: Naresh A <nareshk@ti.com>
104 lines
5.3 KiB
NASM
104 lines
5.3 KiB
NASM
;
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; Copyright (c) 2023, Texas Instruments Incorporated
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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;
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; * Neither the name of Texas Instruments Incorporated nor the names of
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; its contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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; EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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.cdecls C,NOLIST
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%{
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#include "icssg_sddf.h"
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%}
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.include "sddf_cfg.h"
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; Initial FW register values
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; SDDF_EN=0, PRU_ID=uninitialized
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INIT_SDDF_CTRL .set (SDDF_EN << SDDF_CTRL_BF_SDDF_EN_SHIFT) | (PRU_ID << SDDF_CTRL_BF_PRU_ID_SHIFT)
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; SDDF_EN_ACK=0, PRU_ID_ACK=uninitialized
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INIT_SDDF_STAT .set (SDDF_EN_ACK << SDDF_STAT_BF_SDDF_EN_ACK_SHIFT) | (PRU_ID_ACK << SDDF_STAT_BF_PRU_ID_ACK_SHIFT)
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; IEP0 default increment=1
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INIT_IEP_CFG .set (IEP_DEFAULT_INC << IEP_CFG_BF_IEP_DEFAULT_INC_SHIFT)
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; IEP0 CMP0 count to simulate EPWM (FOC loop) period:
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; - IEP frequency = 300 MHz
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; - IEP Default Increment = 1
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; - Simulated EPWM frequency = 8e3
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; CMP0 = 300e6/1/8e3 = 37500 = 0x927C
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; CMP3 = 300e6/16e3 = 18,750 = 0x493E
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INIT_IEP_CFG_CMP0_CNT_EPWM_PRD .set (CMP0_CNT_EPWM_PRD << IEP_CFG_BF_CMP0_CNT_EPWM_PRD_SHIFT)
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; SD Ch0 ID=0, Ch1 ID=1, Ch2 ID=2
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INIT_SDDF_CFG_SD_CH_ID .set (SD_CH0_ID << SDDF_CFG_BF_SD_CH0_ID_SHIFT) | (SD_CH1_ID << SDDF_CFG_BF_SD_CH1_ID_SHIFT) | (SD_CH2_ID << SDDF_CFG_BF_SD_CH2_ID_SHIFT)
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; SD_PRD_CLOCKS=10 => 20 MHz SD clock, SD_CLK_INV==0 => No clock inversion
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INIT_SDDF_CFG_SD_CLK .set (SD_PRD_CLOCKS << SDDF_CFG_SD_CLK_BF_SD_PRD_CLOCKS_SHIFT) | (SD_CLK_INV << SDDF_CFG_SD_CLK_BF_SD_CLK_INV_SHIFT)
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; SD OC OSR=(13+1)=14
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INIT_SDDF_CFG_OSR .set (OC_OSR << SDDF_CFG_OC_OSR_BF_OSR_SHIFT)
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; SD OC positive threshold = (OC OSR)^(OC SINC ORDER) = 14^3 = 2744
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INIT_SDDF_CFG_OC_POS_THR .set (OC_POS_THR << SDDF_CFG_OC_POS_THR_SHIFT)
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; SD OC negative threshold = 1
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INIT_SDDF_CFG_OC_NEG_THR .set (OC_NEG_THR << SDDF_CFG_OC_NEG_THR_SHIFT)
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; For SD samp freq==20e6, OSR==64, EPWM (FOC) loop freq = 8e3, sddf_setup_time=0 (TBD) &
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; IEP freq = 300e6, IEP counter increment=1:
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; (1/2*(1/8e3) - 3/2*(64/20e6) - 0)*300e6*1 = 17310
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; ()
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;
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;for 16KHz (1/2*(1/16e3)-3/2*(64/20e6)-0)*300e6 = 7935
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;for
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INIT_SDDF_CFG_TRIG_SAMP_TIME .set (TRIG_SAMP_TIME << SDDF_CFG_TRIG_SAMP_TIME_BF_TRIG_SAMP_TIME_SHIFT)
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; Generate 3 NC samples after trigger
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INIT_SDDF_CFG_TRIG_SAMP_CNT .set (TRIG_SAMP_CNT << SDDF_CFG_TRIG_SAMP_CNT_BF_TRIG_SAMP_CNT_SHIFT)
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; IEP0 counts in NC sampling period:
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; - IEP0 count =
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; (NC OSR * SD clock period)*(IEP0 frequency * IEP default count) =
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; (NC OSR * IEP0 frequency * IEP default count)/(SD clock frequency) =
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; 64*300e6*1/20e6 = 960
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; for NC OSR = 128
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; 128*15 = 1920
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; 256*15 = 3840
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INIT_SDDF_CFG_NC_PRD_IEP_CNT .set (NC_PRD_IEP_CNT << SDDF_CFG_NC_PRD_IEP_CNT_SHIFT)
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INIT_SDDF_CFG_OUT_SAMP_BUF .set (NC_OUT_SAMP_BUF << SDDF_CFG_NC_OUT_SAMP_BUF_BF_NC_OUT_SAMP_BUF_SHIFT)
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; SDDF Firmware Registers
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.sect ".fwRegs"
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.retain ".fwRegs"
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.retainrefs ".fwRegs"
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.byte INIT_SDDF_CTRL
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.byte INIT_SDDF_STAT
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.byte INIT_IEP_CFG
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.byte 0 ; RESERVED
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.word INIT_IEP_CFG_CMP0_CNT_EPWM_PRD
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.word INIT_SDDF_CFG_SD_CH_ID
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.short INIT_SDDF_CFG_SD_CLK
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.byte INIT_SDDF_CFG_OSR
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.byte 0 ; RESERVED
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.short INIT_SDDF_CFG_OC_POS_THR
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.short INIT_SDDF_CFG_OC_NEG_THR
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.word INIT_SDDF_CFG_TRIG_SAMP_TIME
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.short INIT_SDDF_CFG_TRIG_SAMP_CNT
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.short INIT_SDDF_CFG_NC_PRD_IEP_CNT
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.word INIT_SDDF_CFG_OUT_SAMP_BUF
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