198 lines
5.5 KiB
C
198 lines
5.5 KiB
C
/*
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* Copyright (C) 2023 Texas Instruments Incorporated
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _EPWM_DRV_AUX_H_
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#define _EPWM_DRV_AUX_H_
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#include <stdint.h>
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#include <drivers/hw_include/hw_types.h>
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#include <drivers/epwm.h>
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/* Write EPWM CMPA */
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static inline void writeCmpA(
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uint32_t baseAddr,
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uint32_t cmpVal
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)
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{
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HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPA), PWMSS_EPWM_CMPA,
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(uint16_t)cmpVal);
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}
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/* Write EPWM CMPB */
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static inline void writeCmpB(
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uint32_t baseAddr,
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uint32_t cmpVal
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)
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{
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HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPB), PWMSS_EPWM_CMPB,
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(uint16_t)cmpVal);
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}
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/* Write EPWM CMPA/CMPB */
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static inline void writeCmpAB(
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uint32_t baseAddr,
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uint32_t cmpAVal,
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uint32_t cmpBVal
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)
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{
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/* Write CMPA */
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HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPA), PWMSS_EPWM_CMPA,
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(uint16_t)cmpAVal);
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/* Write CMPB */
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HW_WR_FIELD16((baseAddr + PWMSS_EPWM_CMPB), PWMSS_EPWM_CMPB,
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(uint16_t)cmpBVal);
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}
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/* Configure Output ChannelA AQ Zero */
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static inline void cfgOutChAAqZero(
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uint32_t baseAddr,
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uint32_t zeroAction
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)
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{
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uint32_t regVal = 0U;
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regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA);
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HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_ZRO, zeroAction);
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HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal);
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}
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/* Configure Output ChannelA AQ CMPA Up */
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static inline void cfgOutChAAqCAU(
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uint32_t baseAddr,
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uint32_t cmpAUpAction
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)
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{
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uint32_t regVal = 0U;
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regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA);
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HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CAU, cmpAUpAction);
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HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal);
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};
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/* Configure Output ChannelA AQ CMPA Down */
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static inline void cfgOutChAAqCAD(
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uint32_t baseAddr,
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uint32_t cmpADownAction
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)
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{
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uint32_t regVal = 0U;
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regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA);
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HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CAD, cmpADownAction);
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HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal);
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}
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/* Configure Output ChannelB AQ Zero */
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static inline void cfgOutChBAqZero(
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uint32_t baseAddr,
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uint32_t zeroAction
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)
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{
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uint32_t regVal = 0U;
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regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLB);
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HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLB_ZRO, zeroAction);
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HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLB), (uint16_t)regVal);
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}
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/* Configure Output ChannelA AQ CMPB Up */
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static inline void cfgOutChAAqCBU(
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uint32_t baseAddr,
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uint32_t cmpBUpAction
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)
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{
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uint32_t regVal = 0U;
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regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_AQCTLA);
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HW_SET_FIELD32(regVal, PWMSS_EPWM_AQCTLA_CBU, cmpBUpAction);
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HW_WR_REG16((baseAddr + PWMSS_EPWM_AQCTLA), (uint16_t)regVal);
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}
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/* Write TB Period */
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static inline void writeTbPrd(
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uint32_t baseAddr,
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uint32_t tbPeriodCount
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)
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{
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HW_WR_REG16((baseAddr + PWMSS_EPWM_TBPRD), (uint16_t)tbPeriodCount);
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}
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/* Write TB Phase */
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static inline void writeTbPhase(
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uint32_t baseAddr,
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uint32_t tbPhsValue
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)
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{
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HW_WR_REG16((baseAddr + PWMSS_EPWM_TBPHS), (uint16_t)tbPhsValue);
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}
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/* Write TBCTL HSPDIV & CLKDIV */
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static inline void writeTbClkDiv(
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uint32_t baseAddr,
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uint32_t hspClkDiv,
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uint32_t clkDiv
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)
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{
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uint32_t regVal = 0U;
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regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_TBCTL);
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HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_CLKDIV, clkDiv);
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HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_HSPCLKDIV, hspClkDiv);
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HW_WR_REG16((baseAddr + PWMSS_EPWM_TBCTL), (uint16_t)regVal);
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}
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/* Write TBCTL CTRMODE */
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static inline void writeTbCtrMode(
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uint32_t baseAddr,
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uint32_t ctrMode
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)
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{
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uint32_t regVal = 0U;
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regVal = HW_RD_REG16(baseAddr + PWMSS_EPWM_TBCTL);
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HW_SET_FIELD32(regVal, PWMSS_EPWM_TBCTL_CTRMODE, ctrMode);
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HW_WR_REG16((baseAddr + PWMSS_EPWM_TBCTL), (uint16_t)regVal);
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}
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/* Configure PWM Time base counter Frequency/Period */
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void tbPwmFreqCfg(
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uint32_t baseAddr,
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uint32_t tbClk,
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uint32_t pwmFreq,
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uint32_t counterDir,
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uint32_t enableShadowWrite,
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uint32_t *pPeriodCount
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);
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#endif /* _EPWM_DRV_AUX_H_ */
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