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	.include "memory.inc"
	.include "defines.inc"
	.include "macros.inc"

	.sect	".text"
	.global update_events
	.global demp_data_symbols
	.global calc_acc_crc
	.global calc_16bit_crc
	.global load_code

;--------------------------------------------------------------------------------------------------
;Function: update_events (RET_ADDR1)
;Updates event register and generates interrupts if necessary
; 9 cycles
;input:
;	REG_FNC.b0: event number
;output:
;modifies:
;--------------------------------------------------------------------------------------------------
update_events:
;read events and masks
	lbco		&REG_TMP0, MASTER_REGS_CONST, EVENT_H, 4
	set		REG_TMP0.w0, REG_TMP0.w0, REG_FNC.b0
;save events
	sbco		&REG_TMP0.w0, MASTER_REGS_CONST, EVENT_H, 2
	qbbc		update_events_no_int, REG_TMP0.w2, REG_FNC.b0
;generate interrupt
	ldi		r31.w0, PRU0_ARM_IRQ
update_events_no_int:
	RET1
;--------------------------------------------------------------------------------------------------
;Function: calc_16bit_crc (RET_ADD1)
;This function checks the crc for the acceleration channel (polynomial is x^5 + x^2 + 1)
;11*REG_FNC.b2+3 cycles -> 69 cycles for 6 bytes data
;input:
;	REG_FNC.b0: num bytes
;	r1.b0: pointer to register + 1 byte, counting down from there
;output:
;	REG_FNC.w0: 16 bit CRC
;modifies:
;	REG_TMP0, REG_FNC, r1
;--------------------------------------------------------------------------------------------------
calc_16bit_crc:
	ldi		REG_TMP2, (LUT_CRC16+PDMEM00)
	mov		REG_TMP0.b2, REG_FNC.b0
	ldi		REG_FNC.w0, 0
calc_16bit_crc_loop:
	ldi		REG_TMP0.w0, 0
	mvib		REG_TMP0.b0, *--r1.b0
	xor		REG_TMP0.b0, REG_FNC.b1, REG_TMP0.b0
	lsl		REG_TMP0.w0, REG_TMP0.w0, 1
	lbbo		&REG_TMP0.w0, REG_TMP2, REG_TMP0.w0, 2
	lsl		REG_FNC.w0, REG_FNC.w0, 8
	xor		REG_FNC.w0, REG_TMP0.w0, REG_FNC.w0
	sub		REG_TMP0.b2, REG_TMP0.b2, 1
	qblt		calc_16bit_crc_loop, REG_TMP0.b2, 0
;CRC_L is flipped
	xor		REG_FNC.b0, REG_FNC.b0, 0xff
	RET1