%%{
    let options = args.options;

    let stackSize = 0x10000;
    let heapSize =  0x20000;

    let isSingleCore = true;
    let useDdr = true;
    let addrBaseDdr = 0x80000000;
    let codeDataSizeDdr = 0x1000000;

    /* if no options given use defaults */
    if(options && options.stackSize)
        stackSize = options.stackSize;
    if(options && options.heapSize)
        heapSize = options.heapSize;

    if(isSingleCore == true) {
        codeDataAddrDdr = addrBaseDdr;
        codeDataSizeDdr = 0x1000000 * 2;
    }
    else {
        if(args.project.cpu == "a53ss0-0")
        {
            codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*0;
        }
        if(args.project.cpu == "a53ss0-1")
        {
            codeDataAddrDdr = addrBaseDdr + codeDataSizeDdr*1;
        }
    }

    if(options && options.addrBaseDdr)
        addrBaseDdr = options.addrBaseDdr;
    if(options && options.codeDataSizeDdr)
        codeDataSizeDdr = options.codeDataSizeDdr;

%%}

ENTRY(_c_int00)

__TI_STACK_SIZE = `stackSize`;
__TI_HEAP_SIZE = `heapSize`;

MEMORY
{
    % if(useDdr) {
    DDR : ORIGIN =  0x`(codeDataAddrDdr).toString(16).toUpperCase()`, LENGTH = 0x`(codeDataSizeDdr).toString(16).toUpperCase()`
    % }

    /* shared memory segments */
    /* On A53,
     * - make sure there is a MMU entry which maps below regions as non-cache
     */
    USER_SHM_MEM            : ORIGIN = 0x701D0000, LENGTH = 0x80
    LOG_SHM_MEM             : ORIGIN = 0x701D0000 + 0x80, LENGTH = 0x00004000 - 0x80
    RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D4000, LENGTH = 0x0000C000
}

SECTIONS {

    .vecs : {} > DDR
    .text : {} > DDR
    .rodata : {} > DDR

    .data : ALIGN (8) {
        __data_load__ = LOADADDR (.data);
        __data_start__ = .;
        *(.data)
        *(.data*)
        . = ALIGN (8);
        __data_end__ = .;
    } > DDR

    /* General purpose user shared memory, used in some examples */
    .bss.user_shared_mem (NOLOAD) : { KEEP(*(.bss.user_shared_mem)) } > USER_SHM_MEM
    /* this is used when Debug log's to shared memory are enabled, else this is not used */
    .bss.log_shared_mem  (NOLOAD) : { KEEP(*(.bss.log_shared_mem)) } > LOG_SHM_MEM
    /* this is used only when IPC RPMessage is enabled, else this is not used */
    .bss.ipc_vring_mem   (NOLOAD) : { KEEP(*(.bss.ipc_vring_mem)) } > RTOS_NORTOS_IPC_SHM_MEM

    .bss : {
        __bss_start__ = .;
        *(.bss)
        *(.bss.*)
        . = ALIGN (8);
        *(COMMON)
        __bss_end__ = .;
        . = ALIGN (8);
    } > DDR

    .heap (NOLOAD) : {
        __heap_start__ = .;
        KEEP(*(.heap))
        . = . + __TI_HEAP_SIZE;
        __heap_end__ = .;
    } > DDR

    .stack (NOLOAD) : ALIGN(16) {
        __TI_STACK_BASE = .;
        KEEP(*(.stack))
        . = . + __TI_STACK_SIZE;
    } > DDR

}