From dd0d2e356bc673873cf49edc6fe0917add991ae3 Mon Sep 17 00:00:00 2001 From: Dhaval Khandla Date: Tue, 22 Aug 2023 13:14:18 +0530 Subject: [PATCH] am64x/am243x: hdsl: Make FREL/FRES bit set sticky in EVENT/EVENT_S - Firmware should not clear these bits in EVENT/EVENT_S registers - Update the version to 0.3 Fixes: PINDSW-6526 Signed-off-by: Dhaval Khandla --- .../position_sense/hdsl/firmware/defines.inc | 2 +- .../firmware/hdsl_master_icssg_300_mhz_bin.h | 58 +++++++++---------- .../hdsl/firmware/transport.asm | 13 +---- 3 files changed, 29 insertions(+), 44 deletions(-) diff --git a/source/position_sense/hdsl/firmware/defines.inc b/source/position_sense/hdsl/firmware/defines.inc index 14f9452..179f40a 100644 --- a/source/position_sense/hdsl/firmware/defines.inc +++ b/source/position_sense/hdsl/firmware/defines.inc @@ -35,7 +35,7 @@ FIRMWARE_VERSION_CODING .set 0x1 ; bit5..4 major number FIRMWARE_VERSION_MAJOR .set 0x0 ; bit3..0 minor number -FIRMWARE_VERSION_MINOR .set 0x2 +FIRMWARE_VERSION_MINOR .set 0x3 ICSS_FIRMWARE_RELEASE .set ((FIRMWARE_VERSION_CODING << 6) | (FIRMWARE_VERSION_MAJOR << 4) | (FIRMWARE_VERSION_MINOR << 0)) diff --git a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h index 79e8506..aecf04b 100644 --- a/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h +++ b/source/position_sense/hdsl/firmware/hdsl_master_icssg_300_mhz_bin.h @@ -55,7 +55,7 @@ */ const unsigned int Hiperface_DSL2_0[]= { -0x21067a00, +0x21067400, 0x24000125, 0x2eff818f, 0x24001d8d, @@ -151,7 +151,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0xd104ff00, 0xd703ffff, 0x24002f1e, -0x23046b9d, +0x2304659d, 0x05014545, 0x4f0045d2, 0x24000070, @@ -530,7 +530,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x511f0d03, 0x51190d02, 0x79000003, -0x230641d1, +0x23063bd1, 0x7900001a, 0xd104ff00, 0xd703ffff, @@ -637,7 +637,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1f00c0c0, 0x1f008181, 0x81505880, -0x2104f500, +0x2104ef00, 0x91042580, 0xd708e0ff, 0x91042580, @@ -769,7 +769,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x813a188d, 0x24000019, 0x79000002, -0x2304d5d1, +0x2304cfd1, 0x10535300, 0x10333320, 0x10131340, @@ -932,7 +932,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24003001, 0xd1066b0e, 0x2400010d, -0x23066cd1, +0x230666d1, 0x68ab8d45, 0x13803b3b, 0x913d1880, @@ -945,7 +945,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81531800, 0x7900003b, 0x2400020d, -0x23066cd1, +0x230666d1, 0x688b8d38, 0x8137184b, 0x13803b3b, @@ -988,7 +988,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x1d09c4c4, 0x2400040d, 0x24003001, -0x23066cd1, +0x230666d1, 0x15ff8d9c, 0x69005c34, 0x51009c33, @@ -1051,7 +1051,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x7900005d, +0x79000057, 0x91351800, 0xc9060007, 0x1d060000, @@ -1059,7 +1059,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x24001e31, 0x2eff829a, 0x1d09c4c4, -0x79000055, +0x7900004f, 0xc909c41c, 0x05041b1b, 0x490c1b06, @@ -1067,7 +1067,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x110f3131, 0x69001b02, 0x1d09c4c4, -0x7900004d, +0x79000047, 0xc9077a08, 0x905a1831, 0xc9021b03, @@ -1087,12 +1087,9 @@ const unsigned int Hiperface_DSL2_0[]= { 0x14809a9a, 0x69101b02, 0x15ff1a1a, -0x79000039, +0x79000033, 0x91401800, -0x513f0016, -0x913d1840, -0x1d004040, -0x813d1840, +0x513f0013, 0x91531840, 0x1d004040, 0x81531840, @@ -1110,15 +1107,12 @@ const unsigned int Hiperface_DSL2_0[]= { 0x2400201b, 0x2400403b, 0x1f09c4c4, -0x79000022, +0x7900001f, 0x912c1800, -0xc9000020, +0xc900001d, 0x1d000000, 0x812c1800, 0x1f09c4c4, -0x91041880, -0x1d098080, -0x81041880, 0x91511800, 0x1d010000, 0x81511800, @@ -1229,7 +1223,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x108787c7, 0x04c98087, 0x108080c9, -0x2304bcd1, +0x2304b6d1, 0x108b8b9d, 0x91aa1800, 0x1f018000, @@ -1249,7 +1243,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x108787c7, 0x04c98087, 0x108080c9, -0x2304bcd1, +0x2304b6d1, 0x91983880, 0x10eeeee1, 0x24000061, @@ -1338,7 +1332,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x81080580, 0x24001fc0, 0x810605c0, -0x24004200, +0x24004300, 0x810b1800, 0x81441800, 0x2eff8383, @@ -1372,7 +1366,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x9101185b, 0x51005b0e, 0x7900000d, -0x230629d1, +0x230623d1, 0x91dc388c, 0x240000e2, 0x91e21882, @@ -1380,7 +1374,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x100c0c2a, 0x106c6c4a, 0x102c2c6a, -0x230629d1, +0x230623d1, 0x0b01e2e2, 0x0501e2e2, 0x4f00e2ff, @@ -1503,7 +1497,7 @@ const unsigned int Hiperface_DSL2_0[]= { 0x0b077200, 0x12001313, 0x0901f2f2, -0x230635d1, +0x23062fd1, 0x510e6506, 0x6f010df6, 0x10656546, @@ -1540,16 +1534,16 @@ const unsigned int Hiperface_DSL2_0[]= { 0xd703ffff, 0x24001b8d, 0x23016a9d, -0x2305fb9d, -0x230635d1, +0x2305f59d, +0x23062fd1, 0x6f010deb, 0x05012525, 0x4f0025f8, 0x24001025, 0x24001c8d, 0x23016a9d, -0x2305fb9d, -0x230635d1, +0x2305f59d, +0x23062fd1, 0x6f010dd8, 0x05012525, 0x4f0025fa, @@ -1716,4 +1710,4 @@ const unsigned int Hiperface_DSL2_0[]= { 0x91003c82, 0x1308e2e2, 0x81003c82, -0x2104f500 }; +0x2104ef00 }; diff --git a/source/position_sense/hdsl/firmware/transport.asm b/source/position_sense/hdsl/firmware/transport.asm index e429f11..6819b66 100644 --- a/source/position_sense/hdsl/firmware/transport.asm +++ b/source/position_sense/hdsl/firmware/transport.asm @@ -135,7 +135,6 @@ transport_on_v_frame_dont_update_qm: add REG_TMP1, REG_TMP1, 1 sbco ®_TMP1, MASTER_REGS_CONST, NUM_VERT_ERR0, 4 .endif - ;HALT qba transport_on_v_frame_exit check_for_slave_error_on_v_frame: ;CRC was correct -> add 1 to QM @@ -825,11 +824,7 @@ transport_layer_check_for_new_short_msg: lbco ®_TMP0.b0, MASTER_REGS_CONST, SLAVE_REG_CTRL, 1 qbeq transport_layer_no_short_msg, REG_TMP0.b0, 0x3f -;set short msg channel to busy (reset EVENT_S_FRES) - lbco ®_TMP0.b2, MASTER_REGS_CONST, EVENT_S, 1 - clr REG_TMP0.b2, REG_TMP0.b2, EVENT_S_FRES - sbco ®_TMP0.b2, MASTER_REGS_CONST, EVENT_S, 1 -; Set ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register +; Clear ONLINE_STATUS_1_FRES in ONLINE_STATUS_1 register lbco ®_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 clr REG_TMP0.b2, REG_TMP0.b2, (ONLINE_STATUS_1_FRES-8) sbco ®_TMP0.b2, MASTER_REGS_CONST, (ONLINE_STATUS_1_L), 1 @@ -869,11 +864,7 @@ transport_layer_no_short_msg: sbco ®_TMP0.b0, MASTER_REGS_CONST, PC_CTRL, 1 ;set para channel to busy set H_FRAME.flags, H_FRAME.flags, FLAG_PARA_BUSY -;set long msg channel to busy (reset FREL) - lbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 2 - clr REG_TMP0.w0, REG_TMP0.w0, EVENT_FREL - sbco ®_TMP0, MASTER_REGS_CONST, EVENT_H, 2 -; Set ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register +; Clear ONLINE_STATUS_D_FREL in ONLINE_STATUS_D register lbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1 clr REG_TMP0.b0, REG_TMP0.b0, (ONLINE_STATUS_D_FREL-8) sbco ®_TMP0.b0, MASTER_REGS_CONST, (ONLINE_STATUS_D_L), 1